Laboratory 2:

FINITE STATE MACHINES

HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY

DIGITAL DESIGN LAB – REPORT

Lecturer: Nguyễn Trung Hiếu
Class: CC01
NAME STUDENT ID
Nguyễn Vĩnh Khang 2251021
Bùi Hồ Quang Vũ 2051220

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Digital Design Laboratory (Advanced Program)
 Laboratory 2:
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OBJECTIVES
➢ Getting to know how to describe finite state machine (FSM) using variety styles of
System Verilog code (logic expressions/ behavioral expressions/ shift registers).
➢ Design and implement digital circuits using FSM.
➢ Download the circuit into the FPGA chip and test its functionality.

PREPARATION FOR LAB 2

➢ Finish Pre Lab 2 at home.
➢ Students have to simulate all the exercises in Pre Lab 2 at home. All results (codes,
waveform, RTL viewer, … ) have to be captured and submitted to instructors prior to the
lab session.
If not, students will not participate in the lab and be considered absent this session.

REFERENCE
1. Intel FPGA training

EXPERIMENT 1
Objective: Know how to implement a FSM circuit and download the cicuit into the FPGA chip.

Requirement: Implement a FSM that recognizes two specific sequences of applied input
symbols, namely four consecutive 1s or four consecutive 0s. There is an input w and an output z.
Whenever w = 1 or w = 0 for four consecutive clock pulses the value of z has to be 1; otherwise,
z = 0. Overlapping sequences are allowed, so that if w = 1 for five consecutive clock pulses the
output z will be equal to 1 after the fourth and fifth pulses.

Figure 1 illustrates the required relationship between w and z. And the state diagram for this
FSM is shown in Figure 2.

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Figure 1: Required timing for the output z.

Instruction:

Students derive an FSM circuit that implements this state diagram, including the logic
expressions that feed each of the state flip-flops. Using 9 state flip-flops called y 8, …, y0 and the
one-hot state assignment given in Table 1.

Figure 2: A state diagram for the FSM Table 1: One-hot codes for the FSM

1. Create a new Quartus project for your circuit.

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2. Follow FSM circuit designed in exercise - Pre-Lab 2, write a System Verilog file that
instantiates the nine flip-flops in the circuit and which specifies the logic expressions that
drive the flip-flops input ports.
3. Use the toggle switch SW0 as an active-low synchronous reset input for the FSM, use
SW1 as the w input, and the pushbutton KEY0 as the clock input which is applied
manually. Use the red light LEDR9 as the output z, and assign the state flip-flop outputs
to the red lights LEDR8 to LEDR0.
4. Compile the project, and then download the resulting circuit into the FPGA chip. Test the
functionality of your design by applying the input sequences and observing the output
LEDs. Make sure that the FSM properly transitions between states as displayed on the red
LEDs, and that it produces the correct output values on LEDR9.
5. It is often desirable to set all flip-flop outputs to the value 0 in the reset state. Table 2
shows a modified one-hot state assignment in which the reset state, A, uses all 0s. Create
a modified version of your System Verilog code that implements this state assignment.
Compile your new circuit and test it.

Table 2: Modified one-hot codes for the FSM

Check: Your report has to show two results:

➢ The waveform to prove the circuit works correctly.

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 Laboratory 2:
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➢ The result of RTL viewer.

CODE

module Lab2_Exp1(

input logic clk,

input logic rst,

input logic w,

output logic z,

output logic [8:0] LEDR);

typedef enum logic[8:0]{

A=9'b000000001,

B=9'b000000010,

C=9'b000000100,

D=9'b000001000,

E=9'b000010000,

F=9'b000100000,

G=9'b001000000,

H=9'b010000000,

I=9'b100000000} stateCoding_t;

stateCoding_t preState=A;

stateCoding_t nextState=A;

always_ff@(posedge clk)

begin

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if(rst)

preState <= A;

else

preState <= nextState;

end

always_comb begin

case(preState)

A: begin

if(w==0) nextState <= B;

else nextState <= F;

end

B: begin

if(w==0) nextState <= C;

else nextState <= F;

end

C: begin

if(w==0) nextState <= D;

else nextState <= F;

end

D: begin

if(w==0) nextState <= E;

else nextState <= F;

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end

E: begin

if(w==0) nextState <= E;

else nextState <= F;

end

F: begin

if(w==0) nextState <= B;

else nextState <= G;

end

G: begin

if(w==0) nextState <= B;

else nextState <= H;

end

H: begin

if(w==0) nextState <= B;

else nextState <= I;

end

I: begin

if(w==0) nextState <= B;

else nextState <= I;

end

default nextState=A;

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endcase

end

always_comb

begin

case(preState)

A:z=0;

B:z=0;

C:z=0;

D:z=0;

E:z=1;

F:z=0;

G:z=0;

H:z=0;

I:z=1;

endcase

end

assign LEDR = preState;

endmodule

SIMULATION

https://drive.google.com/file/d/12kZ_Z2t_BD2IETf6qglJN-pferCwvuCr/view?usp=sharing

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EXPERIMENT 2
Objective: Know how to implement a FSM circuit using System Verilog behavioral expressions
and download the cicuit into the FPGA chip..

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Requirement: Implement the FSM given in experiment 1, using another style of System Verilog
code. Use a Verilog CASE statement in a ALWAYS block, and use another ALWAYS block to
instantiate the state flip-flops. You can use a third ALWAYS block or simple assignment
statements to specify the output z. To implement the FSM, use four state flip-flops y3, . . .
, y0 and binary codes, as shown in Table 3.

Table 3: Binary codes for the FSM

Instruction:

1. Create a new Quartus project for your circuit.

2. Use the same switches, pushbuttons, and lights that were used in previous experiments.
3. It is necessary to explicitly tell the Synthesis tool in Quartus that you wish to have the
finite state machine implemented using the state assignment specified in your Verilog
code. If you do not explicitly give this setting to Quartus, the Synthesis tool will
automatically use a state assignment of its own choosing, and it will ignore the state
codes specified in your Verilog code. To make this setting, choose Assignments >
Settings in Quartus, and click on the Compiler Settings item on the left side of the
window, then click on the Advanced Settings (Synthesis) button. As indicated in Figure
3, change the parameter State Machine Processing to the setting User-Encoded.

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Figure 3: Specifying the state assignment method in Quartus.

4. Compile your project.

Examine the circuit produced by Quartus open the RTL Viewer tool. Double-click on the
box shown in the circuit that represents the finite state machine, and determine whether the
state diagram that it shows properly corresponds to the one in Figure 2.

To see the state codes used for your FSM: open the Compilation Report → Analysis
and Synthesis section → State Machines.

5. Download the circuit into the FPGA chip and test its functionality.
6. Change the setting for State Machine Processing from User_Encoded to One-Hot.
Recompile the circuit and then open the report file, select the Analysis and Synthesis
section of the report, and click on State Machines. Compare the state codes shown to
those given in Table 2, and discuss any differences that you observe.

Check: Your report has to show two results:

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➢ The waveform to prove the circuit works correctly.
➢ The result of RTL viewer.
CODE
module Lab2_Exp2(

input logic clk,

input logic rst,
input logic w,
output logic z,
output logic [8:0] LEDR);

typedef enum logic[3:0]{

A=4'b0000,
B=4'b0001,
C=4'b0010,
D=4'b0011,
E=4'b0100,
F=4'b0101,
G=4'b0110,
H=4'b0111,
I=4'b1000} stateCoding_t;
stateCoding_t preState=A;
stateCoding_t nextState=A;
always_ff@(posedge clk)
begin
if(rst)
preState <= A;
else
preState <= nextState;
end
always_comb begin
case(preState)
A: begin
if(w==0) nextState <= B;
else nextState <= F;
end
B: begin

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if(w==0) nextState <= C;
else nextState <= F;
end
C: begin
if(w==0) nextState <= D;
else nextState <= F;
end
D: begin
if(w==0) nextState <= E;
else nextState <= F;
end
E: begin
if(w==0) nextState <= E;
else nextState <= F;
end
F: begin
if(w==0) nextState <= B;
else nextState <= G;
end
G: begin
if(w==0) nextState <= B;
else nextState <= H;
end

H: begin
if(w==0) nextState <= B;
else nextState <= I;
end

I: begin
if(w==0) nextState <= B;
else nextState <= I;
end
default nextState=A;
endcase
end
always_comb

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begin
case(preState)
A:z=0;
B:z=0;
C:z=0;
D:z=0;
E:z=1;
F:z=0;
G:z=0;
H:z=0;
I:z=1;
endcase
end
assign LEDR = preState;
endmodule
SIMULATION
https://drive.google.com/file/d/1f-og4VmVg5ozOvVvIZBtJGDaqKBMCFsO/view?usp=sharing

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EXPERIMENT 3
Objective: Know how to implement sequence detector using shift registers.

Requirement: Create System Verilog code that instantiates two 4-bit shift registers; one is for
recognizing a sequence of four 0s, and the other for four 1s. Include the appropriate logic
expressions in your design to produce the output z.

Shift Register 1s
w Combinational z
circuit
Shift Register 0s
Figure
4: Sequence detector using shift registers.

Instruction:

1. Create a new Quartus project for your circuit.

2. Use the same switches, pushbuttons, and lights that were used in previous experiments.
3. Compile your project. Download the circuit into the FPGA chip and test its functionality.
Observe the behavior of your shift registers and the output z.
❖ Could you use just one 4-bit shift shift register, rather than two? Explain your answer

Check: Your report has to show two results:

➢ The waveform to prove the circuit works correctly.

➢ The result of RTL viewer.

CODE
module Lab2_Exp3(
input logic clk,
input logic rst,
input logic w,
output logic z);
logic [3:0] d_out_0;
logic [3:0] d_out_1;

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shift_right_register zero( .clk(clk), .rst(rst), .d_in(w), .d_out(d_out_0));
shift_right_register one( .clk(clk), .rst(rst), .d_in(w), .d_out(d_out_1));
always_comb
begin
z = ((d_out_0 == 4'b0000) || (d_out_0 == 4'b1111));
end
endmodule
module shift_right_register(
input logic clk,
input logic d_in,
input logic rst,
output logic [3:0] d_out
);

reg [3:0] reg_data;

always@(posedge clk,negedge rst)
begin
if(~rst)
reg_data <= 4'b0000;
else
reg_data <= {d_in, reg_data[3:1]};
end

assign d_out = reg_data;

endmodule
TESTBENCH
`timescale 1ps/1ps
module Lab2_Exp3_tb;

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logic w;
logic z;
logic clk;
logic rst;
Lab2_Exp3 uut( .w(w), .z(z), .clk(clk), .rst(rst), .LEDR(LEDR));
initial
begin
clk = 0;
rst = 0;
w = 0;
#5 w=1;
#10 w=1;
#15 w=1;
#15 w=1;
#20 w=1;
#25 w=0;
end
always
begin
#10 clk=~clk;
end
endmodule
SIMULATION
https://drive.google.com/file/d/1SkhR04V9GbMnOoQ9lRa8nEPA2yOL2ggY/view?usp=sharing

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EXPERIMENT 4
Objective: Know how to implement a digital circuit using an FSM.

Requirement: The Morse code uses patterns of short and long pulses to represent a message.
Each letter is represented as a sequence of dots (a short pulse), and dashes (a long pulse). For
example, the first eight letters of the alphabet have the following representation:
A•—
B—•••
C—•—•
D—••
E•
F ••—•
G——•
H••••
Design and implement a Morse-code encoder circuit using an FSM. The circuit take as input one
of the first eight letters of the alphabet and display the Morse code for it on LEDs.
A high-level schematic diagram of a possible circuit for the Morse-code encoder is shown in
Figure 5.

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Figure 5: High-level schematic diagram for the Morse-code encoder.

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Instruction:

1. Filling this suggested skeleton of the VHDL code:

module part4 (SW, CLOCK_50, KEY, LEDR);

/******************************************************************/
/**** DECLARATIONS ****/
/******************************************************************/

// FSM State Table

always @(…)
begin: state_table
…
end // state_table

// FSM State flip-flops

always @(posedge Clock)

…
// FSM outputs
// turn on the Morse code light in the states below
assign light_on = … ;
// specify when to load the Morse code into the shift register, and length into the counter
assign load_regs = …;
// specify when to shift the Morse code bits and decrement the length counter
assign shift_and_count = …;

/* Create an enable signal that is asserted once every second. */

modulo_counter …;

/* Letter selection */
always @(*)
case (SW)
A_SW: begin morse_code = … ; morse_length = … ; end
…
…

endcase

/* Store the Morse code to be sent in a shift register, and its length in a counter */
always@(posedge CLOCK_50)
begin
/* if Reset = 0 then data = size = 0; otherwise, if load = 1 then data = morse_code and size = morse_length; if shift
= 1 then data[2:0]= data[3:1]) & data[3] = 1'b0 and size = size – 1’b1 */ endmodule

module modulo_counter(…);
…
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endmodule

Page |

2. Create a new Quartus project for your circuit.

3. Use switches SW2 − SW0 and pushbuttons KEY1 − KEY0 as inputs. When a user
presses KEY1, the circuit should display the Morse code for a letter specified by SW 2−0 ,
using a LEDR0 to represent dots, and LEDR1 to represent dashes. Each LED will be on
for half of a second. Pushbutton KEY0 should function as an asynchronous reset.
4. Compile your project. Download the circuit into the FPGA chip and test its functionality.

Check: Your report has to show two results:

➢ The waveform to prove the circuit works correctly.
➢ The result of RTL viewer.

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module lab2_4(
input logic CLOCK_50,
input [2:0] SW,
input logic rst,
output logic [1:0] LEDR,
input logic enable );

logic reset;
logic done;

half_second_counter
counter(.clk(CLOCK_50), .reset(reset), .done(done), .enable(enabl
e));
typedef enum logic[10:0]{
S= 11'b00000000001,
A= 11'b00000000010,
R= 11'b00000000100,
A1= 11'b00000001000,
B= 11'b00000010000,
R1= 11'b00000100000,
B1= 11'b00001000000,
R2= 11'b00010000000,
B2= 11'b00100000000,
R3= 11'b01000000000,
B3= 11'b10000000000

} stateCoding_t;
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stateCoding_t preState=S;
stateCoding_t nextState=S;

always_ff@(posedge CLOCK_50)
begin
if(rst)
preState <= S;
else
preState <= nextState;
end

always_comb begin
nextState = S;
case(preState)
S: begin
if (rst == 1 || enable == 1'b0)
nextState = S;
else if (SW == 3'b000 && enable == 1'b1)
nextState = A;
else if (SW == 3'b001 && enable ==1'b1)
nextState = B;
end

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A: begin
//dot
if (done==0) nextState = A;
else nextState = R;
end
R: begin
nextState = A1;
end
A1: begin
//dash
if (done==0) nextState = A1;
else nextState = S;
end
B: begin
if (done==0) nextState = B;
//dash
else nextState = R1;
end
R1: begin
nextState = B1;
end
B1:
begin
if (done==0) nextState = B1; //dot
else nextState = R2;
end

R2: begin

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nextState = B2;
end
B2:
begin
if (done==0) nextState = B2;
//dot
else nextState = R3;
end
R3: begin
nextState = B3;
end
B3:
begin
if (done==0) nextState = B3;
//dot
else nextState = S;
end

default: nextState = S;
endcase
end
always_comb //reset
begin
reset = 1;
case(preState)
A: reset =0;
R: reset =1;
A1: reset =0;
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B: reset =0;
R1: reset =1;
B1:reset =0;
R2: reset =1;
B2: reset =0;
R3: reset =1;
B3: reset =0;
default: reset = 0;
endcase
end
always_comb
begin
LEDR[0]=0;
case(preState)
A: LEDR[0]=1;
R: LEDR[0]=0;
A1: LEDR[0]=1;
B: LEDR[0]=0;
R1: LEDR[0]=0;
B1:LEDR[0]=1;
R2: LEDR[0]=0;
B2: LEDR[0]=1;
R3: LEDR[0]=0;
B3: LEDR[0]=1;
default: LEDR[0]=0;
endcase
end

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always_comb
begin
LEDR[1]=0;
case(preState)
A: LEDR[1]=0;
R: LEDR[1]=0;
A1: LEDR[1]=1;
B: LEDR[1]=1;
R1: LEDR[1]=0;
B1:LEDR[1]=0;
R2: LEDR[1]=0;
B2: LEDR[1]=0;
R3: LEDR[1]=0;
B3:LEDR[1]=0;
default: LEDR[1] = 0;
endcase
end
endmodule
module half_second_counter(
input logic clk,
input logic reset,
input logic enable,
output logic done
);
localparam HALF_SEC_COUNT = 25_000_000;
reg [25:0] counter = 0; // Correct bit width to hold the counter
value

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always @(posedge clk or posedge reset) begin
if (reset == 1'b1) begin
counter <= 0;
done <= 0;
end
else if (enable == 1'b1) begin
if (counter == HALF_SEC_COUNT - 1) begin
counter <= 0;
done <= 1;
end
else begin
counter <= counter + 1;
done <= 0;
end
end
end

endmodule

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