CMOS Analog Design

Prof. Dr. Bernhard Hoppe

Channel length modulation

CMOS Analog Design 2

Disadvantages of short channel devices:

• Reduction in gain
• Cannot switch off properly due to reduction in VT
• More leakage current in the „off“ condition
• More dependence on transistor variables

CMOS Analog Design 3

Basic Transistor Formulas:

cutoff iD = 0 VGS  VT

 nCox 2 (VGS − VT )VDS − VDS 

W
linear iD = 2
VGS − VT  VDSSAT
2L

W

saturation iD =  n Cox (VGS − VT ) (1 + VDS )
2L
2
 VGS − VT  VDSSAT

VDSSAT = VGS-VT if not otherwise stated in the parameter table

VT = VT 0 +  ( −2F + VSB − −2F )

CMOS Analog Design 4
CMOS amplifiers

CMOS Analog Design 5

Basic principles:

• MOSFET translates variations in its gate-source

voltage to a small signal drain current
• If a resistive load is used, these current variations in
turn produce variations in the output voltage

CMOS Analog Design 6

Amplifier configurations:

1. Common source stage (CS)

2. Source follower or common drain stage (SF)
3. Common gate stage (CG)
4. Cascode stage: cascade of CS and CG stage
5. Differential amplifiers

CMOS Analog Design 7

Common source amplifier configuration (CS):

Small signal model for the

saturation region:

CMOS Analog Design 8

Input – output characteristics:
1. Vin < VTH:
Vout = VDD

2. Vin >= VTH:

M1 is ON
saturation region

3. Vin >= Vout + VTH:

M1 in linear
region

CMOS Analog Design 9

Input – output characteristics:

1. Vin < VTH:

Vout = VDD
2. Vin >= VTH:
= −
1
Vout V DD R D n Cox
W
(Vin − VTH )2

2 L
3. Vin >= Vout + VTH:

Vout
1
= VDD − R D  n Cox
W
2(Vin − VTH ) Vout − Vout
2

2 L

CMOS Analog Design 10

Supressing short channel effects:

• Analog circuits: Lmin of technology is not utilized.

Instead analog circuits use 4...5 times Lmin
• Longer transistor length results in
(1) negligible subthreshold current
(2) small channel length modulation effect
(3) small velocity saturation effect

CMOS Analog Design 11

Deep triode region:

If Vin is high enough to drive M1 into deep triode region,

Vout << 2(Vin - VTH) and from the equivalent circuit
VDD
V out = V DD R on =
R on
+ R D
1 + RD / Ron
RD RD
=
Ron 1
nCox
W
L
(
V in −V T − VDS )
V DD
Vout =
W
1 + n Cox R D (V in −V TH )
L
CMOS Analog Design 12
Small signal gain:
• In deep triode region, we have a voltage divider while in
the saturation region we have the proper amplifier
operation due to the quadratic dependence of the
current:

= −
Vout V DD R D
1
 n Cox
W
(Vin − VTH )2

2 L
• The small signal gain is given as:  Vout
A =
 Vin

= − R D  n Cox
W
(Vin − VTH )
L
= − gmR D
CMOS Analog Design 13
Transconductance gm:
• Small signal parameter
• In saturation,
 ID
gm = VDS fixed
 Vin
=  n Cox
W
(VGS − VTH )
L
W 2 ID
= 2 n Cox I D =
L VGS − VTH
 g m = f (VGS − VTH )

CMOS Analog Design 14

Transconductance gm:

• Thus transconductance gm is dependent on input

voltage!
• Gain A  varies with Vin...Nonlinearity problem for
large signals!

CMOS Analog Design 15

How to maximize the voltage gain?
W VRD
A = − 2  C
n ox ID 
L ID
Where VRD is voltage drop across load resistance

W VRD
A = − 2  n Cox 
L ID
• To increase the gain:
- make W/L larger
- make VRD large.... make RD large
- make ID smaller (make transistor weaker)

CMOS Analog Design 16

Trade-offs in maximizing the voltage gain:

• Larger W/L  larger input capacitance

• Larger VRD  smaller output swing
• If VRD is kept constant  ID has to be made smaller
 RD must be increased
 higher time constants at the output !
• Trade-off: gain, BW, voltage swing !

CMOS Analog Design 17

Intrinsic gain:

• Intrinsic gain = upperbound of the overall gain

• Ideal current source  infinite impedance
rO
• lim R D → , A  = −g m results in
rO
+1
RD
A  = −g m rO

• Todays technology:
gmrO is between 10 to 30

CMOS Analog Design 18

CS stage with diode connected load:

• In MOS technology, resistors are complicated to

implement
• Hence „active loads“ or so called „diode connected
transistors“ are used
• MOSFET acts as small signal resistor when gate and
drain is shorted
• Diode connected transistors are always in saturation
because VDS = VGS

CMOS Analog Design 19

Small signal equivalent circuit:

• As VDS = VGS  V1 = VX
VX
IX = + g m VX
rO
1 1
 Impedance rO 
gm gm

CMOS Analog Design 20

Active load with body effect:

Vx is the source potential of the transistor in

the operating point: hence Vbs equals Vx = V1

I X = (g m + g mb )VX +
VX
rO
CMOS Analog Design 21
Active load with body effect:
VX 1
• Impedance = =
IX g + g + 1
m mb
rO
1 1
= rO 
g m + g mb g m + g mb
• Thus the body effect reduces the impedance !

CMOS Analog Design 22

Voltage gain of CS stage with diode connected
load:

• For negligible λ,
1
A  = −g m1
g m 2 + g mb 2
g m1 1 g mb 2
=− where  =
g m2 1 +  g m2
• Considering device dimensions,
2  n C ox (W L )1 I D1 1
A = −
2  n C ox (W L )2 I D 2 1+ 

CMOS Analog Design 23

Voltage gain of CS stage with diode connected
load:

• Since ID1 = ID2 ,

(W L )1 1
A = −
(W L )2 1 + 

CMOS Analog Design 24

CS stage with diode connected load – Large
signal analysis:

• ID1 = ID2
W W
  n Cox   (Vin − VTH 1 ) =  n Cox   (VDD − Vout − VTH 2 )
1 2 1 2

2  L 1 2  L 2
W W
   (Vin − VTH 1 ) =   (VDD − Vout − VTH 2 )
 L 1  L 2

Note: If VTH2 depends only slightly on Vout (weak body

effect), then we have a linear behavior and Vout is
proportional to Vin

CMOS Analog Design 25

CS stage with diode connected load – Large
signal analysis:

• Differentiating both sides w.r.t Vin

W  W   Vout VTH 2 
  =    − − 
 L 1  L  2  Vin Vin 
• With application of the chain rule
VTH 2  VTH 2  Vout   Vout 
=    =  
Vin  Vout  Vin   Vin 
we get

Vout (W L )1 1 The result matches

A = =− with the small
Vin (W L )2 1 +  signal analysis !
CMOS Analog Design 26
Input / output characteristics of active load CS
stage:

• At point A, M1 enters the triode region (strong

nonlinearity !)
• Above VTH1 and below VA,
Vout  Vin (linear behavior)

CMOS Analog Design 27

CS stage with pMOS active load:

• To improve amplification we use CS

stage with pMOS active load
• pMOS output node can charge upto
full VDD .....more voltage swing !
• No body effect   = 0
•
 n (W L)1
A = −
 p (W L)2
• Gain depends very weakly on device dimensions

CMOS Analog Design 28

 CS-Stage with pMOS-Load
Output Voltage range

• Vout(max) = VDD – Vtp

• Vout(min): (more complicated) V
out(min)

VDD
M1 at unsaturated region: vds1  vgs1 − Vtn  vout  vin − Vtn

W vds1 ² W vout ²
id 1 = µnCox ((vgs1 − Vtn )vds1 − ) = µnCox ((vDD − Vtn )vout − )
L 2 L 2
µ p Cox W µ p Cox W
id 2 = (vsg 2 − Vtp )² = ( vDD − vout − Vtp )²
2 L 2 L
CMOS Analog Design 29
 CS-Stage with pMOS-Load
Output Voltage range:

• id1 = id2 to find out Vout

VDD − VT
vout (min) = VDD − VT −
results µ pWp
1+
µnWn

Assumption: For both PMOS and NMOS, VT values are

the same

CMOS Analog Design 30

 CS-Stage with pMOS-Load
A = Vout/Vin and
For output resistance Rout:
Sum up all currents flowing into the output node:
0 = gm1vin + gds1vout + gm 2vout + gds 2vout

Vout − g m1 µn COX W1 L2
= =
Vin g ds1 + g m 2 + g ds 2 µ p COX W2 L1
1 1
Rout = 
gds1 + gm 2 + gds 2 gm 2
CMOS Analog Design 31
Source follower:
• CS stage has a good voltage gain, but load impedance
has to be high
• If the load impedance is low, a „buffer“ is needed for
impedance matching
• The maximum possible voltage gain is 1.

CMOS Analog Design 32

Source follower:

• Source follower (or „common drain stage“) may

operate as a voltage buffer

CMOS Analog Design 33

Source follower – input/output characteristics:

• Vout follows Vin with a voltage difference (level shift)

equal to VGS

Vout
1
=  n Cox
W
(Vin − VTH − Vout ) R S
2

2 L

CMOS Analog Design 34

Small signal gain (large signal analysis):

Vout
1
=  n Cox
W
(Vin − VTH − Vout )2 R S
2 L
• Differentiating both sides w.r.t. Vin
Vout 1  VTH Vout 
2 (Vin − VTH − Vout )1 −
W
=  n Cox − R S
Vin 2 L  Vin Vin 
VTH  Vout 
• since =  
Vin  Vin 

Vout
 n Cox
W
( Vin − VTH − Vout )R S
= L
Vin 1 +  C W (V − V − V )R (1 + )
n ox in TH out S
L
CMOS Analog Design 35
Small signal gain (large signal analysis):

• With g m =  n C ox
W
(Vin − VTH − Vout ) we get:
L
gmRS
A =
1 + (g m + g mb )R S

CMOS Analog Design 36

Small signal gain (small signal analysis):

Vout
g m1V1 − g mb 1Vout =
RS
Vout
A =
Vin
gmRS
A =
1 + (g m + g mb )R S
• since Vin − V1 = Vout
Vbs = −Vout

The maximum possible gain is 1!

CMOS Analog Design 37
Small signal gain (small signal analysis):
Vout
• g m1V1 − g mb 1Vout =
RS
Vout
A = will result in
Vin
gmRS
A =
1 + (g m + g mb )R S

• Maximum possible gain = 1

CMOS Analog Design 38

Drawback of RS implemented as ohmic resistor:

• ID1 depends strongly on input DC level

• If Vin changes from 1.5 to 2.0 V (10 % increase)
then ID1 increases by a factor of „2“
• Hence VGS – VTH increases by √2 
highly non linear I/O characteristics !
• Improvement: instead of RS we take
a constant current source M2 to get
a linear behavior

CMOS Analog Design 39

Output impedance of SF with constant current
source as load:

• V1 = −VX
 I X − g m VX − g mb VX = 0

CMOS Analog Design 40

Output impedance of SF with constant current
source as load:
VX 1
• Hence = R out =
IX g m + g mb

• Note: Body effect decreases the output resistance of the

source follower !

CMOS Analog Design 41

Example:
Source follower:
W/L = 20µm/0.5µm
VTH0 = 0.6 V
|2ΦF| = 0.7 V
µnCox = 50 µA/V2
γ = 0.4 V2
I1 = 200 µA

Q1: What is Vout for Vin = 1.2 V?

Q2: If I1 is produced by an nMOS device, what is the
minimum W/L ratio for which M2 remains saturated?

CMOS Analog Design 42

Solution A1:

• VTH depends on Vout

Iterative solution:
(1) we calculate Vout for VTH0
(2) we calculate VTH for Vout obtained in (1)
W
I D =  n Cox  (Vin − VTH − Vout )
1 2

2 L
 (Vin − VTH − Vout ) =
2 2I D
W
 n C ox
L
2*200 A 2
 (1.2 − 0.6 − Vout ) =
2
V
50 A *40
CMOS Analog Design 43
Solution A1:
 Vout = 0.153 V
• Now,
(
VTH = VTH 0 +  2F + VSB − 2F )
(
 VTH = 0.6 + 0.4 0.7 + 0.153 − 0.7 )
= 0.635 V

• Using the new VTH the improved value of Vout is 0.119 V,

which is approximately 35 mV less than the calculated
value.
• The next iterations yield VTH = 0.635V ➔ 0.627V and
Vout = 0.117V ➔ 0.125V

CMOS Analog Design 44

Solution A2:

• Consider transistor in place of current source:

• Drain-source voltage of M2 is 0.119 V
• Device is saturated only if VGS – VTH < 0.119 V
• In the saturation region we have,
W
I D = 200 A =  n Cox   (0.119)
1 2

2  L 2
W 283 m
  =
 L  2 min 0.5 m

CMOS Analog Design 45

Common gate stage (CG):

CMOS Analog Design 46

Common gate stage (CG):

• In the CS-Stage and for Source-Followers input signal is

applied to a gate of a MOSFET.
• If the input is applied to the source terminal of a
MOSFET and output is taken at the drain terminal we
have a Comon Gate Stage
• Gate is connected to a dc voltage to establish proper
operating conditions
• Bias current flows directly through input signal source
– direct coupling
• M1 can be biased by a constant current source, with the
signal capacitively coupled to the circuit
– capacitive coupling
CMOS Analog Design 47
Direct coupling – Large signal analysis:

• Assume that Vin decreases from a large positive value

• Vin >= Vb – VTH: M1 is off and Vout = VDD
• For lower values of Vin: M1 goes into saturation

1
I D =  n Cox
W
(Vb − Vin − VTH )2

2 L
• As Vin decreases, so does Vout, eventually driving M1 into
the triode region if
1
VDD −  n Cox
W
(Vb − Vin − VTH )2 R D = Vb − VTH
2 L

CMOS Analog Design 48

CG input – output characteristics:

• If M1 is saturated, output voltage can be expressed as:

Vout
1
= VDD −  n Cox
W
(Vb − Vin − VTH )2 R D
2 L
CMOS Analog Design 49
CG stage small signal gain:

• Small signal gain can be obtained by differentiating w.r.t.

Vin
Vout  VTH 
= − n Cox (Vb − Vin − VTH ) − 1 −
W
R D
Vin L  Vin 
• Since VTH Vin = VTH VSB = , we have
Vout
R D (Vb − Vin − VTH )(1 + )
W
=  n Cox
Vin L
 A = g m (1 + )R D Gain is positive !

CMOS Analog Design 50

Multi-stage Amplifiers

CMOS Analog Design 51

Cascode stage:

• Input signal of a CG-stage may be a current

• A common source stage converts a voltage signal
into a current signal
• Cascade of a common source and a common gate
stage is called a „cascode stage“
• A cascode (cascaded triode, vacuum tube days)
offers advantages over simple CS-stages:
1. High output impedance!
2. High voltage gain!

CMOS Analog Design 52

Cascode stage:

• Cascade of a common source

and a common gate stage is
called a „cascode stage“
• M1 generates small signal
drain current proportional to
Vin
• M2 routes this current to RD
• M1 is the input device
• M2 is the cascode device
• M1 and M2 carry the same
current

CMOS Analog Design 53

Voltages in cascode stage:

CMOS Analog Design 54

Cascode stage – small signal equivalent circuit:

CMOS Analog Design 55

Cascode stage – output impedance:

• The circuit can be viewed as a degenerate common-

source with a source resistor rO1

CMOS Analog Design 56

Cascode stage – output impedance:

• Using the equation of output resistance for common

source stage,
R out = (1 + (g m 2 + g mb 2 )rO 2 )rO1 + rO 2
• Assuming g m rO  1 , we have
R out  (g m 2 + g mb 2 )rO 2 rO1
• M2 boosts the output impedance of M1 by a factor of
(g m2 + g mb 2 )rO2 !!

CMOS Analog Design 57

Cascode stage – voltage gain:

• Voltage gain of a cascode stage is given as:

A = − gm1 ( gm2 + gmb2 ) rO 2 rO1

• The maximum voltage gain is roughly equal to the

square of the intrinsic gain of the transistors
• High output impedance of the cascode stage results in a
high voltage gain !

• A simplified formula without body effect:

− gm1 2 K N '(W1 / L1 )
A  =−
gds 3 3P 2 I
Transistor „3“ is a PMOS-Fet connected to Vdd implementing
the pull-up-resistor
CMOS Analog Design 58
Cascode stage – Design Procedure:

• The following relations determine the properties of the

amplifier:

CMOS Analog Design 59

Cascode stage – Design Procedure:

• For cascode amplifiers we have the folllowing design

parameters:

1. The W/L-ratios for three transistors

2. The dc current I
3. The bias voltages

• Typical specifications are: supply voltage VDD, small

signal gain A, the max. and min. output voltage swing
vout(max) and vout(min), and the power dissipation P

• Example: VDD = 3,3V, A =-50 V/V, P = 1mW, Vout(max) =

2,8V and Vout(min) = 1,4V, Slew Rate 10V/µs @ 10pF

CMOS Analog Design 60

Cascode stage – Design Procedure:

1. P sets an upper bound 1mW/3V = 330µA, Slew Rate

sets a lower bound 100µA: We take I = 200µA
2. We calculate (W/L)3 since all other numbers are known in
the relation for M3 in the figure
W3 2I 400µA
= = = 26,7
L3 K P '(VDD − vout (max))2 60µA / V 2 (3.3 − 2.8)2V 2

• The current source on the upper left-hand side has the

same dimensions if IBIAS = I

3. Next we obtain (W/L)1 from the relation on the lower right

of the figure
W1 ( A  ) I ( 50  0.06 ) 200µA
2 2

= = = 51,5
L1 2K N ' 2 175µA / V 2

CMOS Analog Design 61

Cascode stage – Design Procedure:

4. Next we calculate (W/L)2

• First we need VDS1(sat) and use the vout(min)-spec to

obtain VDS2(sat)
2I 400µA
vDS 1 ( sat ) = = = 0,67V
K N '(W1 / L1 ) 175µA / V  51,5
2

• Subtracting this figure from 1.4V yields VDS2(sat)=0.73V

• Therefore
W2 2I 400µA
= = = 4,3
L2 K N 'VDS 2 ( sat ) (0,73) 175µA / V
2 2 2

CMOS Analog Design 62

Cascode stage – Design Procedure:

5. At last we need the bias voltage VGG2

• First we need VDS1(sat) and use the vout(min)-spec to

obtain VDS2(sat)

2I 400µA
VGG 2 = VDS 1 ( sat ) + + VTN = 0.67V +
K N '(W2 / L2 ) 175µA / V 2 (4.3)
= 0.67V + 0.73V + 0.50V = 1.90V

CMOS Analog Design 63

Current sources

CMOS Analog Design 64

Practical current source:

• For an ideal current source rO =  and Iout is constant for

all output voltages
• Normally rO is finite and Iout = f(Vout)

CMOS Analog Design 65

Requirements of a good performance current mirror:

• The current-ratio is precisely set by the aspect-ratio

(W/L) and is independent of temperature
• Output impedance is very high, i.e., very high Rout and
very low Cout. As a result, the output current is
independent of output voltage (DC and AC)
• Input resistance Rin is very low
• The voltage compliance is low, i.e., the minimum output
voltage Vout, for which the output acts as a current
source, is low

CMOS Analog Design 66

Basic current mirror:

• M1 is diode connected transistor which is always in

saturation
• ID1 is mirrored into transistor M2

CMOS Analog Design 67

Basic current mirror:
W1 W2
• Since VGS1 = VGS2 and if =  I D1 = I D 2
L1 L 2
provided the channel length modulation effects are very
small

•
1
I D1 =  n Cox
W1
(VGS1 − VTH )2

2 L1
1
I D 2 =  n Cox
W2
(VGS2 − VTH ) 2

2 L2
• Since VGS1 = VGS2 , I D 2 W2 L1 W/L ratios determine
=
I D1 W1L 2 ID2 !

CMOS Analog Design 68

Basic current mirror – design example:

• 5 design variables: L1, W1, L2, W2, and R = f(VGS)

• If we test 10 values per design parameter per simulation,

then we need 105 simulations !
• Strategy:
step (1): Select a common channel length such that λ is
very small
I D1 W1
L1 = L2 = L  =
I D 2 W2
λ = f(L) should be as small as possible
therefore L >> Lmin
Note: For AMS CSD Lanalog = 1 µm
CMOS Analog Design 69
Basic current mirror – design example:

• step (2): Select VGS

VGS is chosen close to VTH in order to have reasonable
currents in large devices

VGS – VTH = ΔV is „overdrive“ or excess voltage

n-channel device p-channel device Parameter

0.5 -0.65 VTH (V)

0.58 0.42  ( V)
175 60 Cox (  A V 2 )
0.06 0.06 λ (1/V) for L = 1µm

CMOS Analog Design 70

Basic current mirror – design example:

• For a reasonable overdrive voltage say, ΔV = 0.2V, we

get VGS = VTH + ΔV = 0.7 V

• step (3): Calculate R

VDD − VGS − VSS
R=
I D1
For example: to design a current mirror ID1 = ID2 = 10 µA
the required R can be calculated as
3.3 − 0.7 − 0 2.6
R= = = 260 k
10 A 10 A

CMOS Analog Design 71

Basic current mirror – design example:

• How to implement R = 260 kΩ ?

sheet resistance: N-well: 1 kΩ per square
NDIFF: 180 Ω per square
PDIFF: 160 Ω per square
Note: On-chip resistance of such a high value is not
possible to implement. To overcome this we usually use
externally connected resistances to the IC pins

• step (4): Calculate W1 and W2

 A 
 n Cox  2  * (0.7 − 0.5) = 10 A
1 W1
I D1 =
2

2 L1 V 
175  A 
 ( )
 2  * 0.04 V *
2 V 
2 W1
1 m
= 10 A
CMOS Analog Design 72
Basic current mirror – design example:

 W1 = W2 = 2.85 m  3 m
• step (5): Calculate Vmin
 VDS2  VGS − VTH
Vmin = Vout = V = 0.2 V

Note: Thus, the minimum output voltage = overdrive

voltage selected by the designer

• step (6): Calculate rout

1 1
rout = = = 1.67 M
I D 2 0.06 (1 V) *10 A
CMOS Analog Design 73
Basic current mirror – design example:

Design Example: 5/1 Current Mirror using Iref = 10µA

CMOS Analog Design 74

Cascode current mirrors:

• In practice, channel length modulation effect results in

significant error in copying currents
• While VDS1 = VGS1 = VGS2, VDS2 may not equal VGS2
because of the circuitry fed by M2
• In order to suppress the effect of channel length
modulation, a cascode current source can be used

CMOS Analog Design 75

Cascode curent mirrors:
• If Vb is chosen such that
VY = VX, then Iout closely
tracks IREF
• This is because the
cascode device „shields“
the bottom transistor from
variations in Vp
• Thus, we say that VY
remains close to VX and
hence ID2 = ID1 with high
accuracy

CMOS Analog Design 76

Cascode curent mirrors:
• Proper choice of the dimensions of M0 w.r.t. M3 yields
VGS0 = VGS3
• Connecting node N to the
gate of M3 we have
VGS0 + VX = VGS3 + VY

• If the transistor dimensions

are properly matched, then
we get VX = VY

• This result holds even if

M0 and M3 suffer from
body effect
• Voltage range: Vmin is 2*V
• Output resistance: gm2rds3

CMOS Analog Design 77

Differential Amplifiers

CMOS Analog Design 78

 Why Differential Amplifiers?

• Differential amplifiers are versatile building

blocks in analog circuits:
– Input stages of Operational amplifiers
– Read amplifier in SRAMs
– Noise and crosstalk immune signal
processing
– Low voltage data transfer

CMOS Analog Design 79

 Why Differential Signals?

Clock • Differential signals

are immune with
Coupling Signal
respect to crosstalk
effects as „+“ and „-“
signals are affected
in an identical
fashion!

CMOS Analog Design 80

Principles of Differential Amplifiers

• Differential amplifier may be

formed by two CS-stages.
• Problem im input voltage is
too low on one side, then
the corresponding CS-stage
is switched off!

➔ output voltage is clipped

➔ nonlinear behaviour

CMOS Analog Design 81

Principles of Differential Amplifiers

• Solution the two CS-

stages are source-
coupled by a current
source
• No clipping of output
voltage but slight
nonlinearities for low
input common mode
voltages!

Obviously the gain

vanishes for larger
input voltage
differences!
CMOS Analog Design 82
Key parameters of Differential Amplifiers

Gain (of course)

Input Common Mode Range: linear operation until one of the

transistors leaves saturation!
ICMR: Input Common Mode Range (ca. 50% VDD-VSS)

Offset:
Transistors M1 and M2 are not completely identical due to
process variations ➔
Vin1 = Vin2 not necessarily Vout1 = Vout2
but Vout1 = Vout2 if and only if Vin1 = Vin2 + Vos
Vos = Input-Offset-Voltage (typ. 5 - 20 mV)

CMOS Analog Design 83

Common Mode Amplification
Common Mode Voltages should not be
amplified!

Only Differential Voltages are of interest!

Common mode gain AvC = 0!

Vin1 + Vin 2
Vout1 − Vout 2 = A D (Vin1 − Vin 2 )  A C
2
Differential Common
Gain Mode Gain

CMOS Analog Design 84

Common Mode Amplifification
Common Mode Voltage VinCM
applied to the amplifier inputs
reduces the diff-amp to an
effective CS-stage with half the
load resistance and twice the
W/L-ratio of the pull-down
transistor. The common mode
gain results in

RD / 2
Acm =
1
+ RSS
W
2 2 n Cox I d
L
For a zero common mode gain Rss has to be infinity ➔
ideal current source at the bottom!
CMOS Analog Design 85
 Real Differential Amplifier

• Real Differential Amplifier amplifies a differential signal and outputs

a single ended voltage Vout

+
-
Vin1 Vin2 Vout
VSS

Quite often we have a symmetrical voltage range around 0V

e.g. VDD=2.5V, VSS=-2.5V
Then all voltages are referenced to analog ground: 0V

CMOS Analog Design 86

 Differential to Single Ended
• Just drop one output voltage say Vout1?

Vout

M1 M2
I SS I I SS I
I1 = − I2 = +
2 2 2 2

M3
ISS

If we do so, only I/2 = (I2 –I1)/2 is utilised to produce the

output voltage using the voltage drop over RD
Gain is reduced by 50%, as current of M1 is not considered!
CMOS Analog Design 87
 Differential to Single Ended
• Better solution is to mirror current in M1 into the output path

M3 M4 Vout

M1 M2

M5
ISS

If Vin grows then I1 + I and I2 - I but I3 and I4 grow due to

mirror-effect by I !
I2 gets smaller and I4 grows ➔ Vout  I !
CMOS Analog Design 88
 Gain Calculation
• Source-coupled pair M1 and M2 with a current mirror current source
(M3 and M4)
ID1 ID2
M1 M2
VG1 VG2
IBias VGS2
VGS1
MB
M5

VBulk

Note that M1 and M2 are effected by the substrate bias effect!

Hence bulk-terminals of these transistors may be connecte either
to VSS or to a floating well! MB is the mirror-transistor for
adjustment of the bias-voltage for M5
CMOS Analog Design 89
 Gain Calculation
• The input differential voltage vID maybe expressed by the differences
in the Gate-Source-Voltages of M1 and M2

ID1 ID2
2iD1 2iD 2
vID = vGS1 − vGS 2 = −
M1 M2
VG1 VG2
IBias VGS2 W W
VGS1
K 'N K 'N
MB L L
M4

VBulk

The current Iss in M4 is the sum of the currents of M1 and M2

I SS = iD1 + iD 2

CMOS Analog Design 90

 Gain Calculation
• The drain currents of M1 and M2 are readily obtained by using both
equations for vID and ISS and by some algebraic transformations:

I I  W vID 2  W  v ID 4 
2

iD1 = SS + SS  K 'N −  K 'N  2

2 2  L I SS  L  4 I SS 

I I  W vID 2  W  v ID 4 
2

iD 2 = SS − SS  K 'N −  K 'N  
2 2  L I SS  L  4 I SS 2 

The normalized currents look like

-2 ID/ISS 2
iD2 iD1

vID{ISS/KN’(W/L)}-1/2

CMOS Analog Design 91

 Gain Calculation

The current equations apply as long as the arguments of the

square roots remain real, imposing the condition:

I SS
v ID  2
K 'N W
L
From the currents one may obtain the transconductances of the
differetial inputs, which have the same magnitude but different signs:
The maximum gain is achieved at vID = 0

I D1 W I SS
gm = (VID = 0) = K ' N
vID L 4
Compared with the transconductance of an NMOS-Transistor ID=ISS/2 one sees
that the transconductance is reduced to 50%, because only half of the differential
input voltage is acting at each input node.
CMOS Analog Design 92
 Gain with current mirror loads

If a current mirror and no load resistances are utilized, the current

mirror mirrors the current in transistor M1 into the path with
transistor M2 with the correct sign and transform the output
differential voltage into a single ended signal.

VDD

M3 M4
iOUT
iD3
iD4 NMOS-inputs
M1 M2
PMOS Current
iD1 iD2 vOUT Mirror load
vG1 vG2
M5
VBIAS
ISS

CMOS Analog Design 93

 Gain with current mirror loads

iout is the differential current i1-i2 (perfect matching of devices). The

transconductance of this current is denoted gmd

iout W
gmd = (VID = 0) = K ' N 1 I SS = 2 gm
vID L1
Compared with the transconductance of an NMOS-Transistor ID=ISS/2
one sees that the transconductance is now 100%.

Large signal voltage transfer curve:

VDD
M4 linear
M4 Sättigung
VIC
M2 Sättigung
VSS M2 linear
vID
0
CMOS Analog Design 94
 Gain with current mirror loads

The (small signal) gain maybe obtained from

iout = gmd vID

vID = routiout
The output resistance is determined by the devices M2 and M4 in the
output sidebranch
1 1
rout = =
gds 2 + gds 4 ( +  ) I SS
2 4
2
Hence we obtain
vout 2 W 1
A = = K 'N 1
vID 2 + 4 L1 I SS

CMOS Analog Design 95

 Input Voltage Range
The differential amplifier operates properly until the input voltages are
such that one transistor leaves saturation.
This voltage range is investigated by setting the differential voltage to
zero and sweeping the common mode voltage VIC
To keep M1 (or M2) in saturation. We have to find the highest
(lowest) input voltage keeping M1 (and M2) in saturation:
D1 VDS1  VGS1 – VT1

G1
VDS1 VIC (max) = VG1 (max) = VDD − VSG 3 − VDS1 + VGS1 =
VGS1
S1 VDD − VSG 3 + VTN 1
Voltage drop in M3: VD1
The minimum voltage is determined by the voltage drop in the
source transistor M5
VIC (min) = VSS − VDS 5 ( sat ) + VGS1
CMOS Analog Design 96
 Slew Rate
The Slew Rate (SR) specifies the speed for charging or
discharging a capacitive load at the output CL to a voltage
which is the gain multiplied with VID. Note that all internal
parasitics contribute to the total output load. The
charging/discharging current is sourced from the current
sink (transistor M5).

SR = I 5 / CL

Current in M5

CMOS Analog Design 97

3dB-frequency and power dissipation

The 3dB-frequency is determined by the RC-time-constant

of the output branch
1
−3dB = 2 f −3dB =
Rout CL

Power dissipation Pdiss is obtained from the current

supplied or sourced from the bottom-transistor M5 multiplied
with the voltage drop from VDD to VSS

Pdiss = (VDD − VSS )  I SS

CMOS Analog Design 98

Summary of the relevant formula

For a design we use the following fomulas:

2
Rout =
(  N + P ) I 5
W1 g md
Adiff = g m1 Rout = 2n Cox I d 1  Rout =
L1 g ds 2 + g ds 4
Pdiss = (VDD + VSS ) I 5 = (VDD + VSS )  ( I 3 + I 4 )
1
−3dB =
Rout CL
VIC (min) = VSS − VDS 5 ( sat ) + VGS 2
VIC (max) = VDD − VSG 3 − VDS 1 + VGS 1 = VDD − VSG 3 + VTN 1

CMOS Analog Design 99

 How to meet the design targets?

Assume we have the following specification and we use the 0.8µm

sample technology

VDD = −VSS = 2,5V

SR  10V / µs
f −3dB  100kHz (CL = 5 pF )
−1,5V  ICMR  2V
Adiff = 100
Pdiss  1mW

In which order we have to determine the transistor dimensions for

a differential amplifier with NMOS-inputs and a PMOS current
mirror load?

CMOS Analog Design 100

 Design procedure: I5

The first quantity to be dimensioned is the current of

transistor M5 the source coupling current sink. This
transistor has to provide the current for charging and
dischargig the load capacitance. Hence the Slew-Rate-
Specification has to be considered:

SR = I 5 / CL = I 5 / 5 pF  10V / µs
I 5  50µA

CMOS Analog Design 101

 Design procedure: I5

We have to consider the upper bound for the power

dissipation, which limits I5 to 200µA and we have to be
aware that the this current is relevant for the output
resistance Rout, which itself enters together with CL into the
3dB-frequency, which was specified to exceed 100kHz ➔
Rout has to be less than 318 k
1
−3dB = 2 f −3dB =
Rout CL
1
6, 28 100kHz   Rout  318k 
Rout 5 pF
2
Rout =  318k 
( N + P ) I 5
CMOS Analog Design 102
 Design procedure: I5 then M3(=M4)
Using the channel length modulation factors we obtain I5 = 70µA.
To achieve some design margin we set I5 = 100µA

M3 (and M4) have to dimensioned according to the Input

Common Range ICMR

VIC (max) = VDD − VSG3 − VDS1 + VGS1 = VDD − VSG3 + VTN 1

Solving for VGS3 we obtain 2,5V – 2V + 0,7V = 1,2V = VSG3 This

voltage detremines the saturation current of M3, which has to be in
the operating point (vID = 0) equal to Iss / 2 = 50 µA. If use the
equation for the saturation current of M3 and solve for VGS3 = - VSG3
we get

CMOS Analog Design 103

Design procedure: I5 then M3(=M4)
Note that M3 is PMOS!
1 W
I D3 = 50 µA / V 2 3 (VGS 3 − VTP ) 2
2 L3
1 W
50 µA = 50 µA / V 2 3 (−1, 2 + 0, 7) 2
2 L3

2  50µA L3
VSG3 = 1,2V = + 0,7V
50µA / V ² W3

L3
0,5V = 2
W3
W3 W4 2
= = =8
L3 L4 0.5²

CMOS Analog Design 104

 Design procedure: M1 (=M2)
Using the gain specification and using
vout g md 2 W1 1
A = = = K 'N
vID g ds 2 + g ds 4 2 + 4 L1 I SS
W1 W
g md = g m1 = g m 2 = 2 K N ' I D1 = K N ' I SS 1
L1 L1
g ds 2 + g ds 4 = (N + P ) I D1,2 = (N + P )( I SS / 2)

W1 W1 µA
2 µnC Ox 2 110
L1 L1 V ² W1
= = 23,31 = 100V / V
(N + P )  I SS (0, 04 + 0, 05)  100µA L1

W3
100 = 23.31
L3
W1 W2
== = = 18, 4
CMOS Analog Design L1 L2 105
 Design procedure: M5
Using the lower ICMR specification we may calculate VDS5

VIC (min) = VSS − VDS 5 ( sat ) + VGS 2

At first we need VGS2 which can be calculated from the current in M2 which is in
the operating point ISS/2=50µA
µnCox W2
I2 = ( GS 2 TN )
−
2
V V
2 L2
W2/L2 = 18,4 and hence (using VT and the other technology dependent
parameters): VGS2 = 0.222V + 0,7V.
The resulting voltage VDS5(sat) = 0,3V – 0,222V = 0.0777V.
M5 has to provide for this small overdrive voltage of 0.0777V 100µA
W5 2 I5 200µA
= = = 300
L5 µnCoxVds 5 ( sat )² 110µA  ( 0,0777 ) 2

CMOS Analog Design 106

 Design procedure: Fine tuning
M5 is very large. To get a smaller M5 we need to increase M1 (and M2). Then
the voltage drop across the input transistors is less and hence VDS5 is
increased and then a smaller M5 is sufficient to provide the required 100µA

Using W1/L1 = W2/L2 = 25 we get W5/L5 = 150, which is sufficient for the resulting
overdrive voltage VDS5(sat) = 0,11V.
Note that the gain is increased by larger input transistors, but this is no
drawback!
In order to reduce the small channel effects we select as a common channel
length 1µm, which is slightly more than the minimum dimension of 0.8µm

W1 = W2 = 25 µm Cross check: Is the gain large enough?

W3 = W4 = 8 µm
W5 = 150 µm 2 K1'  W1 2 K1'  W1 2 110  25
A = = = = 117
1 + 2 L1  I SS 1 + 2 L1  I SS 0,09 100

CMOS Analog Design 107

1. Design targets for 0.35µm design

Assume we have the following specification and

we use the 0.35µm sample technology

VDD = −VSS = 1,65V

SR  10V / µs
f −3dB  100kHz (CL = 5 pF )
−1.1V  ICMR  1.3V
0.55V  ICMR  2.95V
Adiff = 100
Pdiss  1mW

CMOS Analog Design 108

2. Design targets for 0.35µm design

Assume we have the following specification and

we use the 0.35µm sample technology

VDD = −VSS = 1, 65V

W1/L1=164
SR  20V / µs W3/L3=84
f −3dB  200kHz (CL = 5 pF ) W5/L5=143
R=13,4kOHM
−1.1V  ICMR  1.3V
0.55V  ICMR  2.95V
Adiff = 200
Pdiss  1mW

CMOS Analog Design 109

Operational Amplifiers

CMOS Analog Design 110

 Overview

Operational Transconductance Amplifier – OTA

= Unbuffered Operational Amplifier

1. Design Methodology
2. Two-Stage Opamps
3. Frequency Compensation of Opamps
4. Cascode Opamps
5. Characterization of Opamps

CMOS Analog Design 111

 Opamp Design Methodology

• Differential-transconductance OTA-stage provides the

differential-to-single-ended conversion as well as good
part of overall gain
⇒ improves noise + offset performance

• Second gain-stage is usually an inverter

• If opamp is to drive low-resistive loads, a buffer (output)
stage must be included ⇒ to lower the output
resistance and maintain a large signal swing
• Bias circuit provides the proper operating point to each
stage

CMOS Analog Design 112

 Opamp Design Methodology

• Compensation is necessary to ensure

close-loop stability!

CMOS Analog Design 113

 Opamp Design Methodology
Ideally, an opamp has:
• Infinite differential-voltage gain
• Infinite input-resistance
• Zero output-resistance
• Infinite bandwidth
• Perfect rejection of common-mode voltage (CMRR →∞)
• Perfect rejection of supply voltage variations (PSRR
→∞)
In reality, an opamp only approaches these
conditions:
For most applications involving unbuffered opamps,
an open-loop of 5000 or more is usually sufficient
CMOS Analog Design 114
 Ideal and non ideal Opamp
Symbol for an opamp realized by a VCVS

CMOS Analog Design 115

 Ideal and non ideal Opamp
Model for a real Opamp

CMOS Analog Design 116

 Ideal and non ideal Opamp
Modelparameters for Opamp-Model
• Rid, Cid : differential-input impedance
• Ricm : common-mode input resistance
• Rout: output resistance
• VOS: input-referred offset voltage ( necessary to make Vo=0 when both
inputs are grounded)
• IB1, IB2: input-bias current (approx. zero for a CMOS opamp)
• Vi/CMRR : represents the effect of a finite common-mode rejection ratio on
the opamp output.
• en2 and in2 : model the input-referred noise generated by the opamp
components. These are voltage- and current-noise spectral densities, with
units of mean square volts and mean square amperes, respectively. They
have no polarity and are always assumed to add.

CMOS Analog Design 117

 OpAmp non-idealities
a) Finite Bandwidth:

CMOS Analog Design 118

 Finite Bandwidth
p1, p2, p3 … are poles of the opamp open-loop transfer
function.
In general, pi = -ωi , where ωi is the reciprocal time-
constant or break-frequency of the pole pi.
Zeros are ignored at the present time as they appear
frequencies well-above the unity gain frequency of the
opamps to be discussed.

CMOS Analog Design 119

 Finite Bandwidth
Bode-Diagram: Amplification vs. Frequency (semilog.)

CMOS Analog Design 120

 Finite Bandwidth and PSSR
• Typical frequency response: imposed by design, ω1 is
much lower than other pole frequencies
• ⇒ω1has the dominant influence in the frequency
response (p1 is the dominant pole)
b) Finite PSSR (Power Supply Rejection Ratio)
• PSRR : represents the change in the output voltage
caused by a variation on the supply
• voltage. PSRR+ and PSRR- are referred to VDD and
VSS, respectively.

CMOS Analog Design 121

 Finite PSSR
• Fully-differential (differential-in, differential-out)
structures minimize the effect of supply variations on the
opamp output, as they are seen as common-mode
voltages, at expense of higher circuitry complexity,
however.

CMOS Analog Design 122

 OpAmp non-idealities

c) finite Slew-Rate
• The opamp output has a limited capability to
drive/source load currents. There’s a limited range over
which the output voltage can swing while still maintaining
high-gain property.
• The limiting voltage-rate associated to the output swing
when a large-signal is applied to the input is called slew-
rate, which is usually determined by the maximum
current available to charge/discharge a capacitance.

CMOS Analog Design 123

 Slew Rate

Slewing effect on a unity-gain closed-loop opamp configu-

ration. Normally, slew-rate is determined by the first
stage, rather than by the output circuit.

CMOS Analog Design 124

 OpAmp non-idealities

d) finite Settling Time

• Important in sampled-data applications, it is the time
needed for the opamp output to reach a final value, to
within a predetermined tolerance, following a small-
signal applied to the input.
• The settling time can be completely determined from the
location of poles (and zeros) in the opamp small-signal
transfer function

CMOS Analog Design 125

 Settling Time
Time-response to a small-signal voltage-step on
closed-loop configuration (buffer)

CMOS Analog Design 126

 Typical Unbuffered CMOS Opamp
Specifications
• Open-loop Voltage Gain ≥ 70dB
• GBW (unity-gain frequency) ≥ 2MHz
• Settling-time ≤ 1μs
• Slew-rate ≥ 2V/μs
• Input CMR ≥ ± 3V
• CMRR ≥ 60dB
• PSRR ≥ 60dB
• Output swing ≥ ± 4V
• Output resistance ≤ 50 – 100Ω
• Offset voltage ≤ 10mV
• Noise ≤ 100nV/Hz1/2 @ 1KHz
• Layout area ≤ 120k sq μm
CMOS Analog Design 127
Typical Unbuffered CMOS Opamp
Specifications
Boundary Conditions
Supply-voltage: ±5V ±10%
Supply-current: 100μA (quiescent)
Temperature range: 0 to 70°C

CMOS Analog Design 128

Typical Unbuffered CMOS Opamp:
2 Stage Architecture
M1 to M5 stage 1, M6 and M7 stage 2

Compensation
Capacitor CC

CMOS Analog Design 129

Frequency-Compensation of Opamps
Opamps are primarily used in closed-loop configuration.
The high and imprecise gain can be used with
negative feedback to achieve a very accurate transfer
function, which approximately depends only on the
feedback elements.

CMOS Analog Design 130

 Negative Feedback System
If F(s)A(s) = -1 at s = j1 the gain reaches infinity
and the circuit amplifies ist own noise until it
begins to oscillate. In other words:
if F(j1 )A(j1 ) = -1 the circuit begins to oscillate!

Barkhausen criteria

CMOS Analog Design 131

 Negative Feedback System
This situation happens at a particular ferquency s = j1 ,
where magnitude and phase
F(s)A(s) = 1 and arg{F(s)A(s)} = -180
represent F(j1 )A(j1 ) = -1
Note that total phase shift around the loop at critical
frequency 1 is 360 (or 0 because of mod(360°-
feature) but the negative feedback alone adds 180 of
phase shift, so we have 180 (or -180) left for the
OpAmp and the feedback circuit.
Loop gain of unity or larger is also required to enhance the
oscillation amplitude!

CMOS Analog Design 132

 Negative Feedback System
The frequencies where the magnitude and the
phase of the loop gain are equal to unity or -
180 are of special importance to stability.
For stability one has to avoid the Barkhausen
criteria by adding appropriate passive
components into the loop!
How to do so?
Look at the Bode-Diagram!

CMOS Analog Design 133

Frequency-Compensation of Opamps
It’s imperative that the signal fed back to the input be of
such amplitude and phase that it does not regenerate
the signal around the loop, leading to either an
oscillation or clamping the opamp output to one of the
supply potentials.
In order to avoid positive and regenerative feedback,
the following conditions should be met (in an negative
feedback system):

Loop Gain = - F(s)A(s) < 1 and Phaseshift < -180

CMOS Analog Design 134

 Example for Bode Plots
Look at a transfer function:
s +1 1 + 1/ s
H ( s ) = 100 = 0.1
( s + 10)( s + 100) (1 + s /10)(1 + s /100)
All poles and roots are given in the form: (1+s/k)
One root at s = -1 and two poles at s = -10 and s = -100.
For a Bode-Plot the complex factors are written as phasors,
i.e. absolute value times the phase factor.
1 + s /1 1 + j /1 (1 + j )
H ( s) = 0.1 = 0.1 (0.1)
(1 + s /10)(1 + s /100) (1 + j /10) (1 + j /100) (1 + j /10)(1 + j /100)
(1 + j ) = exp(arctan( j /1))

CMOS Analog Design 135

 What looks the Bode Plot like?
MATLAB generates the Bode-Plot using the commands
– >> Mysys=tf(100*[1 1],[1 110 1000])
–
– Transfer function:
– 100 s + 100 magnitude
– ------------------
– s^2 + 110 s + 1000
– phase
– >> bode(Mysys)
Bode diagram consists of 2
plots: magnitude (or „gain“) in
dB and phase (linear) against
the logarithmic frequency
CMOS Analog Design 136
 Asymptotic Bode Plots: The Phase
Note: Phase factor is exponential of the arctangens of the fraction of
imaginary part divided by the real part of the complex number.
Hence the total phase is the sum of the individual phase angles.
The real coefficient which is multiplied with the fraction (here 0.1) in
general maybe positive or negative:
A positive factor has phase 0 and a negative factor -180

H ( s) = H ( s) exp j(arctan(0)  exp j(arctan()  exp j( − arctan( /10)  exp j(− arctan( j /100) =
H ( s) exp(exp j(arctan(0 + j − j /10 −  /100)
Drawing the phase is simple, just draw the phase-angles individually
and add them!

CMOS Analog Design 137

 Asymptotic Bode Plots: The
Magnitude
Magnitude is a product of different terms. In order to draw them in a
simple fashion, we take a logarithm.
To be specific we write the magnitude in units of decibels.
Each quantity Q has a representation X in decibels:
X = 20.0log10(Q)
The magnitude in decibels reads:
1 + j /1
H ( s ) = 0.1
(1 + j /10) (1 + j /100)
20  log H ( s ) = 20  log 0.1 + 20  log 1 + j /1 − 20  log 1 + j /10 − 20  log 1 + j /100

Changing to decibels transforms the multiplication into a summation

of constant terms and terms of the form 20log101+j/k!

CMOS Analog Design 138

 Constructing a Bode Diagram
A constant term:
H(s)=100=40dB
The magnitude is straight line and the phase is 0

CMOS Analog Design 139

 Constructing a Bode Diagram
A real pole: 1 1
H ( s) = =
s 
1+ 1+ j
0 0
0 is the -3dB or corner frequency.
The magnitude is given by
2
1 
20 log10 H ( s ) = 20 log10 = −20 log10 1+  
1+ j
  0 
0
Boundary Cases
low frequency   0 : H ( s )  0dB
2
 
high frequency   0 : H ( s )  −20 log10   = −20 log10  
 0   0 
2
 0 
break frequency  = 0 : H ( s ) = −20 log10  1 +  = −20 log10
 0 
( 2 ) = −3.01dB
CMOS Analog Design 140
 Constructing a Bode Diagram
A real pole: H ( s) = 1 1
=
s 
1+ 1+ j
0 0
0 is the -3dB or corner frequency.
The phase is given by

H ( s ) = − arctan  
 0 
Boundary Cases
low frequency   0 : H ( s )  − arctan ( 0 ) = 0

high frequency   0 : H ( s )  − arctan (  ) = −90 = − rad
2

break frequency  = 0 : H ( s )  − arctan (1) = −45 = − rad
4
CMOS Analog Design 141
 Constructing the Magnitude
Using the high and low frequency approximation we
obtain:

CMOS Analog Design 142

 Constructing the Phase
Using the high and low frequency approximation we
obtain:

CMOS Analog Design 143

 Constructing a Bode Diagram
s 
A real zero: H ( s) = 1 + = 1+ j
0 0

The magnitude is given by

2
 
20log10 H ( s ) = 20log10 1 + j = 20log10 1+  
0  0 
Boundary Cases
low frequency   0 : H ( s )  0dB
2
 
high frequency   0 : H ( s )  20log10   = 20log10  
 0   0 
2
 0 
break frequency  = 0 : H ( s ) = 20log10  1 +  = 20log10
 0 
( 2 ) = 3.01dB
CMOS Analog Design 144
 Constructing a Bode Diagram
s 
A real zero: H ( s) = 1 + = 1+ j
0 0

The phase is given by


H ( s ) = arctan  
 0 
Boundary Cases
low frequency   0 : H ( s )  arctan ( 0 ) = 0

high frequency   0 : H ( s )  arctan (  ) = 90 = rad
2

break frequency  = 0 : H ( s )  arctan (1) = 45 = rad
4

CMOS Analog Design 145

 Constructing a Bode Diagram
Example for neg. real
zero: s
H ( s) = 1 +
30
Magnitude rises by
20dB per decade
Phase rises by 90
10% of 0

10 times 0

CMOS Analog Design 146

 Constructing a Bode Diagram
Example for positive
real zero
s
H ( s) = 1 −
30

Decreases phase
margin! Like a pole!

CMOS Analog Design 147

 Rules for Ass. Bode Plots
Bode Plots illustrate the asymptotic behavior of
magnitude and phase of a complex function in terms
of it‘s poles and zeros.
Rule 1: The slope of the magnitude plot changes by
+20dB/dec at every zero and by -20dB/dec at every
pole frequency.
Rule 2: At every pole(zero) frequency m the phase
begins to fall(rise) at approximately 0.1m,
experiences a change of -45(+45) at m and -
90(+90) at 10 m
Note that the phase is much more affected by high
frequency poles than the magnitude is!

CMOS Analog Design 148

 Location of poles
Poles and zeros in the complex plane: sp = jp + p
Pole in the RHP: p > 0. As the impulse response
includes a term of the form exp(jp + p)t then the
time domain response contains a growing exponential
➔ oscillation
Pole at the imaginary axis: p = 0. In the time domain
response circuit sustains oscillation
Pole in the LHP: p < 0. As the impulse response
includes a term of the form exp(jp + p)t then the
time domain response contains a falling exponential
➔ oscillation is damped out!
If one plots the location of poles as the loop gain varies
one gets a root locus diagram
CMOS Analog Design 149
Frequency-Compensation of Opamps
Stability is achieved if following condition hold

– Stability condition is better illustrated with the use of Bode

diagrams. The A(jω)F(jω)  curve must cross the 0dB-
point before Arg[- A(jω)F(jω)] reaches 0°
– A measure of stability is given by the phase value when
A(jω)F(jω)  =1 and it is called phase-margin M.

CMOS Analog Design 150

Frequency-Compensation of Opamps
Note: CMOS OpAmp has a negative
feedback: Inherent phase margin of 180

CMOS Analog Design 151

Frequency-Compensation of Opamps

The importance of good stability with adequate

phase-margin (ΦM) is better understood by
considering the response of the closed-loop system
in time domain, shown in the figure below, for
different phase-margin values.

• Larger phase-margins result in less ringing of the

output signal.
• It’s desirable to have ΦM of at least 45°, whereas
60° is preferable in most cases.

CMOS Analog Design 152

Frequency-Compensation of Opamps
Closed-loop time-response for different ΦM values

CMOS Analog Design 153

Frequency-Compensation of Opamps
2-stage opamp equivalent small-signal circuit

There are two poles (second order system)

CMOS Analog Design 154

Frequency-Compensation of Opamps

There are two poles (second order system)

CMOS Analog Design 155

Frequency-Compensation of Opamps
As Ro1 and Ro2 and naturally high in order to obtain
very high voltage gain on every stage, both poles
have relatively low-frequencies ⇒ very low ΦM ⇒
frequency compensation is needed to move one
pole to higher frequencies.

CMOS Analog Design 156

 The Miller-Capacitance (pole-splitting)
Compensation of Opamps
This technique comprises connecting a capacitor CC from
the output to the input of the second stage, leading to:

i) the effective capacitance Co1 is increased by a factor

(gm2Ro2) CC , which moves down p1 quite considerably.

ii) owing to the negative feedback, the second-stage output

resistance is reduced, moving p2 to higher frequencies

CMOS Analog Design 157

 The Miller-Capacitance (pole-splitting)
Compensation of Opamps
This technique comprises connecting a capacitor CC from
the output to the input of the second stage, leading to:

CMOS Analog Design 158

The Miller-Capacitance (pole-splitting)
Compensation of Opamps

CMOS Analog Design 159

The Miller-Capacitance (pole-splitting)
Compensation of Opamps

⇒ as far as phase-shift is concerned, a RHP zero behaves

like a LHP pole ⇒ΦM is degraded

⇒ Compensation comprises moving p2 and z1 (except

p1) to frequencies sufficiently high beyond the unity-
gain frequency of the opamp

⇒ a first-order system condition is approached

CMOS Analog Design 160

The Miller-Capacitance (pole-splitting)

CMOS Analog Design 161

The Miller-Capacitance (pole-splitting)
Compensation of Opamps
Root-locus movement as CC increases and Bode plots before and after
compensation for gain and Bode plot after compensation for phase.
unkorrigiert

104dB
Arg|A(j)F(j)| |A(j)F(j)|

−6dB/Okt.

p’1 p1 −12dB/Okt.
0dB
p’2 p2 
180

90

0 M

j


p2 p’2 p’1 p1 z1

CMOS Analog Design 162

Eliminate or Relocate the RHP zero
The RHP zero can be displaced by inserting a nulling
resistor RZ in series with CC

CMOS Analog Design 163

Eliminate or Relocate the RHP
zero
Again, assuming that p1 and p2 are widely spaced
and Rz << Ro1 or Ro2, it turns out

CMOS Analog Design 164

Eliminate or Relocate the RHP
zero

CMOS Analog Design 165

Eliminate or Relocate the RHP
zero

CMOS Analog Design 166

Eliminate or Relocate the RHP
zero

Implementation of Resistor by linear MOSFET

CMOS Analog Design 167

 Design procedure

Specification

A > 5000 V/V VDD = 2,5 VSS = -2,5V

Verst.*Bandbr. CL = 10 pF Slew Rate >

(GB): 5 MHz 10V/µs
Vout-Bereich:  2V ICMR = -1 bis 2V Pdiss  2mW

CMOS Analog Design 168

 Design procedure
Circuit diagram

M4 M6
M3

IREF
Io
R CC Vout

- CL
vin M1 M2
+
+

M5 M7
-

CMOS Analog Design 169

 1. Choice of technology and
channel length

⇒ Compensation comprises moving p2 and z1 (except

p1) to frequencies sufficiently high beyond the unity-
gain frequency (the Gain-Bandwidth GBW) of the
opamp

⇒ a first-order system condition is approached

CMOS Analog Design 170

 1. Choice of technology and
channel length

We use a 0.8µm CMOS technology

⇒ Minimum Channel Length is 1,0µm

CMOS Analog Design 171

 The Miller Capacitance

Moves p2 and z1 (except p1) to frequencies sufficiently

high beyond the unity-gain frequency (the Gain-Bandwidth
GBW) of the opamp

⇒ OpAmp behaves like a a first-order system

(Low Pass)

CMOS Analog Design 172

 2. Choose the Miller-Capacitance
As outlined in the previous slides
Position of non dominant pole and the root in RHP are given by
the transconductance of second stage (i.e. that of transistor M 6
in the schematic) and the output capacitance (i.e. in principle
the load cap)
− gm 6 gm 6
p2  z1 
CL CC

GB is amplification at 0Hz multiplied with p1:

g(1st . sat ) g(2 nd stage. sat ) Ro1R02 = A (0)
1 g m1
p1 = − GB 
g(2. stage ) Ro1Ro 2CC Cc
CMOS Analog Design 173
 Choosing the Miller-Capacitance
The 2 stage OpAmp has two poles and one RHP-zero. If the zero is assumed
to be placed 10 times higher then the Gain-Bandwidth (GB), then the second
pole has to be placed at a frequency 2.2times higher than GB to obtain a
phase margin of 60 = M
The total phase is the
 M = 180 − Arg  A( j ) F ( j ) =
sum of the individual
   phase contributions of
180 − tan −1 − tan −1 − tan −1 = 60
p1 p2 z1 the two poles and the
GB GB GB zero
120 = tan −1 + tan −1 + tan −1
p1 p2 z1

The phase margin has to be 60 below and above GB. Hence all
frequencies are replaced in the formula by GB.
GB is given by the DC-amplification multiplied by the absolute value of
the dominant pole p1. As A(0) is very large we obtain

CMOS Analog Design 174

 Choosing the Miller-Capacitance
together with our assumption that the zero is placed 10 times
higher then the Gain-Bandwidth (GB) in the third term we obtain

−1 GB −1
120 = tan A (0) + tan + tan −1 0,1
p2
GB
24,3 = tan −1
p2
tan −1 A (0)  tan −1 ( ) = 90
tan −1 (0.1) = 5,7
Therefore the pole p2 has to be located 2.2 times higher then GB:
GB
tan 24,3 = tan(tan −1 ) = 0.45
p2
GB
p2 = = 2.2GB
0.45
CMOS Analog Design 175
 Choosing the Miller-Capacitance
If the RHP-zero is placed at 10xGBW, by placing the non dominant pole
p2 at a frequency 2.2times higher than GBW gives 60 = M

− gm6 g g
g g
z1  m 6  10GBW = 10 m1 p2  = m 6 = 2.2 m1
CL CL CC
CC CC
g m1 g
 g m 6  10 g m1 or g m 6  10 g m 2 with g m 6  10 g m1   2.2 m1  10CC  2.2CL
CL 10CC

CC  0, 22CL
here CL = 10 pF
CC = 2.2 pF better CC = 3 pF

CMOS Analog Design 176

 Choosing I5 for the Slew Rate
The slew rate is determined by the current of M5 divided by the load
capacitance of the differential stage at the input. The load is the Miller
capacitor:

SR = I 5 / CL*) = I 5 / 3 pF  10V / µs

I5 = SR(Cc )  (10V / µs )(3 pF ) = 30µA

*)Load capacitace for I5 is the compensation capacitor!

CMOS Analog Design 177

 Choosing W3 and W4
These two devices form a current mirror. The relevant spec-value is the
maximum ICMR-voltage Vin(max) = 2.0V:

I5
W3 = =
K (VDD − Vin (max) − VT 03 (max) + VT 1 (min) )
' 2
3

30µA
= 15µm
50 10 −6
( 2,5V − 2,0V − 0,85V + 0,55)
2

Therefore we have identical widths of 15µm for M3 and M4

CMOS Analog Design 178

 Choosing gm1 i.e. W1 and W2
gm1 is the transconductance of the input transistors forming a differential pair
(M1 and M2). This quantity is related to the GB specified and Cc obtained
already:

 gm1 = ( 5 106 ) ( 2 ) ( 3 10−12 ) = 94, 25µS

gm1
GB =
Cc

Since M1 and M2 provide 50% of the I5-current which was calculated to be

30µA, we find

W1 W2 g m12 94, 252

= = = = 2,79  3
L1 L2 2 K N ' I1 2 110 15

CMOS Analog Design 179

 Choosing W5 by VDS5
The drain-source voltage of M5 is obtained from the required minimum input
common mode voltage -1.0V.

I5
VDS 5 = Vin (min) − VSS − − VT 1 (max) =
ß1
Note: ß = K‘/W/L)
−6
30 10
−1V − ( −2,5V ) − V − 0,85V = 0,35V
3 110 10−6
This voltage must not drop below VDS(sat) in order to keep M5 (as an
effective current source) in saturation

2I5 W5 2I5
VDS 5 ( sat ) =  = ' 2
=
ß5 L5 K 5 (VDS 5 )
2 ( 30 10−6 )
−6
= 4, 49  4,5
110 10 (0,35) 2

CMOS Analog Design 180

 Choosing W6 from gm6 and gm4
Since the transconductances of M1 and M2 are identical we obtain from the
considarations for the choice of the Miller capacitance

g m 2CL g 10 pF
gm 6 = 2, 2 = 2, 2 m1 = 942,5µS
Cc 2, 2 pF
gm4 is determined by I5: ID4 = I5/2:

W 
gm 4 = 2K P '   I D 4 = 2  50 10−12 15 15 = 150µS
 L 4
From gm4, W4/L4 and gm6 we may calculate W6/L6 : Mirroring in first stage
requires VSG4  VSG6 hence:

 W   W  gm 6 942
  =  = 15 = 94
 L 6  L  4 g m 4 150
CMOS Analog Design 181
 Choosing W7
The current ratios of M6 and M5 determine the width of this transistor

 W   W   I6   W 
  =        = 14
 L  7  L 5  I 5   L  7

I6 can be determined from gm6 and the W/L-ration of this transistor from
the small signal formula of the input transconductance. If M7 leaves
saturation then we are at the minimum output-voltage-range (here -2V):
Vmin (out ) = −2,5V + VDS 7 ( sat )

2I7 2  95
VDS 7 ( sat ) = = = 0,351V
W
K N' 7 110 14
L7

The minimum output voltage is met, hence first cut design is complete!
CMOS Analog Design 182
 Recheck Gain and Power
With the dimensions obtained so far, we check whether Pdiss and A are OK

Pdiss = 5V (30µA + 95µA) = 0,625mW  2mW

 2 gm 2 gm 6 
A =  =
 I 5 (2 + 7 ) I 6 (6 + 7 ) 
 2  942,5  92, 45  10−12 
 −12 
= 7696V / V  5000V / V
 30(0,04 + 0,05)95(0,04 + 0,05)  10 

First cut design meets specification!

CMOS Analog Design 183

Final Design with dimensions
M6
M3 M4 94/1
2,5V 15/1
15/1
IREF
Io
R CC =3 pF vout

- CL =10 pF
M1 M2 95µA
vin
3/1 3/1
+
+
30µA
VBIAS M7
M5
- 14/1
4,5/1
-2,5V

CMOS Analog Design 184