Digital CMOS IC Design

Course Overview
• Basics of MOS(FET) Transistor
– Types
– MOSFET characteristics
– MOSFET as a Switch
• CMOS Inverter
– Static Behavior
– Dynamic Behavior
– Power Dissipation
• Designing Combinational Logic Gates in CMOS
– Static CMOS Design
– Dynamic CMOS Design
 Objectives
• Provide the understanding of primary design building
block, semiconductor devices-MOSFET
• Design and analysis of an CMOS gates.
• Provide the understanding of different techniques
through which complex logic gates can be
implemented.
 Session Plan
Session Topics to be covered

1 MOSFET types, Characteristics and MOSFET as a switch

2 Static Behavior of CMOS Inverter- Switching Threshold, Noise Margin

3 Dynamic Behavior of CMOS Inverter- Capacitance and Propagation

Delay
4 Power Consumption- Static and Dynamic Power Consumption

5,6 Static CMOS Design Techniques-Complementary CMOS, Ratioed Logic,

Pass-Transistor Logic

7,8 Dynamic CMOS Design- Dynamic Logic Concept and Domino Logic
 Introduction

• Why is designing digital

ICs different today than
it was before?
•SSI (Less than 100 components)
•MSI ( Less than 500 components in 1960)
•LSI (Less than 10000 in 1970)
•VLSI (1.5 Mega components, in 1980)
•ULSI, 3D IC (more than 1.5 Mega components in 2009)

5
The First Computer

The Babbage
Difference Engine
(1832)
25,000 parts
cost: £17,470

6
ENIAC - The first electronic computer (1946)

7
The Transistor Revolution

First transistor
Bell Labs, 1948

8
The First Integrated Circuits

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966

9
Intel 4004 Micro-Processor

1971
1000 transistors
1 MHz operation

10
Intel Pentium (IV) microprocessor

11
 Design Metrics

• How to evaluate performance of a digital

circuit (gate, block, …)?
– Area
– Speed (delay, operating frequency)
– Power dissipation

12
 Moore’s Law

In 1965, Gordon Moore noted that the

number of transistors on a chip doubled
every 18 to 24 months.
He made a prediction that semiconductor
technology will double its effectiveness every
18 months

13
 Transistor Counts
1 Billion Transistors
K
1,000,000

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected

Courtesy, Intel 14
Moore’s law in Microprocessors
1000

100 2X growth in 1.96 years!

Transistors (MT)

10
P6
Pentium® proc
1 486
386
0.1 286
8085 on 8086
Transistors
Transistors
0.01 Lead
Lead Microprocessors
on8080 Microprocessors double
double every
every 22 years
years
8008
4004
0.001
1970 1980 1990 2000 2010
Year

Courtesy, Intel 15
 Frequency
10000
Doubles every
1000 2 years
Frequency (Mhz)

100 P6
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Lead
Lead Microprocessors
Microprocessors frequency
frequency doubles every
every 2 years

Courtesy, Intel 16
 Power Dissipation
100

P6
Pentium ® proc
Power (Watts)

10
486
8086 286
386
8085
1 8080
8008
4004

0.1
1971 1974 1978 1985 1992 2000
Year

Lead Microprocessors power continues to

to increase
increase

Courtesy, Intel 17
Power will be a major problem
100000
18KW
10000 5KW
1.5KW
Power (Watts)

1000 500W
Pentium® proc
100
286 486
10 8086 386
8085
8080
8008
1 4004

0.1
1971 1974 1978 1985 1992 2000 2004 2008
Year

Power delivery and dissipation will be prohibitive

Courtesy, Intel 18
 Power density
10000
Rocket
Power Density (W/cm2)

Nozzle
1000
Nuclear
Reactor
100

8086
10 4004 Hot Plate P6
8008 8085 386 Pentium® proc
286 486
8080
1
1970 1980 1990 2000 2010
Year

Power
Power density too high to keep junctions at low temp

Courtesy, Intel 19
Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

20
MOSFET
 Uni-polar Device
Basics of MOSFET
4 terminal device GATE
SOURCE DRAIN
MOSFET is symmetrical device with
respect to gate

Aspect Ratio W/L

N-channel

BODY
Symbol

NMOS

PMOS
Layout Of MOSFET
 Basic Operation Of Mosfet
When Vgs = 0 and Vds= +ve Voltage

Vgs = 0

Vds = +ve

I=0

Diodes in Reverse Bias Offers high resistance

 Basic Operation Of Mosfet
When Vgs = +ve and Vds= +ve

Vgs = +ve
Potential at which current
Starts to flow is known as Vds = +ve
Threshold Voltage Vth

I D
-- -- -- -- -- -- -- -- -- --

Depletion Region
+ + + + + N-channel
+ + + + +
 Basic Operation Of Mosfet
When Vgs = +ve and Vds= Vgs-Vth

Voltage between gate and Vgs = +ve

points along the channel
decreases from Vgs at Vds = Vgs-Vth or Vgd = Vth
source end to Vgs-Vds at
drain end so channel width
is not uniform.

Channel width is maximum

at source end and
minimum at drain end
because voltage at source
end is higher than voltage Channel is pinched
at drain end Off. point at which
Vgs-Vds =Vth
 What is Pinch-off
Initially we get an increasing
current with increasing drain bias

When we reach VDsat = VG – VT,

inversion layer(channel) is disabled at
the drain end (pinch-off)

The charges still flow, just that you

can’t draw more current
with higher drain bias, and the
current saturates
Current-Voltage Relations
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3
VDS = VGS - VT
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)
 Current Through Semiconductor Bar

First Consider a semiconductor bar carrying current I. If the charge density along the
direction of current is Qd columns per meter and the velocity of the charge is v meter per
second.

Current is total charge that passes through the a cross section of the bar in unit time. With
a velocity v, all of the charge enclosed in v meters of the bar must flow through the cross
section in one second.

Since charge density is Qd columns per meter , total charge in v meters equal to Qdv and
this charge must flow through the cross section and current is given by,

I  Qd
I/V Characteristics
Qd is charge density of channel
and v is velocity of electrons

I  Qdv
Qd  WCox[VGS  V ( x)  VTH ]

I  WCox[VGS  V ( x)  VTH ]v

-Ve sign is inserted because channel charge

carrier is electrons
dV ( x)
v  E   n
dx
dV ( x)
I  WCox[VGS  V ( x)  VTH ]n
dx
I/V Characteristics
dV ( x)
I  WCox[VGS  V ( x)  VTH ]n
dx
Now, at x=0 voltage at source end is Vgs-Vth so
V(x) = 0 and at X=L voltage at drain end is
Vgs-Vds-Vth so V(x)= Vds.

Idx  WnCox[VGS  V ( x)  VTH ]dV ( x)

L VDS

 Idx   W C
0 0
n [VGS  V ( x)  VTH ]dV ( x)
ox

W 1
I  nCox[(VGS  VTH )VDS  VDS 2 ]
L 2
Current in Triode Region
W 1
I  nCox[(VGS  VTH )VDS  VDS 2 ]
L 2

Peak of parabola occurs at Vds =Vgs-Vth for

different values of Vgs
1W
ID max  nCox(VGS  VTH ) 2
2 L

Vgs-Vth overdrive voltage

 MOSFET as Resistor

For very small value of Vds<<Vgs-Vth we can assume that I-V characteristics
is linear and MOSFET can work as Resistor in deep Triode Region
W 1
I  nCox[(VGS  VTH )VDS  VDS 2 ] ID  W nCox[(VGS  VTH )VDS ]
L 2 L
VDS 1
RON  
ID W nCox(VGS  VTH )
L
 Example 1
For the arrangement shown in the figure below, plot the on resistance of M1 as
a function of VG. Assume the following parameters.
W
nCox  50 A 2 ,  10 and VTH  0.7V
V L
First find out wether transistor is in deep triode .
To start the current flow Vgs≥Vth i.e Vg-Vs ≥Vth or we can
say that Vg ≥ Vs+Vth so Vgs ≥ 1.7V

Vds = Vd- Vs = 0-1 =-1 so Vds<<Vgs-Vth and MOSFET will be

operated in deep triode region.

1 1 1
RON   6
 M
W
nCox(VGS  VTH ) 10  50 10  (VG  1  0.7) 5(VG  1.7)
L
 Example 1 Contnd…

RON

VG
 Current In Saturation Region
In real, Drain current does not follow the
parabolic behavior for Vds>Vgs-Vth

Once Vds reaches to Vgs-Vth, channel will be

pinched-off and further increase in Vds will not
increase the drain current and transistor is
operated in saturation

W 1
ID  nCox[(VGS  VTH )VDS  VDS 2 ]
L 2
In equation if we replace Vds by Vgs-Vth we will get current when transistor is operated in
saturation .
1W
ID  nCox(VGS  VTH ) 2
2 L
 Summary of I/V Characteristics
NMOS Transistor PMOS Transistor

Vgs Vgs

Vgs<Vth Vgs≥Vth Vgs>Vth Vgs≤Vth

Cut-off ID=0 Cut-off ID=0

Vds<Vgs-Vth Vds > Vgs-Vth
Vds≥Vgs-Vth Vds ≤ Vgs-Vth

Triode
Saturation Saturation
W 1 1W
ID  nCox[(VGS  VTH )VDS  VDS 2 ] ID   nCox(VGS  VTH ) 2
1W L 2 2 L
ID  nCox(VGS  VTH ) 2
2 L Triode
W 1
ID   nCox[(VGS  VTH )VDS  VDS
L 2
 2nd Order Effect-Channel Length Modulation

L
VDS
1 W L
ID ( sat)  nCox(VGS  VTH ) 2 L
2 L(1  VDS )  VDS
L
1W
ID ( sat)  nCox(VGS  VTH ) 2 (1  VDS )
2 L
ID ( sat)  ID (1  VDS )
 The MOSFET as a Switch
VGS  V T
For NMOS
R on
S D

≤
For PMOS
MOSFET as a Switch
Example of MOSFET as a Switch

•The input is grounded ( 0v )

• Gate-source voltage less than
threshold voltage VGS < VTH
• MOSFET is “fully-OFF” (Cut-off region )
• No Drain current flows ( ID = 0 )
• VOUT = VDS = VDD = ”1″
• MOSFET operates as an “open switch”
Example of MOSFET as a Switch
• The input is VDD
• Gate-source voltage is much greater than
threshold voltage VGS > VTH
• MOSFET is “fully-ON” ( saturation region )
• Max Drain current flows ( ID = VDD / RL )
• VDS = 0V (ideal saturation)
• Min channel resistance RDS(on) < 0.1Ω
• VOUT = VDS = ≅0.2V due to RDS(on)
• MOSFET operates as a low resistance
“closed switch”
The MOSFET as a Switch
5
x 10
7

5
Req (Ohm)

0
0.5 1 1.5 2 2.5
VDD (V)