Milestone1 - Group 6

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Vietnam National University Ho Chi Minh City

Ho Chi Minh City University of Technology


Department of Electronics

EE3043: Computer Architecture

Laboratory Report
Milestone 1

Student
Group 6
Ta ̣ Quố c Khánh — 2013465
Nguyễn Hoàng Nguyên — 1911721
Huỳnh Tấn Luân — 2012515

Supervisor
Dr. Linh Tran

March 2024
EE3043: Computer Architecture

Table of Contents

Design of a Vending Machine 2

1. Objectives 2

1.1. Review of Basic Logic Design Theory for Sequential Circuits 2

1.2. Review of State Machine Diagram Drawing and Sequential Circuit Design 3

1.3. Understanding Sequential Circuit Design Using Hardware Description


Language (HDL) 4

1.4. Understanding Coding Structures (Coding Guidelines) in SystemVerilog 6

2. Analyses 6

2.1. Analyze design requirements 6

2.2. Analyze design solutions 6

3. Design 7

3.1. Input and output signals 7

3.3. Moore State Diagram 7

4. Results 9

4.1. Verification plan 9

4.2. Output functionality testing method 10

5. Discussion 14

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EE3043: Computer Architecture

Design of a Vending Machine


1. Objectives

1.1. Review of Basic Logic Design Theory for Sequential Circuits


A sequential circuit is an important type of electronic circuit in digital system
design, capable of storing states and changing over time. The fundamental difference
between a sequential circuit and a combinational circuit is its ability to "remember" –
a sequential circuit can retain information across clock cycles.
Basic Concepts
 Flip-Flop: The most basic element of a sequential circuit, typically used to
store binary states.
 State: Each flip-flop can be in one of two states, commonly referred to as SET
(1) or RESET (0).
 Clock pulse: Used to synchronize the state changes of flip-flops.
Basic Operation of Flip-Flops
 Set: When the Set (S) input is activated, the flip-flop switches to the SET
state.
 Reset: When the Reset input is activated, the flip-flop switches to the RESET
state.
 Hold: When neither Set nor Reset signals are present, the flip-flop holds its
current state.
Common Types of Flip-Flops
 SR Flip-Flop: Uses two inputs, Set and Reset, to control the state.
 JK Flip-Flop: An improved version of the SR Flip-Flop, allowing both J and
K inputs to be high without causing an undefined state.
 D Flip-Flop: Has a single D (Data) input; the flip-flop's state reflects the value
of the D input when a clock pulse is present.
 T Flip-Flop: Toggles its current state each time a clock pulse occurs.
Applications of Sequential Circuits
 Register: Used to store data in CPUs and digital devices.
 Counter: Counts the number of clock pulses or events.
 State Machine: Controls the flow of operations in a digital system.
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EE3043: Computer Architecture

Sequential Circuit Design


 Identify the states and transitions between them through a state diagram.
 Use design methodologies to create a sequential circuit that meets functional
and performance requirements.

1.2. Review of State Machine Diagram Drawing and Sequential


Circuit Design
A state diagram is a useful tool for describing the behavior of sequential
circuits. It helps design engineers easily identify the different states of the circuit and
how to transition between them.
Steps to Draw a State Diagram
1. Identify the initial state: This is the state from which the machine will start
operating.
2. List all states: This includes the initial state and any final states (if
applicable).
3. Identify events: These are the events that will trigger transitions from one
state to another.
4. Draw the states: Use circles to represent the states and clearly label the state
names inside them.
5. Draw the transitions: Use arrows to connect the states and label the
triggering events for each transition.
Types of State Machines
 Moore FSM: The output depends only on the current state.
 Mealy FSM: The output depends on both the current state and the inputs.
Sequential Circuit Design
1. Analyze requirements: Identify the desired function and behavior of the
circuit.
2. Build the state diagram: Based on the requirements, draw a state diagram
that accurately reflects the behavior of the circuit.
3. Choose storage elements: Typically flip-flops; select the type that fits the
design (SR, JK, D, T).
4. Design logic: Determine the logic for generating the next state and output
based on the current state and inputs.

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EE3043: Computer Architecture

5. Optimize: Simplify the state diagram and logic to reduce the number of
necessary elements.
Notes on Design
 Avoid asynchronous circuits: Ensure that all transitions are synchronized
with the clock pulse.
 Handle undefined states: Clearly define the behavior for any undefined or
undesirable states.

1.3. Understanding Sequential Circuit Design Using Hardware


Description Language (HDL)
Designing sequential circuits using HDL is a crucial part of developing digital
systems. HDL allows engineers to describe, simulate, test, and synthesize digital
circuit designs effectively.
Steps for Designing Sequential Circuits:
1. Identify Requirements: Analyze and specify the functional requirements
of the circuit.
2. Describe the Circuit Using HDL: Use languages like Verilog or VHDL to
describe the behavior of the circuit.
3. Simulate the Circuit: Test the circuit's behavior using simulation software.
4. Synthesize the Circuit: Convert the HDL description into a physical circuit
using synthesis tools.
5. Test and Verify: Ensure the circuit operates as described through various
testing methods.
HDL Languages:
1. Verilog: A hardware description language with C-like syntax, allowing for
the description of both the structure and behavior of digital circuits.
2. VHDL: Another hardware description language, using a syntax similar to
Ada, suitable for describing both combinational and sequential digital circuits.
Important Concepts in HDL:
1. Module/Entity: The basic building blocks in Verilog/VHDL corresponding
to the components of the circuit.
2. Port: The input/output ports of a module/entity, allowing communication
with the external environment.

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EE3043: Computer Architecture

3. Signal: Variables used to transmit data between modules/entities.


4. Process: A block in VHDL that allows for describing the sequential
behavior of the circuit.
FSM Model in HDL:
FSM (Finite State Machine): A finite state machine model is a powerful tool
for describing the behavior of sequential circuits.

FSM consists of two types:

 Moore FSM: This type generates outputs that do not directly depend on the
inputs of the FSM. The outputs are determined solely by the current state.
 Mealy FSM: This type generates outputs that directly depend on the inputs of
the FSM as well as the current state. This can result in faster response times
since the outputs can change immediately with input changes.

Moore Model Mealy Model

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EE3043: Computer Architecture

1.4. Understanding Coding Structures (Coding Guidelines) in


SystemVerilog
When programming, we must remind ourselves that we will not only see our
code once but multiple times for various reasons, such as debugging or improvement.
A clean code file can save a significant amount of valuable time. However, a "dirty"
code file can strain your eyes and confuse your mind, or worse, make you question
what you have done. Therefore, we can (or must) follow the programming guidelines
in the link below: style-guides/VerilogCodingStyle.md at master · lowRISC/style-
guides (github.com)

2. Analyses

2.1. Analyze design requirements


For the design requirements of an automatic beverage vending machine, the
following requirements must be met:

1. The vending machine is capable of accepting coins: ¢5 (Nickel), ¢10


(Dime), ¢25 (Quarter). However, it should only accept one coin at a time (per clock
cycle).

2. When the deposited amount exceeds ¢20, it should dispense a soda and
calculate the correct change.

3. The change is represented as a 3-bit data:

000: ¢0 010: ¢10 100: ¢20

001: ¢5 011: ¢15

2.2. Analyze design solutions


Thus, for the design of an automatic beverage vending machine according to
the above requirements, the design method should be carried out in the following
steps:

1. Identify the states for specific coin cases.

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EE3043: Computer Architecture

2. Based on the above states, draw the state diagram of a Mealy or Moore
machine.

3. The team will choose the design method based on the Moore state diagram
because the output signal in the Moore state machine does not depend on the
input and the current state, so the result will return to the next cycle.

4. After completing the state diagram, divide the design of this automatic
vending machine into three main parts: combinational input system, sequential
system, and combinational output system. The specific details of this three-
part diagram will be presented in section 3.

3. Design

3.1. Input and output signals


The input and output signals in the design of the automatic beverage vending
machine will be presented in the following table:

Signal Source Size Description

clk Global 1 Clock signal

rst_ni Global 1 Clock signal

nickel_i Input 1 1 if the coin type is used, 0 if the coin type is not
used

dime_i Input 1 1 if the coin type is used, 0 if the coin type is not
used

quarter_i Input 1 1 if the coin type is used, 0 if the coin type is not
used

soda_o Output 1 1 if the amount is ≥ 20¢ and 0 if the amount is ≤ 20¢

change_o Output 3 Change value if the amount > 20¢

3.3. Moore State Diagram


Based on the operation of the two-dimensional state table in section 3.2, the
team proposes the Moore state diagram represented as follows, with the states S0, S1,
S2, S3, S4, S5, S6, S7, S8.

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EE3043: Computer Architecture

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EE3043: Computer Architecture

4. Results

4.1. Verification plan


The goal of the design function verification method is to ensure that the
automatic beverage vending machine operates accurately according to the established
requirements and is free of errors during operation. To achieve this, we will use a
series of testing and simulation techniques to verify each part of the design.
Steps for performing the verification:
1. Set up the test environment: Prepare the testing environment, including the
necessary script files.
2. Establish functional output checks: Verify the basic functions of the design
by comparing the output expressions with the expected outputs achieved using
assertion functions.
3. Conduct testing: Run the test scripts in the established environment and
record the results. If step 2 encounters design function errors, return to step 1
and recheck the design until step 2 is free of errors.
4. Set up the testbench to check cases: List all test cases based on random
functions for input signals.
5. Simulation (Waveform): Evaluate the output results displayed in the
simulation window.
6. Analyze results: Assess the testing results and determine if there are any
errors that do not meet functional requirements.
7. Report and fix errors: If step 5 encounters design function errors, return to
step 1 and recheck the design until step 2 is free of errors.
Testing tools and methods:
 Waveform Simulation: Use simulation software available on the provided
server, such as Modelsim, Cadence, or Verilator, to test the behavior of the
circuit in different scenarios.
 Output Functionality Testing: Check if the output behaves as expected after
each user action.
 Output Functionality Testing: Check if the output behaves as expected after
each user action.

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EE3043: Computer Architecture

Conclusion: The design function verification method is a crucial part of the


product development process, ensuring that the automatic beverage vending machine
operates accurately and efficiently before being put into actual use. Thorough testing
will help detect and rectify errors early, thereby enhancing the quality and reliability
of the product.

4.2. Output functionality testing method


First, we need to create a task to compare the obtained output with the expected
output. If there is a difference, it will display the text “TEST FAILED”; if all cases
are correct, it will display the text “TEST PASSED”.

Image of the program segment that creates the task

To test the output functionality of the design, we divide it into different cases and
write a testbench for each corresponding case.

Case 1: Nickel = 0, Dime = 0, Quarter = 1

→ In Case 1, we insert 1 quarter (¢25) into the machine, resulting in a total amount of
¢25. Therefore, since the total amount is greater than ¢20, the machine will dispense a
soda can, and the soda_o signal will be activated to level 1, returning ¢5 in change,
corresponding to the change_o value of 001. The testbench code for Case 1 is written
as follows:

Image of the testbench code for Case 1

Case 2: Nickel = 0, Dime = 1, Quarter = 1

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EE3043: Computer Architecture

→ In Case 2, we insert 2 coins, consisting of 1 dime (¢10) and 1 quarter (¢25),


resulting in a total amount of ¢35. Therefore, since the total amount is greater than
¢20, the machine will dispense a soda can, and the soda_o signal will be activated to
level 1, returning ¢15 in change, corresponding to the change_o value of 011. The
testbench code for Case 2 is written as follows:

Image of the testbench code for Case 2

Case 3: Nickel = 1, Dime = 0, Quarter = 1

→ In Case 3, we insert 2 coins, consisting of 1 nickel (¢5) and 1 quarter (¢25),


resulting in a total amount of ¢30. Therefore, since the total amount is greater than
¢20, the machine will dispense a soda can, and the soda_o signal will be activated to
level 1, returning ¢10 in change, corresponding to the change_o value of 010. The
testbench code for Case 3 is written as follows:

Image of the testbench code for Case 3

Case 4: Nickel = 0, Dime = 0, Quarter = 0

→ In Case 4, we do not insert any coins into the machine, resulting in a total amount
of ¢0. Therefore, since the total amount is less than ¢20, the machine will not dispense
a soda can, the soda_o signal will not be activated to level 1, and no change will be

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EE3043: Computer Architecture

returned, corresponding to the change_o value of 000. The testbench code for Case 4
is written as follows :

Image of the testbench code for Case 4

Case 5: Nickel = 0, Dime = 2, Quarter = 0

→ In Case 5, as marked in the image, we sequentially insert 2 dimes (¢10) into the
machine, resulting in a total amount of ¢20. Therefore, initially, since the total amount
is still less than ¢20, the machine will not dispense a soda can; instead, it will go into
a waiting position. As a result, the waveform for soda_o will remain at level 0, and no
change will be returned. However, after inserting an additional ¢10, the total amount
will now be ¢20. Thus, since the total amount is sufficient, the machine will dispense
a soda can, the soda_o signal will be activated to level 1, and since the amount is
exact (with no surplus), the system will not return any change, corresponding to the
change_o value of 000. The testbench code for Case 5 is written as follows:

Image of the testbench code for Case 5

Case 6: Nickel = 1, Dime = 2, Quarter = 0

→ In Case 6, we sequentially insert 3 coins: 1 dime (¢10), 1 nickel (¢5), and 1 dime
(¢10), resulting in a total amount of ¢25. Therefore, initially, since the total amount is
still less than ¢20, the machine will not dispense a soda can; instead, it will go into a
waiting position. As a result, the soda_o signal will remain at level 0, and no change
will be returned. However, after inserting an additional ¢10, the total amount will now

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EE3043: Computer Architecture

be ¢25. Thus, since the total amount is sufficient, the machine will dispense a soda
can, the soda_o signal will be activated to level 1, and it will return ¢5 in change,
corresponding to the change_o value of 001. The testbench code for Case 6 is written
as follows:

Image of the testbench code for Case 6

Case 7: Nickel = 1, Dime = 2, Quarter = 0


→ In Case 7, we sequentially insert 3 coins: 1 dime (¢10), 1 nickel (¢5), and 1 quarter
(¢25), resulting in a total amount of ¢40. Initially, since the total amount is still less
than ¢20, the machine will not dispense a soda can and will go into a waiting state. As
a result, the soda_o signal will remain at level 0, and no change will be returned.
However, after inserting an additional ¢25, the total amount will now be ¢40.
Therefore, with a sufficient amount of money, the machine will dispense a soda can,
the soda_o signal will be activated to level 1, and ¢20 will be returned as change,
corresponding to the change_o value of 100. The testbench code for Case 7 is written
as follows:

Image of the testbench code for Case 7

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EE3043: Computer Architecture

After running the testbench code above, the cases listed above are shown. “TEST
PASSED” indicates that the designs are correct for the cases we have specified.

Results after running the testbench code

In addition, to verify the design, we can use waveforms. Below is the waveform
image of the design for the 7 cases listed above. It can be seen that the waveform
accurately and fully describes the cases mentioned above.

Image of the simulated waveform of the design

Conclusion: By writing the testbench program and checking the output waveform, we
can see that the design is correct in many cases.

5. Discussion

Through the implementation of Milestone 1, we have reviewed the knowledge


about state machine diagrams, how to establish the block diagram of a specific
system, and how to implement that block diagram in software. The simulation results
of the circuit operated as expected by the group. Additionally, the team was able to
assign individual tasks based on each person's strengths and ensure that the work was
carried out according to the initial group plan.

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