VLSI Design Unit 2

VLSI Design (EC 302)
Dr. Sumit Kale

Assistant Professor
Department of Electronics and Communication Engineering
DTU Delhi
VLSI Design (EC-302) 1

Unit-2
MOS Inverters

MOS INVERTERS:
Introduction
In MOS inverter circuits, both the input variable A and the output variable B are represented by
node voltages, referenced to the ground potential. Using positive logic convention, the Boolean (or
logic) value of "1" can be represented by a high voltage of VDD, and the Boolean (or logic) value of
"0" can be represented by a low voltage of 0.
Logic symbol and truth table of the inverter. Voltage transfer characteristic (VTC) of the ideal inverter

General circuit structure of an nMOS inverter. Typical voltage transfer characteristic (VTC) of a
realistic nMOS inverter.

Two critical voltage points on this curve, where the slope of the Vout(Vin) characteristic becomes
equal to -1, i.e.,
The smaller input voltage value satisfying this condition is called the input low voltage VIL, and the
larger input voltage satisfying this condition is called the input high voltage VIH.
As the input voltage is further increased, the output voltage continues to drop and reaches a value
of VOL (output low voltage) when the input voltage is equal to VOH. The inverter threshold voltage
Vth, which is considered as the transition voltage, is defined as the point where Vin = Vout, on the
VTC. Thus, a total of five critical voltages, VOL, VOH, VIL,VIH, and Vth, characterize the DC input-output
voltage behavior of the inverter circuit.

The functional definitions for the first four of these critical voltages are given
below.
Propagation of digital signals under the influence of noise.

Noise Immunity and Noise Margins
The noise immunity of the circuit increases with NM. Two noise margins will be
defined: the noise margin for low signal levels (NML) and the noise margin for high
signal levels (NMH).
Definition of noise margins NML and NMH

Resistive-Load Inverter
As the input voltage is increased beyond VT0., the driver transistor starts
conducting a nonzero drain current. Note that the driver MOSFET is
initially in saturation, since its drain-to source voltage. (VDS = Vout) is
larger than (Vin – VT0). Thus,
With increasing input voltage, the drain current of the driver also
increases, and the output voltage VOUT, starts to drop. Eventually, for input
voltages larger than Vout+VT0, the driver transistor enters the linear
operation region. At larger input voltages, the transistor
remains in linear mode, as the output voltage continues to decrease.
Resistive-load inverter circuit.

The various operating regions of the driver transistor and the corresponding input-
output conditions are listed in the following table.
Operating regions of the driver transistor in the resistive-load

inverter.
Typical VTC of a resistive-load inverter circuit.

Calculation of VOH
The output voltage Vout is given by
When the input voltage Vin is low, i.e., smaller than the threshold voltage of the
driver MOSFET, the driver transistor is cut-off. Since the drain current of the driver
transistor is equal to the load current, IR= ID = 0. It follows that the output voltage of
the inverter under these conditions is:
Calculation of VOL
To calculate the output low voltage VOL, we assume that the input voltage is equal
to VOH i.e., Vin = VOH = VDD. Since Vin – VT0 > Vout in this case, the driver transistor
operates in the linear region. Also note that the load current IR is
Eq. 1

Using KCL for the output node, i.e., IR = ID, we can write the following equation:
Eq. 2
This equation yields a simple quadratic in VOL, which is solved to find the value of
the output low voltage
Eq. 3
Note that of the two possible solutions of Eq. 3, we must choose the one that is
physically correct, i.e., the value of the output low voltage must be between 0 and
VDD. The solution of Eq. 3 is given below. It can be seen that the product (knRL) is
one of the important design parameters that determine the value of VOL.
Eq. 4

Calculation of VIL
By definition, VIL is the smaller of the two input voltage values at which the slope of
the VTC becomes equal to (-1),i.e., dVout/dVin, = - 1. Simple inspection of Fig. shows
that when the input is equal to VIL, the output voltage (Vout) is only slightly smaller
than VOH. Consequently, Vout > Vin- VT0, and the driver transistor operates in
saturation. We start our analysis by writing the KCL for the output node.
Eq. 5
To satisfy the derivative condition, differentiate both side of Eq. 5 with respect to
Vin, which results in the following equation:
Eq. 6

Since the derivative of the output voltage with respect to the input voltage is equal
to (-1) at VIL, we can substitute dVout/ dVin = - 1 in Eq. 6.
Eq. 7
Solving Eq. 7 for VIL, we obtain
Eq. 8
The value of the output voltage when the input is equal to VIL can also be found by
substituting Eq.8 into Eq. 5, as follows:
Eq. 9

Calculation of VIH
VIH is the larger of the two voltage points on VTC at which the slope is equal to (-1). It can
be seen from Fig. that when the input voltage is equal to VIH, the output voltage Vout,, is
only slightly larger than the output low voltage VOL. Hence, Vout < Vin – VT0, and the driver
transistor operates in the linear region. The KCL equation for the output node is given
below.
Eq. 10
Differentiating both sides of Eq. 10 with respect to Vin, we obtain
Eq. 11
Next, we can substitute dVout /dVin = - 1 into Eq. 11, since the slope of the VTC is equal
to (-1) also at Vin = VIH.

Eq. 12
Solving Eq. 12 for VIH yields the following expression.
Eq. 13
Thus, we obtain two algebraic equations, Eq. 10 and Eq. 13, for two unknowns, VIH
and Vout, To determine the unknown variables, we substitute Eq. 13 into the current
equation given by Eq. 10 above.
Eq. 14
The positive solution of this second-order equation gives the output voltage Vout
when the input is equal to VIH.
Eq. 15
Finally, VIH can be found by substituting Eq. 15 into Eq. 13, as follows.

Example: Consider a resistive-load inverter circuit with VDD=5 V, kn,'= 20 µA/V2, VT0= 0.8 V, RL
= 200 kΩ, and W/L = 2. Calculate the critical voltages (VOL, VOH VIL, VIH) on the VTC and find the noise margins
of the circuit.
Solution:
When the input voltage is low, i.e., when the driver nMOS transistor is cut-off, the output 159
high voltage can be found as
In this resistive-load inverter example, the transconductance of the driver transistor is
The output low voltage VOL is calculated by using

VIL is found as follows.
VIH can be calculated by using
The noise margins can be found as follows
Notice that the noise margin NML found here is quite low, and it may eventually lead to misinterpretation of
input signal levels. For better noise immunity, the noise margin for "low" signals should be at least about 25%
of the power supply voltage VDD , i.e., about 1.25 V.
Inverters with n-Type MOSFET Load
Enhancement-Load nMOS Inverter
(a) Inverter circuit with saturated enhancement-type nMOS load. (b) Inverter with linear enhancement-type load.

Saturated enhancement-nMOS load inverter
requires a single voltage supply and a relatively simple fabrication process, yet the
VOH level is limited to VDD – VT,Ioad .
Linear enhancement- nMOS load inverter
on the other hand, is always biased in the linear region. Thus, the VOH level is equal
to VDD, resulting in higher noise margins compared to saturated enhancement-load
inverter. The most significant drawback of this configuration is the use of two
separate power supply voltages.
“Both types of inverter circuits suffer from relatively high stand-by (DC) power
dissipation; hence, enhancement-load nMOS inverters are not used in any large-
scale digital applications.”

Depletion-Load nMOS Inverter
(a) Inverter circuit with depletion-type nMOS load. (b) Simplified equivalent circuit consisting of a nonlinear load resistor
and a nonideal switch controlled by the input.
The immediate advantages of implementing this circuit configuration are:
(i) sharp VTC transition and better noise margins,
(ii) single power supply, and
(iii) smaller overall layout area.
(iv) reduced standby leakage current
The gate and the source nodes of the load transistor are connected, hence, VGS,load
= 0 always. Since the threshold voltage of the depletion type load is negative, the
condition VGS,Ioad > VT,load is satisfied, and the load device always has a conducting
channel regardless of the input and output voltage levels. Both the driver transistor
and the load transistor are built on the same p-type substrate, which is connected
to the ground. Consequently, the load device is subject to the substrate-bias effect,
so that its threshold voltage is a function of its source-to substrate voltage, VSB,load =
Vout.
Eq. 1

When Vout < VDD + VT,load, the load transistor is in saturation. This condition
corresponds to VDS,load > VGS,load –VT,load. Then, the load current is given by the
following equation.
Eq. 2
For larger output voltage levels, i.e., for VOut > VDD + VT,load, the depletion-type load
transistor operates in the linear region. The load current in this case is
Eq. 3
The voltage transfer characteristic (VTC) of this inverter can be constructed by

setting ID,driver = ID,load, VGS,driver = Vin, and VDS,driver = Vout, and by solving the
corresponding current equations for Vout, = f(Vin). Figure shows the VTC of a typical
depletion-load inverter, with kn,driver = kn,load.

Next, we will consider the critical voltage
points VOH, VOL, VIL and VIH for this inverter
circuit. The operating regions and the voltage
levels of the driver and the load transistors
at these critical points are listed below.
Typical VTC of a depletion-load inverter circuit

Calculation of VOH
When the input voltage Vin is smaller than the driver threshold voltage VT0, the
driver transistor is turned off and does not conduct any drain current.
Consequently, the load device, which operates in the linear region, also has zero
drain current. Substituting VOH for Vout, in Eq. 3, and letting the load current ID,load =
0, we obtain
Eq. 4
The only valid solution in the linear region is VOH = VDD.
Calculation of VOL
To calculate the output low voltage VOL, we assume that the input voltage Vin of the
inverter is equal to VOH = VDD. Note that in this case, the driver transistor operates
in the linear region while the depletion-type load is in saturation.
Eq. 5

This second-order equation in VOL can be solved by temporarily neglecting the
dependence of VT,load on VOL, as follows.
Eq. 6
The actual value of the output low voltage can be found by solving the two
equations 6 and 1 using numerical iterations. The iterative method converges
rapidly because the actual value of VOL is relatively small.
Calculation of VIL
By definition, the slope of the VTC is equal to (-1), i.e., dVout/dvin = -1 when the
input voltage is Vin, =VIL. Note that in this case, the driver transistor operates in
saturation while the load transistor operates in the linear region. Applying KCL for
the output node, we obtain the following current equation:
Eq. 7

To satisfy the derivative condition at VIL we differentiate both sides of (Eq.7) with
respect to Vin.
Eq. 8
In general, we can assume that the term (dVT,Ioad/dVin) is negligible with respect to
the others. Substituting VIL for Vin, and letting dVout/dVin = -1, we obtain VIL as a
function of the output voltage Vout.
Eq. 9
To account for the substrate-bias effect on VT,LOad this equation must be solved
together with eq, 1 and eq. 9 using successive iterations.

Calculation of VIH
VIH is the larger of the two voltage points on the VTC at which the slope is equal to
(-1). Since the output voltage corresponding to this operating point is relatively
small, the driver transistor is in the linear region and the load transistor is in
saturation.
Eq. 10
Differentiating both sides of Eq. 10 with respect to Vin, we obtain:
Eq. 11
Now, substitute dVout/dVin = -1 in to Eq. 11, and solve for Vin = VIH.
Eq. 12

Note that the derivative of the load threshold voltage with respect to the output
voltage cannot be neglected in this case.
Eq. 13
The actual values of VIH and the corresponding output voltage Vout are determined
by solving Eq. 13 together with the current equation 10 and with the threshold
voltage expression 1, using numerical iterations. A relatively accurate first-order
estimate for VIH can be obtained by assuming that the output voltage in this case is
approximately equal to VOL.

CMOS Inverter
(a) CMOS inverter circuit. (b) Simplified view of the CMOS inverter, consisting of two complementary nonideal switches.

❑ Steady-state power dissipation of the CMOS inverter circuit is virtually negligible,
except for small power dissipation due to leakage currents.
❑ Exhibits a full output voltage swing between 0 V and VDD, and the VTC transition
is usually very sharp.
Eq. a
Eq. b

When the input voltage is smaller than the nMOS threshold voltage, i.e., when Vin,
< VT0,n, the nMOS transistor is cut-off. At the same time, the pMOS transistor is on,
operating in the linear region. Since the drain currents of both transistors are
approximately equal to zero (except for small leakage currents),,i.e.,
Eq. 1
The drain to source voltage of PMOS transistor is also equal to zero, and the output
voltage VOH is equal to the power supply voltage.
Eq. 2
When the input voltage exceeds (VDD + VT0,P), the pMOS transistor is turned off. In
this case, the nMOS transistor is operating in the linear region, but its drain to-
source voltage is equal to zero because condition Eq. 1 is satisfied. Consequently,
the output voltage of the circuit is
Eq. 3

The nMOS transistor operates in saturation if Vin>VT0,n and if the following condition
is satisfied.
Eq. 4
The pMOS transistor operates in saturation if Vin < (VDD + VT0,p), and if:
Eq. 5
Operating regions of the nMOS and the

pMOS transistors.

A typical CMOS inverter voltage transfer characteristic is also superimposed for
easy reference. Here, we identify five distinct regions, labeled A through E, each
corresponding to a different set of operating conditions.

Calculation of VIL
By definition, the slope of the VTC is equal to (-1), i.e., dVout/dVin = -1 when the
input voltage is Vin = VIL. In this case, the nMOS transistor operates in saturation
while the pMOS transistor operates in the linear region. From ID,n= ID,p,
Eq. 6
Using equations (a) and (b), this expression can be rewritten as
Eq. 7
To satisfy the derivative condition at VIL, we differentiate both sides of Eq. 7 with
respect to Vin.
Eq. 8

Substituting Vin = VIL and (dVoutldVin) = -1 in Eq. 8, we obtain
Eq. 9
The critical voltage VIL can now be found as a function of the output voltage Vout, as
follows:
Eq. 10
where kR is defined as
This equation must be solved together with the KCL eq. 7 to obtain the numerical
value of VIL and the corresponding output voltage, Vout.

Calculation of VIH
When the input voltage is equal to VIH, the nMOS transistor operates in the linear
region, and the pMOS transistor operates in saturation. Applying KCL to the output
node, we obtain
Eq. 11
Using eq. (a) and (b), this expression can be rewritten as
Eq. 12
Now, differentiate both sides of Eq. 12 with respect to Vin.
Eq. 13

Substituting, Vin = VIH and (dV0ut/dVin) =-1 in Eq. 13, we obtain
Eq. 14
The critical voltage VIH can now be found as a function of Vout, as follows:
Eq. 15
Again, this equation must be solved simultaneously with the KCL equation 12 to obtain the
numerical values of VIH and Vout.
Calculation of Vth
The inverter threshold voltage is defined as Vth = Vin = Vout. For Vin = Vout, both transistors
are expected to be in saturation mode; hence, we can write the following KCL equation.
Eq. 16

Replacing VGS,n and VGS,p in Eq. 16 according to eq. (a) and (b), we obtain
Eq. 17
The correct solution for Vin for this equation is
Eq. 18
Finally, the inverter threshold (switching threshold) voltage Vth is found as
Eq. 19

Design of CMOS Inverters
The CMOS inverter can, by virtue of its complementary push-pull operating mode, provide a full
output voltage swing between 0 and VDD, and therefore, the noise margins are relatively wide. Thus,
the problem of designing a CMOS inverter can be reduced to setting the inverter threshold to a
desired voltage value.
Typical VTC and the power

supply current of a CMOS
inverter circuit.

Given the power supply voltage VDD, the nMOS and the pMOS transistor threshold
voltages, and the desired inverter threshold voltage Vth, the corresponding ratio kR
can be found as follows. Reorganizing (Eq. 19) yields
Eq. 20
Now solve for kR that is required to achieve the given Vth.

Eq. 21
Recall that the switching threshold voltage of an ideal inverter is defined as

Eq. 22
Substituting (Eq. 22) in (Eq. 21) gives
Eq. 23

for a near-ideal CMOS VTC that satisfies the condition (Eq. 22). We can achieve
completely symmetric input-output characteristics by setting the threshold
voltages as VT0 = VT0,n = IVT0,PI. This reduces (Eq. 23) to:
Eq. 24
Note that the ratio kR is defined as
Eq. 25
assuming that the gate oxide thickness tox, and hence, the gate oxide capacitance
Cox have the same value for both nMOS and pMOS transistors. The unity-ratio
condition (Eq. 24) for the ideal symmetric inverter requires that

Eq. 26
Hence,
Eq. 27
In (Eq. 26) for electron and hole mobilities are typical values, and that exact µn and
µp values will vary with surface doping concentration of the substrate and the tub.

Voltage transfer characteristics of three CMOS inverters, with different nMOS to PMOS ratios.
For a symmetric CMOS inverter with VT0,n = IVT0,PI and kR = 1, the critical voltage VIL
can be found, as follows
Eq. 28
Also the critical voltage VIH is found as

Eq. 29
Note that the sum of VIL and VIH is always equal to VDD in a symmetric inverter.
Eq. 30
The noise margins NML and NMH for this symmetric CMOS inverter are now
calculated

Which are equal to each other, and also to VIL.
Supply Voltage Scaling in CMOS Inverters

Neglecting second-order effects such as subthreshold conduction, it can be seen
that the CMOS inverter will continue to operate correctly with a supply voltage
which is as low as the following limit value.
This means that correct inverter operation will be sustained if at least one of the
transistors remains in conduction, for any given input voltage.

Voltage transfer characteristics of a CMOS inverter, obtained with different power
supply voltage levels.
MOS INVERTERS: SWITCHING CHARACTERISTICS
Cascaded CMOS inverter stages

This combined capacitance at the output node will be called the load capacitance,
Cload.
Eq. 1
• Csb,n and CSb,p have no effect on the transient behavior of the circuit since the
source-to-substrate voltages of both transistors are always equal to zero.
• The capacitances Cgs,n and Cgs,p are also not included because they are connected
between the input node and the ground (or the power supply).

First-stage CMOS inverter with lumped output load capacitance.

Delay-Time Definitions
The propagation delay times tPHL and tPLH
tPHL is the time delay between the V50%-transition of the rising input voltage and the
V50% -transition of the falling output voltage.
tPLH is defined as the time delay between the V50%- transition of the falling input
voltage and the V50%-transition of the rising output voltage.
tPHL becomes the time required for the output voltage to fall from VOH to the V50%
level, and tPLH becomes the time required for the output voltage to rise from VOL to
the V50% level. The voltage point V50% is defined as follows.
Eq. 2

Input and output voltage waveforms of a typical inverter, and the definitions of propagation delay times. The
input voltage waveform is idealized as a step pulse for simplicity.
Thus, the propagation delay times tPHL and tPLH are found from Fig. as
Eq. 3
The average propagation delay tp of the inverter characterizes the average time
required for the input signal to propagate through the inverter.
Eq. 4
The rise time trise is defined here as the time required for the output voltage to rise
from the V10% level to V90% level.
The fall time tfall is defined here as the time required for the output voltage to drop
from the V90% level to V10% level. The voltage levels V10% and V90% are defined as
Eq. 5
Eq. 6

Output voltage rise and fall times.
Thus, the output rise and fall times are found from Fig. as follows.
Eq. 7
Note that other delay definitions using 20% and 80% voltage levels have also been used.
Calculation of Delay Times
Average Capacitance Current Method
estimating the average capacitance current during charge down and charge
up, respectively. If the capacitance current during an output transition is
approximated by a constant average current Iavg, the delay times are found as
Eq. 8
Eq. 9
the average current during high-to-low transition can be calculated by using
the current values at the beginning and the end of the transition.
Eq. 10

Similarly, the average capacitance current during low-to-high transition is
Eq. 11
the average-current method neglects the variations of the capacitance current

between the beginning and end points of the transition.
Differential equation Method
The propagation delay times can be found more accurately by solving the state
equation of the output node in the time domain. The differential equation
associated with the output node is given below. Note that the capacitance current
is also a function of the output voltage.
Eq. 12

First, we consider the rising-input case for a CMOS inverter. Initially, the output
Voltage is assumed to be equal to VOH. When the input voltage switches from low
(VOL) to high (VOH), the nMOS transistor is turned on and it starts to discharge the
load capacitance. At the same time, the pMOS transistor is switched off; thus,
Eq. 13
The circuit given in Fig. 2 can now be reduced to a single nMOS transistor and a
capacitor, as shown in Fig. 5. The differential equation describing the discharge
event is then
Eq. 14
Equivalent circuit of the CMOS inverter during high-to-low output transition.

The, input and output voltage waveforms during this high-to-low transition are
illustrated in Fig. When the nMOS transistor starts conducting, it initially operates
in the saturation region. When the output voltage falls below (VDD - VT), the nMOS
transistor starts to conduct in the linear region. These two operating regions are
also shown in Fig.
Input and output voltage waveforms during high-to-low transition.

First, consider the nMOS transistor operating in saturation.
Eq. 15
Since the saturation current is practically independent of the output voltage

(neglecting channel-length modulation), the solution of (Eq. 14) in the time interval
between t0 and t1’ can be found as
Eq. 16
Evaluating this simple integral yields

Eq. 17

At t = t1', the output voltage will be equal to (VDD – VT,n) and the transistor will be at
the saturation-linear region boundary. Next, consider the nMOS transistor
operating in the linear region.
Eq. 18
The solution of (Eq. 14) in the time interval between t1' and t1 can be found as
Eq. 19

Evaluating this integral yields
Eq. 20

Eq. 21
Finally the propagation delay time for high to low output transition can be found by combining eq. 17 and 21
Eq. 22
For VOH = VDD and VOL = 0, as is the case for the CMOS inverter eq. 22 becomes
Eq. 23

Example: For the CMOS inverter shown in Fig. with a power supply voltage of VDD = 5 V, determine the fall time tfall,
which is defined as the time elapsed between the time point at which Vout = V90% = 4.5 V and the time point at which VOut
= V10% = 0.5 V. Use both the average-current method and the differential equation method for calculating tfall. The
output load capacitance is 1 pF. The nMOS transistor parameters are given as

The fall time using the differential equation approach. The nMOS transistor operates in the saturation region for
4.0 V≤Vout ≤ 4.5 V. Writing the current equation for the saturation region, we obtain
Integrating this simple expression yields the time during which the nMOS transistor operates in saturation

Switching Power Dissipation of CMOS Inverters
During switching events where the output load capacitance is alternatingly charged up and charged down, the
CMOS inverter inevitably dissipates power.
CMOS inverter used in the dynamic power-dissipation analysis.

Eq. 1
Since during switching, the nMOS transistor and the pMOS transistor in a CMOS inverter conduct current for
one-half period each, the average power dissipation of the CMOS inverter can be calculated as the power
required to charge up and charge down the output load capacitance.
Typical input and output voltage waveforms and the capacitor current waveform during switching of the CMOS inverter.
Eq. 2
Eq. 3
Eq. 4
Noting that f=1/T, this expression can also be written as
Eq. 5

Dissipation Due to Direct-Path Currents
The finite slope of the input signal causes a direct current path between VDD and GND for a short
period of time during switching, while the NMOS and the PMOS transistors are conducting
simultaneously.
Under the (reasonable) assumption that the resulting current spikes can be approximated as triangles
and that the inverter is symmetrical in its rising and falling responses, we can compute the energy
consumed per switching period,
as well as the average power consumption
The direct-path power dissipation is proportional to the switching activity, similar to the capacitive
power dissipation. tsc represents the time both devices are conducting.

Short-circuit currents during transients.
I is determined by the saturation current of the devices and is hence directly proportional to the
peak
sizes of the transistors. The peak current is also a strong function of the ratio between input and
output slopes.

Static power consumption
The static (or steady state) power dissipation of circuit is expressed by
Ideally, the static current of the CMOS inverter is equal to zero.,
Sources of leakage currents in

CMOS inverter (for Vin = 0 V).

The junction leakage currents are caused by thermally generated carriers. Their value increases with increasing
junction temperature, and this occurs in an exponential fashion. At 85C (a common junction temperature limit
for commercial hardware), the leakage currents increase by a factor of 60 over their room-temperature values.
An emerging source of leakage current is the subthreshold current of the transistors. The closer the threshold
voltage is to zero volts, the larger the leakage current at VGS = 0 V and the larger the static power consumption.
To offset this effect, the threshold voltage of the device has generally been kept high enough.
The total power consumption of the CMOS inverter is now expressed as the sum of its three components:
In typical CMOS circuits, the capacitive dissipation is by far the dominant factor. The direct-path consumption
can be kept within bounds by careful design, and should hence not be an issue. Leakage is ignorable at present,
but this might change in the not too distant future.

Power-Delay Product
The power-delay product (PDP) is a fundamental parameter used for measuring the quality and
performance of a CMOS process and gate design. The power-delay product is defined as the average
energy required for a gate to switch its output voltage from low to high and from high to low.
In a CMOS logic gate, energy is dissipated
(i) by the pMOS network while the output load capacitance Cload is being charged up from 0 to VDD,
(ii) by the nMOS network while the output load capacitance is being charged down from
VDD to 0.
The amount of energy required to switch the output can be found as

The energy described is mainly dissipated as heat when the nMOS and pMOS transistors conduct current during
switching. Thus, from a design point-of-view, it is desirable to minimize the power-delay product. Since the PDP
is a function of the output load capacitance and the power supply voltage, the designer should try to keep
both Cload and VDD as small as possible when designing a CMOS logic gate. The power delay product is also
defined
where P*av is the average switching power dissipation at the maximum operating frequency and Tp is the
average propagation delay,

The Power-Delay Product, or Energy per Operation
The power-delay product (PDP) as a quality measure for a logic gate.
The PDP presents a measure of energy, as is apparent from the units (Wsec = Joule). Assuming that the gate is
switched at its maximum possible rate of fmax = 1/(2tp), and ignoring the contributions of the static and direct-
path currents to the power consumption, we find
The PDP stands for the average energy consumed per switching event (this is, for a 0→1, or a 1→0
transition). Remember that earlier we had defined Eav as the average energy per switching cycle (or per energy-
consuming event). As each inverter cycle contains a 0→1, and a 1→0 transition, Eav hence is twice the PDP .
Energy-Delay Product
A more relevant metric should combine a measure of performance and energy. The energy-delay product (EDP)
does exactly that
Eq. 1

Analyzing the voltage dependence of the EDP. Higher supply voltages reduce delay, but harm the energy, and
the opposite is true for low voltages. An optimum operation point should hence exist. Assuming that NMOS and
PMOS transistors have comparable threshold and saturation voltages, we can simplify the propagation delay
expression.
Eq. 2
where VTe = VT + VDSAT/2, and a technology parameter.
Eq. 3
The optimum supply voltage can be obtained by taking the derivative of Eq. 3 with respect to VDD, and equating
the result to 0.
Eq. 4

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VLSI Design (EC 302)

Dr. Sumit Kale

VLSI Design (EC-302) 1

VLSI Design (EC-302) 2

VLSI Design (EC-302) 3

VLSI Design (EC-302) 4

VLSI Design (EC-302) 5

Propagation of digital signals under the influence of noise.

VLSI Design (EC-302) 6

Definition of noise margins NML and NMH

Resistive-load inverter circuit.

VLSI Design (EC-302) 8

Operating regions of the driver transistor in the resistive-load

Typical VTC of a resistive-load inverter circuit.

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Solving Eq. 12 for VIH yields the following expression.

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In this resistive-load inverter example, the transconductance of the driver transistor is

The output low voltage VOL is calculated by using

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VIH can be calculated by using

The noise margins can be found as follows

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The voltage transfer characteristic (VTC) of this inverter can be constructed by

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Typical VTC of a depletion-load inverter circuit

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Operating regions of the nMOS and the

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Finally, the inverter threshold (switching threshold) voltage Vth is found as

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Typical VTC and the power

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Now solve for kR that is required to achieve the given Vth.

Recall that the switching threshold voltage of an ideal inverter is defined as

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Also the critical voltage VIH is found as

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