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Task and Functions: Vinchip Systems Chennai

This document discusses tasks and functions in Verilog HDL. Functions are used for procedures that are combinational with a single output, while tasks can contain timing constructs and have multiple inputs/outputs. The key differences are that functions must be combinational with a single output, while tasks can model timed behavior and pass multiple values in and out. Both can be used to reuse common Verilog code by defining procedures locally within a module.

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Quang Hiệp Ngô
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53 views21 pages

Task and Functions: Vinchip Systems Chennai

This document discusses tasks and functions in Verilog HDL. Functions are used for procedures that are combinational with a single output, while tasks can contain timing constructs and have multiple inputs/outputs. The key differences are that functions must be combinational with a single output, while tasks can model timed behavior and pass multiple values in and out. Both can be used to reuse common Verilog code by defining procedures locally within a module.

Uploaded by

Quang Hiệp Ngô
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Task and Functions

VinChip Systems
(A Design and Verification Company)

Chennai
Goal of presentation
Reusing code
Tasks and Functions

2005 Verilog HDL 2


Introduction
Procedures/Subroutines/Functions in SW
programming languages
The same functionality, in different places
Verilog equivalence:
Tasks and Functions
Used in behavioral modeling

2005 Verilog HDL 3


Contents
Functions
Tasks
Differences between tasks and functions

2005 Verilog HDL 4


Tasks and Functions
Functions
Functions
Keyword: function, endfunction
Can be used if the procedure
does not have any timing control constructs
returns exactly a single value
has at least one input argument

2005 Verilog HDL 6


Functions (contd)
Function Declaration and Invocation
Declaration syntax:

function <range_or_type> <func_name>;


<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction

2005 Verilog HDL 7


Functions (contd)
Function Declaration and Invocation
Invocation syntax:
<func_name> (<argument(s)>);

2005 Verilog HDL 8


Functions (contd)
Semantics
much like function in Pascal
An internal implicit reg is declared inside the function
with the same name
The return value is specified by setting that implicit reg

2005 Verilog HDL 9


Function Examples
Parity Generator
module parity; function calc_parity;
reg [31:0] addr; input [31:0] address;
reg parity; begin
calc_parity = ^address;
initial begin end
endfunction
end
endmodule
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = %b",
calc_parity(addr) );
end

2005 Verilog HDL 10


Tasks and Functions
Tasks
Tasks

Keywords: task, endtask


Must be used if the procedure has
any timing control constructs
zero or more than one output arguments
May be on or more input arguments

2005 Verilog HDL 12


Tasks (contd)
Task declaration and invocation
Declaration syntax
task <task_name>;
<I/O declarations>
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask

2005 Verilog HDL 13


Tasks (contd)
Task declaration and invocation
Task invocation syntax
<task_name>;
<task_name> (<arguments>);

input and inout arguments are passed into the task


output and inout arguments are passed back to the
invoking statement when task is completed

2005 Verilog HDL 14


Tasks (contd)
I/O declaration in modules vs. tasks
Both used keywords: input, output, inout
In modules, represent ports
connect to external signals
In tasks, represent arguments
pass values to and from the task

2005 Verilog HDL 15


Task Examples
Use of input and output arguments
module operation; task bitwise_oper;
parameter delay = 10; output [15:0]
ab_and, ab_or,
reg [15:0] A, B; ab_xor;
reg [15:0] AB_AND, AB_OR, AB_XOR; input [15:0] a, b;
begin
initial #delay ab_and = a & b;
$monitor( ); ab_or = a | b;
ab_xor = a ^ b;
initial end
begin endtask

end
endmodule
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end

2005 Verilog HDL 16


Tasks and Functions
Differences between
Tasks and Functions
Differences between...
Functions Tasks
Can enable (call) just Can enable other tasks and
another function (not task) functions
Execute in 0 simulation May execute in non-zero
time simulation time
No timing control May contain any timing
statements allowed control statements
At lease one input May have arbitrary
Return only a single value input, output, or inout
Do not return any value

2005 Verilog HDL 18


Differences between (contd)
Both
are defined in a module
are local to the module
can have local variables (registers, but not nets) and events
contain only behavioral statements
do not contain initial or always statements
are called from initial or always statements or other tasks or
functions

2005 Verilog HDL 19


Differences between (contd)
Tasks can be used for common Verilog code
Function are used when the common code
is purely combinational
executes in 0 simulation time
provides exactly one output
Functions are typically used for conversions and
commonly used calculations

2005 Verilog HDL 20


2005 Verilog HDL 21

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