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    156DF - Vlsi Design

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    malleswarimalleswari584
    VLSI

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    156DF - Vlsi Design

    Uploaded by

    malleswarimalleswari584
    7 views1 page
    VLSI

    Original Title

    156DF - VLSI DESIGN (1)

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    © © All Rights Reserved

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    PDF, TXT or read online from Scribd

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    VLSI

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    7 views1 page

    156DF - Vlsi Design

    Uploaded by

    malleswarimalleswari584
    VLSI

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 1

    Code No: 156DF R18

    JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD


    B. Tech III Year II Semester Examinations, August - 2022
    VLSI DESIGN
    jn
    (Electronics and Communication Engineering)
    Time: 3 Hours Max.Marks:75
    t
    Answer any five questions
    uh
    All questions carry equal marks
    ---

    1.a) Explain n-well CMOS Process with necessary sketches.


    b) Explain MOS system under external bias with necessary diagram. [8+7]
    us
    2.a) Derive the Drain to source current Ids versus voltage Vds relationship for a NMOS
    Transistor when the transistor is in i) Non-saturated region. ii) Saturated region.
    ed
    b) Discuss about the MOS transistor figure of merit W0. [8+7]

    3.a) Draw the stick diagram, and layout diagram of NMOS inverter.
    b) Draw and explain the CMOS lambda based design rules for transistors and wires. [7+8]
    pa
    4.a) Draw the stick diagram and mask layout for CMOS two input NOR gate.
    b) Discuss CMOS design style. Compare with nMOS design style. [8+7]
    pe
    5.a) Draw and explain fan-in and fan-out characteristics of different CMOS design
    technologies.
    b) What are the alternate gate circuits are available? Explain any one of item with
    ra
    suitable sketch. [8+7]

    6.a) Explain the concept of driving large capacitive loads with, relevant examples.
    ug
    b) Discuss the inverter delay and propagation delay. [8+7]

    7.a) Explain step-by-step subsystem design approach. Consider an example.


    -2
    b) Compare SRAM and DRAM. [8+7]

    8.a) Discuss the overflow of system on chip designs.


    02
    b) Explain the FPGA design flow. [7+8]
    2
    ---oo0oo---

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