2020 - Technologies For Normally-Off GaN HEMTs

137
Technologies for Normally-off GaN HEMTs

Giuseppe Greco 1 , Patrick Fiorenza 1 , Ferdinando Iucolano 2 , and Fabrizio
Roccaforte 1
1
Consiglio Nazionale delle Ricerche – Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII,
n. 5 – Zona Industriale, 95121 Catania, Italy
2 STMicroelectronics, Stradale Primosole 50, 95121 Catania, Italy
4.1 Introduction
One of the most interesting features of GaN-based materials is the presence of
a two-dimensional electron gas (2DEG) in heterostructures (e.g. AlGaN/GaN,
AlN/GaN, and InAlN/GaN), which gives the possibility to fabricate high electron
mobility transistors (HEMTs) [1]. Because of the presence of a 2DEG with a high
charge density and mobility, AlGaN/GaN HEMTs are inherently normally-on
devices. These devices are excellent components for high-frequency applications.
In fact, today, the 5G technology is the driving force for large semiconductor
companies to develop GaN-on-Si HEMTs for power amplifiers, high-efficiency
devices in RF, microwave, and millimeter-wave (mmW) applications [2].
However, GaN is also a suitable material for power electronics. In particular,
for power switching applications, the use of normally-off transistors is highly
preferred, not only to simplify the gate drive configuration but also for safety rea-
sons [3–5]. In fact, if the gate driver fails and the gate bias goes to zero voltage,
a normally-off HEMT switches to the off-state, avoiding circuit burnout prob-
lems. Obviously, this is a more safe condition than having a switch remaining in
the on-state. Hence, in the past 10 years, many efforts have been made to explore
the viable routes toward the development of reliable normally-off GaN HEMT
technologies.
From the physical point of view, to achieve the normally-off operation, the
threshold voltage (V th ) must be shifted in the positive bias direction. Practically,
to achieve this goal, the region below the gate contact in GaN-based heterostruc-
tures must be properly modified.
This chapter is focused on the most common and feasible approaches to obtain
normally-off HEMTs on GaN-based heterostructures.
Although the “cascode” configuration, combining a Si MOSFET with a
normally-on GaN HEMT, can enable to realize a chip with normally-off
operation, “true” normally-off GaN HEMTs are requested in many applications.
Nitride Semiconductor Technology: Power Electronics and Optoelectronic Devices,

First Edition. Edited by Fabrizio Roccaforte and Mike Leszczynski.
© 2020 Wiley-VCH Verlag GmbH & Co. KGaA. Published 2020 by Wiley-VCH Verlag GmbH & Co. KGaA.
138 4 Technologies for Normally-off GaN HEMTs
The first approaches toward the achievement of “true” normally-off HEMTs

consisted in the thinning of the AlGaN barrier layer (recessed gate) or the intro-
duction of fluorine ions in the gate region. Although both approaches resulted
in a positive shift of the threshold voltage, they also exhibited some limitations,
which pushed the technology to move toward more robust solutions.
The natural evolution of these device concepts was the fabrication of
recessed-gate metal insulator semiconductor high electron mobility transistors
(MISHEMTs). These devices are continuously object of scientific interest, but
a number of issues, related to the control of threshold voltage and dielectric
reliability, have hindered their commercialization.
The real breakthrough in normally-off HEMT technology was the introduc-
tion of the p-GaN gate HEMT, which allows to obtain a stable positive threshold
voltage and is not affected by the instability issues of the insulated gate devices
(https://epc-co.com/epc). As a matter of fact, today, the p-GaN gate HEMT is the
only solution available on the market together with the HEMT cascode (https://
www.infineon.com and https://www.transphormusa.com).
Other “unconventional” solutions have been proposed in the literature to
achieve normally-off GaN HEMT operation. Although these approaches are
very far from a real application, they will be mentioned at the end of this chapter
to provide additional inputs for the comprehension of the physics behind the
GaN HEMT technology.
4.1.1 Threshold Voltage in AlGaN/GaN HEMTs

To obtain a normally-off AlGaN/GaN HEMT, an accurate control of the
2DEG sheet charge density (ns ) is required. Figure 4.1 schematically shows the
ΦB
EC
ΔEC
EF
EF(X)
Schottky dAIGaN
gate
AIxGa1–xN GaN
Figure 4.1 Schematic conduction band diagram of an AlGaN/GaN heterostructure in the

Schottky gate region of a HEMT.
4.1 Introduction 139
conduction band diagram of an AlGaN/GaN heterostructure in the Schottky

gate region of a conventional HEMT. The device threshold voltage (V th ) is
defined as the bias needed to deplete the 2DEG under the gate region.
In AlGaN/GaN HEMTs, the threshold voltage V th depends on the different
characteristics of the heterostructure (residual doping, polarization charges, bar-
rier layer thickness, etc.) and has been often described by the following analytical
expression [6]:
𝜎(x) qND
Vth (x) = ΦB (x) + EF (x) − ΔEC (x) − d − (d )2
𝜀0 𝜀AlGaN (x) AlGaN 2𝜀0 𝜀AlGaN (x) AlGaN
(4.1)
where ΦB is the metal/AlGaN Schottky barrier height, EF is the energy differ-
ence between the intrinsic Fermi level and the GaN conduction band edge (and
depends on the sheet charge density of the 2DEG [7]), 𝜎 is the polarization charge
that uniquely depends on the Al-concentration x [7], and dAlGaN , N D , and 𝜀AlGaN
are the barrier layer thickness, doping, and permittivity, respectively.
For a typical AlGaN/GaN heterostructure used for normally-on HEMTs, i.e.
with dAlGaN = 20 nm, x = 25%, and N D ∼ 1 × 1017 cm−3 , considering a barrier
height ΦB = 1 eV, a threshold voltage V th = −4.6 V can be predicted using
Eq. (4.1).
Clearly, Eq. (4.1) gives an indication on the main parameters that can be tailored
to move the V th toward positive values.
An increase of the metal/AlGaN Schottky barrier height ΦB results into a
positive shift of the threshold voltage V th . However, the typical values of the
metal/AlGaN barrier height are limited to the range of 0.8–1.2 eV [8–10]. Hence,
a positive V th shift of only 0.4 eV can be obtained by maximizing the barrier
height of the metal gate. Based on these considerations, it is clear that acting on
the Schottky barrier height of the metal gate is not an efficient solution to obtain
the normally-off operation.
Changing the Al-concentration x and the thickness of the AlGaN barrier layer
dAlGaN produces more significant variations of the threshold voltage V th . As an
example, considering again an AlGaN/GaN heterostructure with dAlGaN = 20 nm,
a reduction of the Al-concentration x from 25% to 10% leads to a shift of V th
from −4.6 to −1.2 V. Moreover, for an Al-concentration x = 25%, a shift of V th
from −4.6 to −1.9 V is expected by reducing the AlGaN thickness from 20 to
10 nm. However, the sheet carrier density in the 2DEG ns decreases by reducing
the AlGaN barrier layer thickness dAlGaN (see Eq. (1.11)). Hence, dAlGaN cannot
be reduced below a critical thickness of few nanometers [11]. The recessed-gate
HEMT, described in Section 4.3.1, is based on the reduction of dAlGaN and has the
peculiarity that the AlGaN thinning is done only below the gate region, without
pauperizing the 2DEG in the access region of the device.
In Eq. (4.1), the value of EF depends on the 2DEG sheet charge density and
typically increases by increasing the sheet charge density [7].
The conduction band offset ΔEC at the AlGaN/GaN interface depends on the
band gap of the Alx Ga1−x N alloy used as a barrier layer. As an example, a decrease
of the Al-concentration from 30% to 20% translates into a change of the band
offset ΔEC from 0.42 to 0.27 eV (see Eq. (4.1)) [12, 13]. For an AlGaN thickness
of 20 nm, it will result in a V th shift of 2.5 V.
As already seen in Chapter 1, the polarization charge (𝜎) depends on both the
spontaneous (PSP ) and piezoelectric (PPE ) polarization, and these parameters in
the AlGaN barrier layer are determined by the Al-concentration x [7].
The AlGaN doping concentration (N D ) also has an impact on V th , as it
determines the conduction band bending in the barrier layer [14]. Moreover,
an increase of the AlGaN donor concentration N D causes a polarization field
screening, which deepens the potential well and increases the 2DEG concen-
tration [15]. In this context, the introduction of an additional negative charge
(e.g. fluorine ions) in the AlGaN barrier layer to deplete the 2DEG is another
possibility to positively shift V th , as will be discussed in Section 4.3.2.
Although the use of a high metal/AlGaN barrier height can produce only a
small positive V th shift, the use of a p-type GaN gate layer on the top of the
AlGaN/GaN heterostructure can raise the AlGaN conduction band of an amount
comparable with the GaN band gap (3.4 eV). Hence, the p-GaN gate HEMT, dis-
cussed in Section 4.3.4, is one of the most efficient routes to obtain a positive
threshold voltage in GaN-based heterostructures.
Finally, it is worth mentioning that the presence of other charges, e.g. trapped
in the surface and in the buffer, can also have a strong impact on the experimental
values of threshold voltage V th in GaN HEMTs. These coulombic effects are not
explicitly considered in Eq. (4.1). For that reason, it is always extremely difficult
to well reproduce the experimental data using the analytical expression of V th .
4.2 GaN HEMT “Cascode”

Driven by commercial market requirements, some companies (IR, Sharp,
and Transphorm) have overpassed the difficulties in achieving a single-chip
normally-off GaN HEMT by using the so-called “cascode” structure. Such
configuration has been originally proposed by Baliga to obtain a stable pos-
itive threshold voltage in 4H–SiC transistors (JFETs) [16]. However, the first
high-voltage (HV, 600 V) normally-off GaN HEMT cascode was released into
the market by Transphorm in 2015 [17].
In a cascode structure, a HV normally-on GaN HEMT is connected in series
with a low-voltage (LV) normally-off Si MOSFET. Figure 4.2 schematically shows
the equivalent circuit of the normally-off GaN HEMT cascode and the two
devices connected in the package.
Using this configuration, the gate-to-source voltage (V GS ) in GaN HEMT is
equivalent to source-to-drain voltage (V DS ) in Si MOSFET. Then, the switch
between off- and on-states of the GaN HEMT can be easily controlled by the
normally-off Si MOSFET. The two devices share the same channel current in the
on-state, while in the off-state, the blocking voltage is distributed between them.
The application of a positive gate bias to the Si MOSFET above its thresh-
old voltage will turn-on this device. In this condition, the gate voltage of the
GaN HEMT is close to zero and, then, this normally-on transistor is turned-on.
4.2 GaN HEMT “Cascode” 141
HV normally on
LV normally off GaN HEMT
Si MOSFET
S D GaN
D Si D S
G
G G S G D
S G S D
(a) (b)
Figure 4.2 (a) Equivalent circuit of a normally-off GaN HEMT cascode, connecting a
high-voltage (HV) normally-on GaN HEMT with a low-voltage (LV) normally-off Si MOSFET.
(b) Schematic representation of the two devices connected in a package.
Because the two devices are connected in series, in the on-state, the same channel
current will flow through the two devices.
On the other hand, when the Si MOSFET is turned-off by removing the gate
voltage, an applied bias to the drain terminal creates a negative gate-to-source
voltage on the GaN HEMT, contributing to deplete the 2DEG in the HEMT chan-
nel. Then, the device will be in the off-state and any further increase of the drain
voltage will drop on the GaN HEMT. Hence, because of the high critical field
of GaN, a high breakdown voltage can be reached with the cascode configura-
tion. Practically, in a 600 V GaN HEMT cascode, most of the bias drops on the
GaN HEMT, while the resistance added by the low-voltage Si MOSFET is very
low (about 3% of the total resistance). On the other hand, if the rated voltage is
reduced to 50 V, the on-resistance of the GaN HEMT decreases. Consequently,
the percentage contribution of the on-resistance from the Si MOSFET increases.
This concept is illustrated in Figure 4.3, showing the percentage on-resistance
contribution from the Si MOSFET as a function of rated voltage in a commercial
GaN HEMT cascode [18]. For this reason, the GaN HEMTs cascode are preferred
for the voltage classes of 600 and 900 V (https://www.infineon.com and https://
www.transphormusa.com).
An advantage of the GaN HEMT cascode is the protection offered by the Si
MOSFET to avoid GaN gate breakdown. As an example, for a 600 V normally-on
GaN HEMT, the gate breakdown voltage is around −35 V. Therefore, using a 30 V
Si MOSFET enables to turn-off the GaN HEMT, while leaving some secure mar-
gin between turn-off and V th of the GaN HEMT.
Moreover, from the reliability point of view, the cascode configuration is a
more robust solution with respect to other approaches for normally-off GaN
(e.g. p-GaN HEMT and recessed-gate hybrid MISHEMT). Indeed, because the
cascode configuration uses a normally-on HEMT, the electric field on the gate
in the on-state is low because of the fact that the gate voltage is zero. Different
is the case of a “true” normally-off HEMT, where a positive gate bias has to be
applied to turn-on the device, leading to many reliability issues [19]. This finally
Figure 4.3 Percentage of on-resistance from Si

Cascode configuration
40 HV GaN HEMT + LV Si MOSFET MOSFET in a normally-off GaN HEMT cascode.
from Si-MOSFET (%) Source: Adapted with permission of Lidow et al.
2014 [18]. Copyright © 2014, Wiley VCH.
Percentage RON
30
20
10
0
0 200 400 600
Rated breakdown voltage (V)
automatically solves any criticism for one of the important tests of the standard
qualification procedure (JEDEC, AEC-Q100/101), i.e. the high-temperature gate
bias (HTGB) [20].
Finally, the fabrication of normally-on HEMTs for the cascode configuration
is simpler than that of a “true” normally-off GaN HEMT, as will be seen in
Section 4.3.
Although the “cascode” configuration has the advantage to be driven by
conventional Si MOSFET drivers, this solution exhibits some drawbacks. As
an example, the series connection of the two devices increases the package
complexity and introduces parasitic inductances that affect the switching
performance of the system. In fact, the two dies are typically connected inside
the package with wire bonds or in a planar architecture (see schematic in
Figure 4.2b). Then, the switching performance of the HEMT cascode relies
heavily on the parasitic inductances in the package, especially between the two
dies and also on how well the junction capacitances of the two are matched.
If the inductances are too high, or the capacitances are not matched well, the
switching losses can increase significantly [21].
Moreover, the advantage of the high-temperature operation offered by a
“pure GaN” device is lost in the HEMT cascode because of the presence of a Si
device [22].
For those reasons, the power electronics market requires the adoption of “true”
normally-off HEMT solutions, and several semiconductor companies all over the
word are working to develop such a technology.
4.3 “True” Normally-off HEMT Technologies

4.3.1 Recessed-gate HEMT
The use of recessed-gate contacts in GaN-based HEMT technology has always
been an attractive topic for the scientific community working on AlGaN/GaN
heterostructures. At the early stages, recessed-gate HEMTs have been fabricated
to minimize the parasitic resistance and achieve a high transconductance
[23–26]. As a side approach, the recessed gate, obtained by a plasma etch below
4.3 “True” Normally-off HEMT Technologies 143
Recessed
Nonrecessed
Source Drain ΦB
Gate ΔEC
EC
AlGaN dAlGaN-recessed
2DEG
Schottky dAlGaN
GaN gate
AlGaN GaN
(a) (b)
Figure 4.4 (a) Schematic cross section of a recessed-gate normally-off AlGaN/GaN HEMT.
(b) Conduction band diagram of the AlGaN/GaN heterostructure below the gate region before
(dashed line) and after the recession (continuous line) of the barrier layer.
the gate electrode, has been considered to obtain a positive shift of the threshold
voltage V th [27, 28]. In fact, as can be deduced from Eq. (4.1), a reduction of
the AlGaN barrier layer thickness dAlGaN leads to a decrease of the 2DEG sheet
carrier concentration and to a positive shift of V th .
Figure 4.4 schematically depicts a recessed-gate AlGaN/GaN HEMT, in which
a partial thinning of the AlGaN barrier has been obtained below the gate contact
by a plasma etch process. Clearly, in this configuration while the 2DEG channel is
depleted below the gate, in the device access regions (source-gate and gate-drain),
the high sheet charge density and low resistance are preserved.
Saito et al. [29] introduced the recessed-gate concept, demonstrating the
possibility to achieve a considerable positive V th shift (i.e. from −4 to −0.14 V)
by reducing the AlGaN thickness from 30 to 9.5 nm. Many other works
[16, 17, 30–35] reported on positive V th shifts in the range of 0.1–0.5 V, main-
taining an AlGaN thickness below the gate contact between 6.5 and 13 nm.
Table 4.1 reports a collection of literature data obtained in recessed-gate
GaN-based HEMTs. Clearly, a direct correlation of the V th values with the resid-
ual AlGaN thickness is not simple, as those experiments have been carried out on
heterostructures with different Al-concentration x. Moreover, the metal/AlGaN
interface quality is strongly influenced by the plasma etch condition used for the
recession, whose effect on the final V th is difficult to quantify. However, from
Table 4.1, it is evident that the values of V th in the recessed-gate HEMT are
always close to zero (in the range 0.05–0.5 V).
Although Saito et al. [29] did not obtain a positive threshold voltage, they
observed a linear correlation between the measured V th and the thickness of
the residual AlGaN layer below the gate contact. From this correlation, shown
in Figure 4.5 for the case with an Al-concentration of 25%, it was possible to
extrapolate the normally-off condition for a residual AlGaN thickness smaller
than 8.2 nm [29]. A similar correlation between the residual AlGaN thickness
after plasma etch and the experimental V th has also been observed in other
works [31, 34].
Table 4.1 Collection of literature data obtained in recessed-gate AlGaN/GaN HEMTs.
Residual AlGaN Threshold

AlGaN Al- Threshold thickness after voltage after
thickness concentration voltage gate recession gate recession
dAlGaN (nm) x (%) V th (V) (nm) V th (V) References
10 10 – – +0.05 [27]
18 25 – – +0.075 [28]
30 25 −4.42 9.5 −0.14 [29]
25 33 −4.2 13 +0.1 [30]
22 27 −2.2 7 +0.47 [31]
38 35 −0.6 10 +0.51 [32]
22 22 −2.7 6.5 +0.1 [33]
25 25 −1.5 3 −0.1 [34]
25 25 −4 10 +0.5 [35]
1 Figure 4.5 Experimental values of the threshold

voltage V th as a function of the residual AlGaN
Normally-off
0 barrier layer thickness in recessed-gate
Threshold voltage (V)
Normally-on AlGaN/GaN HEMTs. Source: The data are taken

from Refs. [29, 31, 34].
–1
–2
–3
Saito et al. 2008
Hao et al. 2008
–4 Anderson et al. 2010
0 5 10 15 20 25 30
Residual AlGaN thickness (nm)
Inductively coupled plasma (ICP) or reactive ion etching (RIE) based on the
chemistry of Cl2 or BCl3 is typically used to etch the GaN or AlGaN layers and
are widely used processes in recessed-gate HEMT technology [36]. However, the
nanometric control of the recessed AlGaN layer thickness and the achievement of
the desired V th is not simple. In fact, plasma-induced damage of the recessed-gate
region represents a serious concern in this technology because of the increase of
the gate leakage current or the device on-resistance [30–33, 37].
A possible solution to overcome the drawbacks of the plasma etch in the
recessed-gate region is the use of a selective area growth (SAG) of the AlGaN
barrier layer [38]. This technology starts from an AlGaN/GaN heterostructure
with a very thin AlGaN barrier layer. On this material, an additional SAG of
AlGaN is carried out on the access regions of the device. In this way, the exposure
of the gate region to the plasma etch process is avoided. He et al. [35] compared
the recessed-gate normally-off HEMTs fabricated by standard ICP with those
fabricated with the SAG of AlGaN layer in the access regions. Although the
value of the threshold voltage obtained with the SAG approach (V th = +0.4 V)
was comparable to that of a standard ICP recession (V th = +0.5 V), avoiding
the use of plasma below the gate electrode allowed to obtain a reduction of
the gate leakage current and higher values of saturation current I Dmax and
transconductance g m .
4.3.2 Fluorinated HEMT

The incorporation of negative charges in the gate region represents another pos-
sible approach to positively shift V th and obtain a normally-off HEMT.
This concept was first proposed by Cai et al. [39] that controlled the thresh-
old voltage V th through the introduction of fluorine (F) ions in the AlGaN/GaN
heterostructure using a CF4 plasma treatment. The presence of fluorine in the
sample was verified by means of secondary ion mass spectrometry (SIMS) [40].
Figure 4.6 reports a schematic in cross section of a fluorine-implanted HEMT,
together with a conduction band diagram of this system to explain the physics
behind. When a certain amount of immobile negative charges is introduced (e.g.
by plasma or ion implantation) inside the AlGaN barrier layer under the gate
electrode (Figure 4.6a), these charges will electrostatically deplete the 2DEG in
the channel region.
Fluorine (F) is the most electronegative element of the periodic table. When F
is introduced in interstitial sites in the AlGaN matrix, close to the neighboring
atoms (Al, Ga, or N), it tends to capture a free electron, becoming a negative fixed
charge. The immobile negative F− -ions incorporated in the AlGaN barrier layer
will raise the potential of the AlGaN of an additional quantity ΦF , thus causing the
depletion of the 2DEG. Consequently, the threshold voltage V th will be positively
shifted and a normally-off condition can be achieved. This situation is illustrated
in Figure 4.6b, which compares the conduction band diagram of an AlGaN/GaN
heterostructure before and after a fluorine treatment.
E Before F treatment
After F treatment
ΦF –
– –
–
–
–
Source Gate Drain
F– F– F– F–
ΦB
AlGaN ΔEC EC
–
F– F F– F–
2DEG
EF
GaN Schottky AlGaN
gate GaN
(a) (b)
Figure 4.6 (a) Schematic cross section of a normally-off fluorinated AlGaN/GaN HEMT.
(b) Conduction band diagram of a fluorinated HEMT structure (continuous line). The band
diagram of the AlGaN/GaN heterostructure before the F treatment is also reported for
comparison (dashed line).
2 Figure 4.7 Calculation of the threshold

voltage V th in fluorinated GaN HEMT as a
1 function of incorporated fluorine
concentration. The following parameters
Normally-off have been assumed for this calculation: an

0
Normally-on Al-concentration x = 30%, an AlGaN
thickness dAlGaN = 20 nm, and a barrier height
–1 ΦB = 1 eV. Under these conditions, the
normally-off behavior occurs for a fluorine
–2 concentration NF = 1.6 × 1019 cm−3 .
–3
–4
0 1 2 3
Fluorine concentration (×1019) (cm–3)
To consider the effect of fluorine incorporation on the threshold voltage

V th , the last term of Eq. (4.1) can be rewritten in an approximate form as
q(ND −NF )
2𝜀AlGaN
(dAlGaN )2 , i.e. including the electrostatic effect caused by a uniform
distribution of negative F− -ions N F [39]. Accordingly, it is possible to estimate
the threshold voltage of a fluorine-implanted HEMT for different concentrations
N F in the AlGaN layer, as reported in Figure 4.7. An AlGaN layer with an
Al-concentration x = 30%, an AlGaN thickness dAlGaN = 20 nm, and a barrier
height ΦB = 1 eV have been assumed for such calculation.
Under these conditions, the transition from a normally-on to a normally-off
behavior occurs for a fluorine concentration N F = 1.6 × 1019 cm−3 . This value
corresponds to a sheet carrier density of 3.2 × 1013 cm−2 within the 20 nm thick
barrier layer.
A similar result has been reported by Cai et al. [39] that estimated a F − sheet
concentration of about 3 × 1013 cm−2 to compensate both the AlGaN doping N D
and the polarization-induced charges 𝜎.
In the fluorine-implanted gate technology, the plasma process conditions are
extremely important, as they influence the final performances of the fabricated
device. Cai et al. [39] investigated different CF4 plasma conditions of power
(90–200 W) and duration (20–180 seconds), demonstrating the possibility to
obtain threshold voltage values V th = +0.9 [39, 41]. Figure 4.8 shows the thresh-
old voltage V th as a function of the process duration for different F-based plasma
power conditions, i.e. 90 and 150 W, on two different heterostructures [39, 41].
The threshold voltage V th of the untreated heterostructures is different in the
two cases, depending on their characteristics. However, in both cases, V th
increased with the plasma process duration because of the increasing amount of
incorporated F-ions. On the other hand, an increase of the plasma power enables
the F-ions to penetrate deeper inside the AlGaN layer. Clearly, the negative
immobile charges must be localized as closest as possible to the 2DEG channel,
in order to efficiently deplete the 2DEG and maximize the V th shift. Moreover,
the V th value changes much faster when the plasma power is increased.
An interesting effect observed in fluorine-implanted HEMTs was a 4 orders
of magnitude reduction of the gate current (from 10−2 to 10−6 A/mm) [39]. This
Figure 4.8 Threshold voltage V th as a 2

function of plasma process duration for 90 W (Chen et al. 2011)
F-based plasma treatments performed on 1 150 W (Cai et al. 2006)
two different heterostructures. Source: The Normally-off

data are taken from [39, 41]. 0
Normally-on
–1
–2
–3
–4
0 50 100 150 200

Plasma process duration (s)
latter can be explained with the electrostatic effect of the immobile negative
charges, leading to an upward bending of the AlGaN conduction band and an
additional barrier ΦF to the gate diode current flow in both forward and reverse
bias (see Figure 4.6b).
However, the effect of fluorine treatments on Schottky contacts is controver-
sial. As an example, Chu et al. [42] explained the reduction of the gate leakage
current after CF4 plasma treatment with the formation of an insulating surface
layer, which passivates the surface states and reduces the recombination current
as well as the tunneling current [43]. In addition, the possibility that nonvolatile
F-based compounds are created during the plasma process, and act as an insulat-
ing surface layer blocking the leakage current, was also considered [44]. Indeed,
TEM micrographs of fluorine-treated AlGaN/GaN heterostructures show a con-
siderable amount of crystalline defects [45], thus suggesting the presence of a
highly resistive defect-rich region.
In this context, the effect of fluorine-based plasma process on the electrical
properties of AlGaN/GaN heterostructures has been monitored by means of
local current measurements carried out by conductive atomic force microscopy
(C-AFM) [45]. In this experiment, schematically illustrated in Figure 4.9a–d,
the surface of an AlGaN/GaN heterostructure has been first patterned by a
photoresist hard mask to selectively expose some regions to the effect of a CHF3
plasma and then scanned by means of C-AFM after the photoresist hard mask
removal. As can be seen in Figure 4.9e, the current maps acquired on the sample
surface revealed a significant reduction of the current in the regions exposed
to the CHF3 plasma process. This evidence is consistent with the reduction of
the leakage current observed by other authors and can be related either to a
screening of the 2DEG or to an increase of the local resistance of the AlGaN
because of plasma-induced damage.
The thermal stability is another important concern for the practical implemen-
tation of the fluorine plasma approach in normally-off GaN HEMTs.
In fact, common to all fluorinated GaN HEMTs is a drain–current degradation,
correlated with a deterioration of the 2DEG channel mobility. In this context,
thermal annealing processes at moderate temperatures (e.g. 400 ∘ C, 10 minutes)
Lithography
Photoresist
250 pA Current map
AlGaN AlGaN
2DEG 2DEG
GaN GaN F-treated

region
(a) (b)
Untreated
F-based plasma region
F– F– F– F
–
F
–
F– F– F– AlGaN 20 μm
2DEG
AlGaN
2DEG
GaN
GaN (e)
(d)
(c)
Figure 4.9 (a–d) Schematic of the process sequence used to localize fluorine ions on selective
regions of the AlGaN/GaN heterostructure surface. (e) C-AFM current map of the sample,
showing a different electrical behavior between the fluorine-treated regions and the
untreated ones. Source: Adapted from Greco et al. [45]. The Ref. [45] is an Open Access article
distributed under the terms of the Creative Commons Attribution License. Copyright © 2011
by the authors; licensee Springer.
showed the possibility to repair the plasma-induced damage and obtain a partial
recover (about 76%) of the drain current [39].
The physical mechanism of fluorine incorporation and its stability in
AlGaN/GaN heterostructures is still an open issue because of the complexity of
the scenario [46]. In fact, the thermal annealing processes not only contribute to
the plasma-induced damage recovery but also influence the fluorine distribution
in the heterostructure. In particular, the fluorine diffusion in AlGaN or GaN is
a process assisted by Ga-vacancies [47]. Accordingly, during annealing, fluorine
tends to diffuse in regions with higher concentration of Ga-vacancies, i.e. toward
the AlGaN surface where a large number of defects have been created by the
plasma process [48]. On the other hand, by increasing annealing time, a large
number of Ga-vacancies are annihilated, so that fluorine diffusion stops and the
immobile negative charges are stabilized in the AlGaN layer [48]. Of course,
extended defects, such as dislocations, can affect the diffusion process, making a
precise control of threshold voltage in fluorinated GaN HEMTs difficult [49].
19 +
F -ion implantation, at energies in the order of 10–50 keV and a dose of
1 × 1012 cm−2 , has also been used as an alternative to the plasma processes to
introduce fluorine into the AlGaN/GaN heterostructures [50]. In particular,
a beam energy of 50 keV results in a F-concentration peak located at a depth
of about 64 nm. Lower implantation energies move the F-concentration peak
closer to the AlGaN/GaN interface. Noteworthy, using F-ion implantation
improved the V th stability with respect to the plasma treatment because of the
deeper F-profile reached by implantation [50]. On the other hand, the higher
fluorine concentration obtained by plasma treatments results in a much efficient
depletion of the 2DEG and, then, in a larger positive threshold voltage shift.
Recently, Shen et al. [51] used AlF3 as diffusion source to introduce fluorine in
the gate region in the AlGaN barrier layer. In particular, an AlF3 layer has been
evaporated on the AlGaN surface and annealed in N2 . After annealing, the AlF3
layer was removed by wet etching. In this way, fluorine could reach a diffusion
depth of about 20 nm, thus leading to a considerable positive V th shift from −2.5
to 1.8 V.
The natural evolution of the fluorine implantation technology to obtain
normally-off HEMTs was the combination of the fluorination with a partial
AlGaN gate recession. Liu et al. [52] used a controlled CF4 plasma etch to reduce
the thickness of the AlGaN layer below the gate and simultaneously introduce
immobile negative charge in the gate region. With this approach, it was possible
to obtain a threshold voltage V th = +0.6 V and a reasonable thermal stability of
the normally-off behavior from room temperature to 200 ∘ C.
Clearly, the gate leakage current can represent a serious concern in GaN-based
HEMTs. Hence, the use of an insulator below the metal gate is a common method
to reduce the leakage current, forming the so-called MISHEMTs [53]. However,
in general, the introduction of a gate insulator in MISHEMTs produces a varia-
tion of the threshold voltage with respect to a standard HEMT with a Schottky
gate [54]. Roberts et al. [55] introduced the fluorine incorporation technology
in AlGaN/GaN MISHEMTs, using in situ fluorine doping of an Al2 O3 insulating
layer grown by atomic layer deposition (ALD). In particular, using the in situ flu-
orination of Al2 O3 during the ALD in combination with a fluorine implantation
of the gate region enabled the authors to obtain a V th = +2.35 V.
On the other hand, Zhang et al. [56] demonstrated that a modulation of the V th
is possible by a precise control of the F-plasma AlGaN etching and the thickness
of a gate insulator (Al2 O3 ). In fact, in this approach, the negative charges intro-
duced by the F-treatment compensate the positive charges present in the gate
insulator.
All these issues are crucial in the recessed-gate hybrid MISHEMT technology
and will be better clarified in Section 4.3.3.
4.3.3 Recessed-gate Hybrid MISHEMT

In a recessed-gate hybrid MISHEMT, the AlGaN barrier layer under the gate elec-
trode is removed by means of a plasma etch process, and this recessed region
is subsequently covered by an insulator and a gate electrode. A schematic of
this device is depicted in Figure 4.10, together with the conduction band dia-
gram in the recessed-gate region. The device is often called “hybrid” as it can be
described as the combination of a transistor controlled by a metal insulator semi-
conductor (MIS) gate (i.e. where the AlGaN barrier layer and the 2DEG have been
removed) connected in series with two access regions in which the AlGaN/GaN
heterostructure remains unaltered. Because of the fact that the 2DEG is inter-
rupted in the recessed-gate region, such a transistor is a normally-off structure.
Hence, a positive bias must be applied to the MIS gate in order to accumulate a
negative charge in the recessed region and enable the conduction between the
source and drain electrodes.
Source Drain Dielectric

Gate
EC
AlGaN
Dielectric
2DEG 2DEG
EF
GaN Metal
GaN
gate
(a) (b)
Figure 4.10 (a) Schematic cross section of a normally-off recessed-gate hybrid GaN MISHEMT.
(b) Conduction band diagram in the recessed-gate region.
The first studies highlighting the potentialities and limitations of this device
for power switching applications were reported in the years 2008–2010,
demonstrating recessed-gate hybrid MISHEMTs with V th up to +2 V and
RON < 10 mΩ cm2 using SiO2 as a gate insulator [57–62]. Afterward, several
progresses have been done until Freedsman et al. [63] demonstrated the feasi-
bility of fabricating recessed-gate hybrid MISHEMT on large-area (200 mm) Si
substrates with high breakdown voltage and low leakage current, using an Al2 O3
layer as the gate insulator.
As mentioned before, the insulated gate channel is the main block of
a recessed-gate hybrid MISHEMT. The total on-resistance of the device
RON_(MISHEMT) is given by the sum different contributions:
RON (MISHEMT) = 2RC + RSG (2DEG) + RGD (2DEG) + Rch (4.2)
where RC is the contact resistance of the source/drain electrodes, RSG_(2DEG) and
RGD_(2DEG) are the access resistance contributions, and Rch is the resistance of the
recessed channel region, i.e. where the 2DEG has been removed.
The channel resistance Rch , expressed in Ω mm, can be written as:
Lg
Rch = (4.3)
qnch 𝜇ch
where Lg is the recessed-gate length, nch and 𝜇ch are the accumulated sheet charge
density and the carrier mobility in the recessed channel region, respectively, and
q is the elementary charge. Hence, this resistive contribution depends on the
channel length Lg , and on the sheet charge density and mobility of the electrons
moving in the recessed channel.
Clearly, the removal of the 2DEG in the gate region has a significant impact on
the total device RON_(MISHEMT) . To make this concept clear, it is useful to quantify
the sheet charge density nch accumulated in the recessed-gate channel of the
device. This charge density can be expressed as nch = C ox × (V gs − V th ), where
C ox is the accumulation capacitance of the gate insulator. Considering, as an
example, a 50 nm thick SiO2 gate insulator (with 𝜀SiO2 = 3.9), having an oxide
capacitance C ox = 6.9 × 10−8 F/cm2 , for a gate bias well above the threshold
100 100
Lg = 1 μm
Lg = 2 μm
RON_(MiSHEMT) (Ω mm)
RON_(MiSHEMT) (Ω mm)
80 80
Lg = 3 μm
Lg = 4 μm
60 60
40 40
µch = 100 cm2/(V s)
20 µch = 150 cm2/(V s) 20
µch = 200 cm2/(V s)
µch = 250 cm2/(V s)
0 0
0 2 4 6 8 10 0 100 200 300 400
(a) Gate length, Lg (μm) (b) Channel Mobility, µch (cm2/(V s))
Figure 4.11 Total on-resistance RON_(MISHEMT) of a recessed-gate hybrid MISHEMT calculated (a)
as a function of the gate length Lg for different channel mobility values and (b) as a function of
the channel mobility 𝜇ch for different gate lengths.
voltage (i.e. V gs − V th = 4–6 V), the accumulated sheet charge density nch will be
in the range of 2.7–4.1 × 1012 cm−2 . These values are evidently much lower with
respect to the sheet charge density available in a 2DEG. Hence, the recessed-gate
hybrid MISHEMT is limited in terms of on-resistance and saturation drain
current. Moreover, as described later on, also the mobility of the electrons in
the recessed-gate channel of a MISHEMT is typically lower with respect to the
mobility of the 2DEG.
Hence, for a fixed transistor gate length Lg , a recessed-gate hybrid MISHEMT
is expected to have a higher on-resistance with respect to other technological
solutions not implying the 2DEG removal.
Figure 4.11 reports the total on-resistance of a recessed-gate hybrid MISHEMT
RON_(MISHEMT) calculated as a function of the gate length Lg for different chan-
nel mobility values (a) and as a function of the channel mobility 𝜇ch for differ-
ent gate lengths (b). For this calculation, we assumed a source–drain distance of
10 μm, a contact resistance RC = 0.5 Ω mm, and a semiconductor sheet resistance
RSH = 400 Ω/sq.
As can be seen in Figure 4.11a, for a given channel mobility 𝜇ch , the
RON_(MISHEMT) increases linearly with the gate length Lg . Moreover, for a given
geometry (fixed Lg ) (see Figure 4.11b), the RON_(MISHEMT) becomes lower with
the increase of the channel mobility 𝜇ch , until a saturation is reached for high
electron channel mobility values, i.e. when the recessed channel resistance Rch
becomes less important with respect to the other contributions (RC , RSG_(2DEG) ,
and RGD_(2DEG) ).
The physical and electronic properties of the recessed channel (i.e. roughness
and electronic quality of the insulator/GaN interface) have a significant influence
on the channel mobility 𝜇ch and, hence, on the total on-resistance RON_(MISHEMT)
of the device.
In the literature, several materials have been used as gate insulators in
recessed-gate hybrid MISHEMTs (SiO2 , SiN, Al2 O3 , AlN/SiN, etc.) [53, 64, 65].
250 Figure 4.12 Field effect mobility 𝜇FE as

Al2O3 (Im et al. 2010) a function of V GS –V th for recessed-gate
AlN/SiN (Greco et al. 2017)
SiN (Oka and Nozawa 2008)
hybrid GaN MISHEMTs using SiO2 ,
200 SiO2 (Fiorenza et al. 2017) AlN/SiN, SiN, or Al2 O3 gate insulators.
Field effect mobility
Source: The data are taken from Refs.

µFE (cm2/(V s))
[71–74].
150
100
50
0
–2 –1 0 1 2 3 4
Vg – Vth (V)
The values of the specific on-resistance RON_(MISHEMT) for transistors with gate
lengths in the order of 1–2 μm, extracted in the operation conditions, range
typically between 7.2 and 22 Ω mm [66–70].
Regarding the mobility, the parameter typically used to describe the channel
properties in recessed-gate hybrid MISHEMTs is the field effect mobility 𝜇FE
defined as:
Lg
𝜇FE = g
W Cox VDS m
where Lg and W are the gate length and gate width, respectively, C ox is the specific
capacitance of the gate oxide, V DS is the applied drain-to-source bias, and g m is
the device transconductance.
The values of the maximum field effect mobility reported in the literature for
recessed-gate hybrid GaN MISHEMTs vary in a wide range (∼30–250 cm2 /(V s))
with values of threshold voltage V th between 1 and 2 V [70].
Figure 4.12 reports the field effect channel mobility 𝜇FE of recessed-gate hybrid
GaN MISHEMTs fabricated using SiO2 , AlN/SiN, SiN, and Al2 O3 as gate insu-
lators. As can be seen, the field effect mobility curves 𝜇FE increase with the gate
bias V GS up to a maximum 𝜇FE(peak) and then decrease at high electric field. It can
be seen that the use of Al2 O3 allowed a higher mobility peak (∼225 cm2 /V s) [71],
with respect to AlN/SiN (∼180 cm2 /V s) [72], SiN (∼110 cm2 /V s) [73], or SiO2
(∼110 cm2 /V s) [74]. However, the mobility curves of Al2 O3 /GaN and SiN/GaN
MISHEMTs drop with a steeper slope at higher V gs –V th values. The mobility
behavior with the electric field is typically associated with the occurrence of dif-
ferent scattering mechanisms limiting the current transport at the insulator/GaN
recessed interface.
In this context, monitoring the dependence of the channel mobility on the
temperature can give useful information on the physical mechanisms limiting
the current transport in the recessed-gate MISHEMT. Recently, the field effect
mobility in a recessed-gate hybrid MISHEMTs employing SiO2 as a gate insu-
lator has been studied by Fiorenza et al. [74] starting from the model proposed
by Pérez-Tomás et al. [75–77] for GaN MOSFETs and normally-on MISHEMTs.
Figure 4.13 Peak values of the field 2000

Experimental data
effect mobility 𝜇FE (peak) (experimental Bulk µB
data) as a function of the temperature Surface roughness µSR
Acoustic phonon µac
for a recessed-gate hybrid SiO2 /GaN
µFE (peak) (cm2/ (V s))

µB Coulomb µC
MISHEMT. The experimental data are 1000 Total µTOT
fitted considering all the contributions µSR
of bulk 𝜇B , roughness 𝜇SR , phonon
scattering 𝜇AC , and Colombian
300
scattering 𝜇C . Source: Adapted with µac
permission of Fiorenza et al. [74]. 200 µC
Copyright © 2017, IEEE.
100
µTot
0
300 350 400 450
Temperature (K)
In particular, the different temperature-dependent contributions to the mobility

have been adapted to the specific case of the normally-off recessed-gate hybrid
MISHEMT, in which electrons are induced in the channel when the gate elec-
trode is in accumulation condition [70].
The peak mobility 𝜇FE(peak) as a function of the measurement temperature for
a recessed SiO2 /GaN MISHEMT is reported in Figure 4.13. As can be noticed,
the experimental values of 𝜇FE(peak) slightly decrease with increasing measure-
ment temperature. In analogy to a standard MOSFET, the channel mobility was
expressed including in the Matthiessen’s rule different scattering contributions,
i.e. the bulk mobility factor (𝜇B ), the acoustic phonon scattering (𝜇AC ), the sur-
face roughness scattering (𝜇SR ), and the Coulomb scattering (𝜇C ) due to inter-
face charges [76]. Using the experimental values of interface-trapped charges
(Qtrap = 1.35 × 1012 cm−2 ) and root mean square roughness of the recessed GaN
surface (RMS = 0.15 nm) enabled the authors to obtain a good fit of the experi-
mental temperature dependence of the total mobility 𝜇TOT .
From this analysis, it can be argued that the main limiting factors for the carrier
transport in the channel are the surface roughness scattering (𝜇SR ), the acoustic
phonon scattering (𝜇AC ), and the Coulomb scattering (𝜇C ) contributions. Hence,
the optimization of the dielectric/GaN interface in the recessed channel, i.e. in
terms of roughness and the interface trap density, is a fundamental issue to opti-
mize the mobility and consequently the RON of the device.
The quality of the gate insulator is a crucial issue in recessed-gate MISHEMT
technology also for the stability of the device characteristics. In fact, the presence
of trapping states located in different positions at the insulator/GaN interface
and/or with different energy positions in the bang gap can result into instabilities
of the threshold voltage V th , when the device is subjected to positive or negative
bias stresses. In particular, positive and/or negative stress may vary the amount
of the occupied slow traps [79–81] located at the insulator/GaN interface and/or
in the bulk of the gate insulator [78, 82].
Figure 4.14a shows, as an example, the transfer characteristics of a
recessed-gate hybrid GaN MISHEMT, employing AlN/Al2 O3 as gate insu-
lator, before and after a positive gate bias stress at V G = 12 V for 10 μs [83].
10–2
Before stress T = 150 °C
After stress
EC
10–3
Drain current (A)
EF
VG-stress EV
10–4 EF
metal Al2O3/AlN GaN
10–5
VDS = 0.5 V
VG-stress = 12 V
10–6
0 1 2 3 4
(a) Gate voltage (V) (b)
Figure 4.14 (a) Transfer characteristics IDS –V GS of recessed-gate hybrid Al2 O3 /AlN/GaN
MISHEMTs before and after a positive gate bias stress at 12 V for 10 μs. (b) Schematic
conduction band diagram illustrating the trapping effect occurring under positive bias stress
in the device. Source: Adapted with permission of Acurio et al. [83]. Copyright © 2017,
Elsevier Ltd.
As can be seen, the transfer characteristics of the device measured after the
overvoltage stress of +12 V are notably shifted in the positive direction with
respect to the original ones, with a threshold voltage shift ΔV th = 2.13 V.
This positive shift indicates an accumulation of negative charges (electrons)
inside pre-existing traps in the gate insulator (see schematic representation in
Figure 4.14b). A similar effect was observed when using SiO2 as a gate insulator
[84]. In this case, the stress-induced ΔV th can be fully recovered by applying a
negative voltage, which causes the electron detrapping [84].
These existing trapping states are associated with defects in the insulator, which
can be located in different positions with respect to the GaN interface and/or
can have different energy positions in the band gap. Their characteristic trap-
ping/detrapping time constant 𝜏 depends on the physical distance of the trap
from the allowed states in the semiconductor substrate. A trap located at a dis-
tance x from the insulator–semiconductor interface can be emitted with an inver-
sion electron tunneling process with time constant 𝜏 ≈ 𝜏 0 exp(x/𝜆), where 𝜏 0 is the
characteristic time for the insulator and 𝜆 is the attenuation length that depends
on the insulator/GaN barrier height [85]. Deeper traps (e.g. >1 nm from the semi-
conductor interface) can be charged during prolonged gate stress and may affect
significantly the V th stability during the transistor switching operation.
Interestingly, more pronounced and faster charge trapping processes have been
observed in recessed-gate hybrid MISHEMTs with bilayer gate insulators [72, 83]
with respect to single-layer insulators [78, 84].
Finally, a further progress of the recessed-gate MISHEMT technology was the
implementation of fluorine treatments below the gate region. In fact, as discussed
in Section 4.3.2, F-implantation introduces negative charges that give the possi-
bility to induce a positive shift of the threshold voltage.
In particular, a partial recession of the AlGaN barrier layer by means of a
CF4 -plasma etch in a Al2 O3 -insulated MISHEMT enabled Zhang et al. [56] to
compensate an intrinsic positive charge of the Al2 O3 gate insulator and obtain
V th up to +4 V without affecting the maximum drive current [56].
In conclusion, the recessed-gate hybrid MISHEMT is a very promising
approach to obtain the normally-off operation in GaN transistors. This
approach is attracting great interest, also because of the similarity with the
well-consolidated MOSFET technology. However, in spite of the large number
of research studies reported in the literature, recessed-gate hybrid MISHEMTs
based on GaN have not reached yet an adequate level of maturity to be
introduced into the market.
4.3.4 p-GaN Gate HEMT

In spite of some preliminary work appeared in 2000 [86], the concept of
normally-off AlGaN/GaN HEMT controlled by a p-type GaN gate was clearly
demonstrated by Uemoto et al. [87] only in 2007. Today, the p-GaN gate HEMT
represents the only “true” normally-off solution available on the market. After
the introduction in the market of the low-voltage (100–200 V) products by EPC
(https://epc-co.com/epc), the p-GaN gate technology has attracted the interest
of other important companies (e.g. Panasonic and Infineon), which in some
years were able to fully qualify and commercialize their products up to 650 V,
introducing some important technological breakthroughs [88, 89].
To understand the operation principle of a normally-off p-GaN HEMT, it
is useful to consider the band structure. Figure 4.15a,b reports the schematic
cross section of a p-GaN gate HEMT (a) and the conduction band diagram of a
p-GaN/AlGaN/GaN heterostructure (b).
As can be seen, the introduction of a p-GaN layer on top of the AlGaN/GaN
heterostructure raises the conduction band of the AlGaN above the Fermi level
of an amount of energy comparable with the GaN band gap (3.4 eV), with the
consequent depletion of the 2DEG. Hence, using a p-GaN/AlGaN/GaN system
can enable to achieve a normally-off condition.
Gate
Source p-GaN Drain
ΔEC
AlGaN EC
p-GaN
2DEG
EF
GaN Metal
gate AlGaN GaN
(a) (b)
Figure 4.15 (a) Schematic cross section of a p-GaN gate HEMT and (b) conduction band
diagram of a p-GaN/AlGaN/GaN heterostructure.
In such a structure, the p-GaN gate is defined by a selective plasma etch process
that removes the p-GaN layer from the access regions, until reaching the under-
lying AlGaN barrier.
Although the operation principle of the p-GaN HEMT may appear simple,
introducing a p-GaN layer on top of an AlGaN/GaN heterostructure is not suf-
ficient to ensure the normally-off behavior. Rather, the fabrication of functional
devices depends on several parameters such as the heterostructure properties,
p-GaN etching and doping, gate contact, and thermal annealing [90].
First, an appropriate choice of the heterostructure is essential to efficiently
deplete the 2DEG at the interface. Hence, the acceptor concentration of p-GaN
(N A ), the thickness (dAlGaN ) and Al-concentration (x) of the AlGaN barrier layer,
and the residual donor concentration in both AlGaN and GaN layers must be
appropriately selected to obtain a positive threshold voltage of the device.
Regarding the p-GaN layer, it is well known that the achievement of the p-type
conductivity represented a long-standing problem in GaN technology [91]. Mag-
nesium (Mg) is the reference p-type dopant for GaN, when it replaces Ga in
the nitride lattice and acts as an acceptor. However, because the high ioniza-
tion energy of the acceptors (150–200 meV), it is quite difficult to obtain high
hole concentrations in the p-GaN layer [92, 93]. The common understanding is
that a high doping level of p-GaN (>1018 cm−3 ) is required to obtain an efficient
depletion of the 2DEG.
The effect of the p-GaN doping level on the band structure of a p-GaN/GaN/
AlGaN heterostructure has been recently studied by Efthymiou et al. [94].
In particular, TCAD simulations showed that the threshold voltage V th first
increases for doping levels of p-GaN in the range 1017 –1018 cm−3 and then
slightly decreases for N A > 6 × 1018 cm−3 [94]. In fact, while the positive voltage
needed to modulate the AlGaN/GaN conduction band initially increases with
the p-GaN doping, at sufficiently high doping levels, the depletion region at
the metal/p-GaN interface becomes very narrow, thus enhancing the tunneling
of holes through the barrier. Hence, a further increase of the gate bias does
not result in an additional widening of the depletion region but leads only to
a shift of the AlGaN/GaN conduction band toward the Fermi level. Typically,
p-GaN layers with thickness in the range of 50–100 nm and doping level
N A ∼ 1018 –1019 cm−3 are used in p-GaN gate HEMTs.
The choice of the AlGaN barrier layer thickness (dAlGaN ) and Al-concentration
(x) has a great influence on the electrical behavior of the p-GaN/AlGaN/GaN
heterostructures [90]. To highlight this aspect, Figure 4.16 reports the conduc-
tion band diagrams for some p-GaN/AlGaN/GaN heterostructures, simulated
using a one-dimensional Poisson–Schrödinger solver. For all the simulated cases,
a p-GaN thickness of 50 nm with N A = 6 × 1018 cm−3 was used, with a n-type dop-
ing level of the AlGaN and GaN layers of 1 × 1016 and 1 × 1015 cm−3 , respectively.
Figure 4.16a shows the case of p-GaN/AlGaN/GaN heterostructures with
an Al-concentration x = 20% in the AlGaN layer for two thicknesses of 10
and 20 nm. As can be seen, only in the case of the thinner AlGaN barrier
layer (dAlGaN = 10 nm), the conduction band is raised above the Fermi level
(normally-off condition), whereas for the thicker layer (20 nm), the 2DEG is
still present at the interface. On the other hand, Figure 4.16b shows the case
5 5
EC dAlGaN = 10 nm EC XAlGaN = 0.1
EC dAlGaN = 20 nm EC XAlGaN = 0.2
4 EF
4 EF
3 3
Energy (eV)
Energy (eV)
2 2 u-GaN
u-GaN
1 1
p-GaN p-GaN
0 0
Thinner AlGaN
–1 Thicker AlGaN –1
AlGaN
–2 –2
0 40 80 120 0 40 80 120
(a) Depth (nm) (b) Depth (nm)
Figure 4.16 Simulated conduction band diagrams for p-GaN/AlGaN/GaN heterostructures for
(a) two different values of the AlGaN thickness (10 and 20 nm) or (b) two different values of the
Al-concentration (10% and 20%).
of a heterostructure with an AlGaN barrier layer thickness of 20 nm for two

different values of the Al-concentration x (10% and 20%). In this case, only for
the lower Al-concentration (x = 10%), the conduction band is raised above the
Fermi level (normally-off condition), whereas the 2DEG is still present for an
Al-concentration x = 20%.
An interesting physical effect observed by Uemoto et al. [87] is the injection of
holes from the p-AlGaN gate toward the AlGaN/GaN interface, for sufficiently
high gate bias values, which led to the definition of the device as gate injection
transistor (GIT).
Figure 4.17a schematically explains the operation principle of a normally-off
p-AlGaN/n-AlGaN/GaN GIT. In this device, because of the presence of the
p-AlGaN layer, the 2DEG channel is interrupted below the gate contact. Hence,
a positive gate bias above the threshold voltage V th is necessary to restore the
2DEG at the AlGaN/GaN interface, enabling the conduction in the channel. By
further increasing the gate bias above the built-in voltage of the p-GaN/AlGaN
junction (V F ), holes are injected from p-AlGaN layer toward the interface,
where the 2DEG has been restored. There, to maintain the charge neutrality in
the material, the injected holes are balanced by an equal number of electrons
that reach the 2DEG at the interface. At this point, while electrons move toward
the drain electrode driven by the applied bias, holes remain in the gate region
because of their lower mobility (about 2 orders of magnitude lower with respect
to that of electrons). Such conductivity modulation results in a further increase
of the drain current I D when hole injection starts, while the gate current remains
low. As can be seen, the occurrence of hole injection manifests itself in the
transconductance curve g m by the appearance of a second peak (Figure 4.17b)
[87], which is typically not observed in standard HEMTs.
A drawback encountered in the switching operation of GaN-based GITs is the
increase of the dynamic on-resistance (“current collapse”) at high drain voltages
(>600 V) [95, 96]. In order to overcome this problem, the hybrid drain-embedded
Gate VG = 0 V
250 200
Source Drain
p-AIGaN
i-AIGaN
Drain current (mA/mm)

200
I
i-GaN
gm (mS/mm)
150
I II III
Gate Vth < VG<VF 100
Source Drain
p-AIGaN 100
i-AIGaN
II
i-GaN 50
Gate V G > VF 0 0
Source
p-AIGaN
Drain –2 0 2 4 6
i-AIGaN (b) Gate voltage (V)
III
i-GaN
(a)
Figure 4.17 (a) Schematic explanation of the operation principle of a normally-off

p-AlGaN/n-AlGaN/GaN in gate injection transistor (GIT). (b) Corresponding drain current and
transconductance (gm ) of the devices. Source: Adapted with permission of Greco et al. [90].
Copyright © 2018, Elsevier Ltd.
gate injection transistor (HD-GIT) [97, 98] has been developed. In the HD-GIT,
an additional p-GaN region between the gate and the drain is introduced to
induce a hole injection in the off-state. Noteworthy, in this device, a thicker
AlGaN barrier layer is used in order to maintain the 2DEG below the p-GaN
drain region, while the normally-off operation is ensured by the recession of
the AlGaN barrier layer below the p-GaN gate. This technology allows a hole
injection from the p-GaN drain that can effectively release the trapped electrons
during the switching process [97, 98]. In this way, the dynamic on-resistance
remains low during fast switch also at a high drain voltage (>600 V). More details
on the reliability aspects of the HD-GIT are discussed in Chapter 6.
One of the most important building blocks of the p-GaN gate HEMT is surely
the metal gate. In fact, the electrical properties of the metal/p-GaN barrier can
have a strong impact on the value of the threshold voltage V th and on the device
leakage current [99–101].
In general, the first question is whether a Ohmic or a Schottky contact must
be used as gate electrode on the p-GaN layer. In the original work of Uemoto
et al. [87], a Pd-based Ohmic contact was used as a gate electrode to improve
hole injection and conductivity modulation. However, a clear description of
the metal/p-GaN electrode formation has not been disclosed in that work. As
a matter of fact, obtaining good Ohmic contacts on p-GaN layers is a complex
task, requiring specific annealing processes in oxidizing atmosphere [102],
which in turn can be detrimental for the underlying 2DEG [103, 104]. Hence,
the formation of good Ohmic contacts on p-GaN gate HEMTs is difficult
to implement in the HEMT fabrication flow. For that reason, normally-off
HEMTs with a p-GaN gate typically employ a Schottky metal as a gate electrode.
In this context, TCAD simulations predicted that low work function metals on
p-GaN/AlGaN/GaN systems, which give higher Schottky barrier height ΦB ,
should enable to obtain a higher threshold voltage V th and a lower gate leakage
current [94, 99]. In real cases, the situation is more complex. As an example, the
large threshold voltage difference (ΔV th = 1.8 V) observed between devices using
W-gate (Φm(W) = 4.6 eV, V th = 3.1 V) and Ni-gate (Φm(Ni) = 5.2 eV; V th = 1.3 V)
could not be explained simply by the energy difference between the two work
function values ΔΦm = 0.6 eV [99]. In fact, the thickness of the depletion region
generated at the metal/p-GaN interface increases with decreasing metal work
function (i.e. increasing the barrier height). Then, for a metal gate with a high
barrier height, the positive gate bias will partially drop on the wider depletion
region, thus leading to an increase of V th . On the other hand, for a metal gate
with a lower barrier height, the voltage drop on the thinner depletion region will
be negligible, similarly to what happens in an Ohmic contact, thus leading to a
lower V th . A direct comparison between Schottky (WSiN-based) and Ohmic
(Ni/Au) metal gate has been done by Meneghini et al. [105]. In particular, using
the WSiN-based Schottky gate resulted in an increase of the transistor gate
voltage swing, giving the possibility to reduce the gate leakage current by about
4 orders of magnitude in the on-state. Hence, the use of Schottky gate contact
is typically preferred on p-GaN normally-off HEMTs respect to Ohmic contact
solution.
Table 4.2 reports a collection of literature data on normally-off p-GaN gate
HEMTs. As can be seen, several metals have been investigated as gate contacts for
p-GaN HEMTs [87, 99–101, 105–114]. However, a clear dependence of V th on the
metal work function cannot be deduced because many parameters (semiconduc-
tor surface defects, metal deposition technique, surface preparation, annealing
conditions, etc.) influence the value of the metal/p-GaN barrier height.
Lee et al. [100] showed that metals with lower work function lead to a higher
V th but reduce the output current. TiN is often used as gate contact for p-GaN
because it is widely diffused in silicon technology and has a good thermal sta-
bility in contact with GaN. In particular, TiN can be adopted in a “self-aligned”
approach. In this case, TiN is first patterned and used as a hard mask to remove
the p-GaN layer from the access regions and is then left as gate electrode for the
device. A self-aligned process has also been demonstrated by Lükens et al. [106],
using Mo metal gate encapsulated on SiOx cap layer and AlOx sidewall space as
protection during annealing or dry etching process.
As mentioned before, the definition of the p-GaN gate is obtained by means of
selective plasma etching, i.e. the p-GaN must be removed in the access regions
and remain only under the gate. In a “self-aligned” process, the metal gate is
deposited at the beginning of the fabrication flow (“gate first”), is used as a
hard mask for the p-GaN definition, and is then left as a metal electrode on the
p-GaN. This approach clearly simplifies the device fabrication flow. However,
in this case, the source and drain Ohmic contacts must be fabricated later, thus
typically requiring high annealing temperatures (>800 ∘ C) [115]. Such thermal
budget can lead to thermal reactions between the metal gate and the p-GaN,
which worsen the electrical quality of the barrier. Greco et al. [101] compared a
“gate first” approach, where the Ti/Al metal gate contact is used as a hard mask
Table 4.2 Collection of literature data obtained on normally-off p-GaN HEMTs.
p-GaN p-GaN Threshold Maximum

Metal thickness doping voltage gate bias
gate (nm) (cm−3 ) V th (V) (V) References
Pd 100 (Al15 GaN) N A = 1 × 1018 1 6 [87]

Ni 100 N A = 2 × 1019 1.23 7 [99]
W 100 N A = 1 × 1019 3.0 10 [99]
Mo/Ti/Au 60 N A ∼ 2 × 1018 1.9 10 [100]
18
Ni/Au 60 N A ∼ 2 × 10 1.8 10 [100]
Ti/Au 60 N A ∼ 2 × 1018 1.7 6 [100]
Ti/Al 50 N A = 3 × 1019 1.5 10 [101]
WSiN N.A. N A not given 1.87 11 [105]
Mo/Ni 80 N A = 3 × 1019 1.08 10 [106]
Ni/Au 50 N A = 3 × 1018 0.48 8 [107]
Pd/Au 70 N A not given 1.0 5 [108]
Ti/Au 70 N A not given 1.2 6 [109]
TiN 70 N A = 1 × 1018 1.6 10 [110]
TiN 70 N A not given 2.1 9.5 [111]
Ni/Au 95 N A = 3 × 1019 1.5 9 [112]
Ni/Au 70 p = 3 × 1019 1.75 10 [113]
Ni/Au 70 p = 1 × 1018 1.75 8 [114]
for the dry etch of p-GaN and then subjected to annealing for Ohmic contacts
(800 ∘ C), with a “gate last” approach, where the Ti/Al gate contact is defined at
the end of the flowchart [101]. As can be seen from the transfer characteristics
of the devices, shown in Figure 4.18, a V th = +1.5 V has been obtained using
a nonannealed Ti/Al metal gate (“gate last” approach). On the other hand, the
annealing of the metal gate at 800 ∘ C (“gate first” approach) resulted in a negative
V th shift and an increase of the leakage current because of the structural change
of the Al/Ti/p-GaN systems occurring upon annealing. In particular, in the
Al/Ti/p-GaN system, a reduction of the barrier height from 2.08 to 1.60 eV has
been observed after 800 ∘ C annealing [116].
An important figure of merit of p-GaN gate HEMTs is the maximum bias that
can be applied to the gate before breakdown. In fact, under positive gate bias, the
metal/p-GaN junction is reversed biased, thus leading to a further extension of
the depletion region. In these conditions, the electrons coming from the 2DEG
channel through the AlGaN can be injected in the p-GaN layer, where they will
be further accelerated by the high electric filed of the reverse-biased depletion
region. When the electrons moving across the depletion region acquire sufficient
energy from the electric field, the avalanche breakdown occurs. Wu et al. [110]
confirmed this effect, observing that the gate breakdown voltage increases with
Figure 4.18 Transfer characteristics (IDS vs. 104

V GS ) at V DS = +10 V of normally-off p-GaN “Gate last” (not annealed)
gate HEMTs fabricated with “gate last “Gate first” (annealed)
102
approach” (nonannealed) and “gate first
Drain current (mA/mm)

approach” (annealed at 800 ∘ C). Source:
Adapted with permission of Roccaforte et al. 100
[22]. Copyright © 2019 by the authors;
10–2 Vth shift
licensee MDPI, Basel, Switzerland. Ref. [22] is
an open access article distributed under the
terms and conditions of the Creative 10–4
Commons Attribution License. Leakage
10–6 increase
VDS = 10 V
–2 –1 0 1 2 3 4
Gate voltage (V)
12 Uemoto et al. 2007

Hwang et al. 2013
Lee et al. 2016
Greco et al. 2016
10
Maximum gate bias (V)
Meneghini et al. 2017

Lukens et al. 2018
Chiu et al. 2018
Chang et al. 2015
8 Xu et al. 2018
Wu et al. 2015
Tallarico et al. 2017
Tapajna et al. 2016
6 Hao et al. 2016
Jiang et al. 2019
2
0 1 2 3 4
Figure 4.19 Maximum gate bias vs. threshold voltage for different p-GaN gate HEMTs. Source:
The data are taken from Table 4.2.
the temperature. In fact, a positive temperature coefficient of the gate breakdown

is typically observed in avalanche breakdown. Figure 4.19 shows a survey of
literature results for maximum applied gate bias vs. threshold voltage for p-GaN
gate HEMTs.
In normally-off p-GaN gate HEMTs, the removal of the p-GaN layer is typically
obtained by ICP or RIE processes. However, a smooth surface morphology, a low
damage, and a controlled etch rate are required. For that reason, this process can
represent a critical step on the fabrication of normally-off p-GaN gate HEMTs.
Hence, some alternative approaches have been proposed in the literature to avoid
plasma etch of the p-GaN. Figure 4.20 schematically illustrates the standard solu-
tion (p-GaN etch) (a) and two alternative solutions, i.e. selective growth of p-GaN
(b) and H-plasma treatment (c).
The “ideal” solution to avoid plasma etch would be the selective epitaxial
growth of p-GaN in the gate region (Figure 4.20b). Indeed, SAG is mostly used
Standard p-Gan Standard p-Gan Figure 4.20 Schematic cross section

dry etching Gate dry etching of normally-off p-GaN HEMTs
fabricated with (a) standard p-GaN
Source Drain dry etching process, (b) selective area
p-Gan
growth (SAG) of p-GaN, and (c)
AlGaN hydrogen plasma surface treatment
for local Mg deactivation. Source:
GaN Reproduced with permission of Greco
et al. [90]. Copyright © 2018, Elsevier.
(a)
Selective p-Gan
growth
Gate
Source Drain
Hard mask p-Gan Hard mask
AlGaN
GaN
(b)
Hydrogen plasma Hydrogen plasma
treatment treatment
Gate
Source Drain
p-Gan
AlGaN
GaN
(c)
for other technologies, such as the fabrication of nonalloyed Ohmic contacts

[117, 118], the recessed-gate MISHEMT structures [68, 119], or for optoelec-
tronics nanostructures (light emission diodes and laser diodes) [120, 121].
However, this approach presents several limitations, such as the nature and
the geometry of the hard mask [122, 123], the growth temperature [124, 125],
and the reactor pressure [126]. Nevertheless, Yuliang et al. [127] obtained a
positive V th shift from −3.95 to −0.35 V, using the selective MOCVD growth of a
p-GaN layer defined with a SiO2 hard mask. Despite the smooth morphology,
a nonuniform growth along the hard mask sidewall was observed [128]. Clearly,
a further optimization of this process is necessary to obtain lager V th shift
and stable normally-off operation, as well as to achieve thickness and dopant
uniformity in the grown layer.
Another very interesting approach consists in the possibility to replace p-GaN
etch process with a hydrogen treatment of the p-GaN surface (Figure 4.20c). In
fact, hydrogen atoms have the capability to compensate p-type doping in GaN by
the formation of Mg–H neutral complexes, which passivate the Mg-acceptors
in the p-type GaN layer [113]. In this condition, the conduction band of the
p-GaN layer can be selectively pulled below the Fermi level, restoring the 2DEG
at AlGaN/GaN interface in the access regions. The devices fabricated with this
approach exhibited a threshold voltage V th = +1.75 V and a current density of
188 mA/mm at the maximum gate voltage swing of +6 V.
4.4 Other Approaches 163
4.4 Other Approaches

The technological approaches described in Sections 4.2 and 4.3 are the most
common and feasible ones to achieve normally-off operation in GaN-based
HEMTs. However, other routes to obtain normally-off HEMT operation have
been attempted in the literature. Although the obtained results were often far
from a practical application, interesting physical insights can be gained from
those studies.
One of these methods consists in the oxidation of the AlGaN barrier layer in
AlGaN/GaN heterostructures, which has been investigated for several scopes,
such as surface passivation [129, 130] or device isolation [131]. As an example,
Roccaforte et al. [103, 104] demonstrated that a local AlGaN surface thermal
oxidation at 900 ∘ C for some hours can be used for 2DEG isolation, even if the
formed oxidized layer is not thick enough to reach the AlGaN/GaN interface
depth. Clearly, a more accurate control of the localized surface oxidation was
required to tailor the properties of the 2DEG, e.g. by using a rapid oxidation pro-
cesses. Figure 4.21 shows a TEM image of a AlGaN layer subjected to a rapid ther-
mal annealing in O2 at 900 ∘ C for 10 minutes [132]. As can be seen, this process
leads to the formation of a uniform 1.5 nm thick crystalline oxide layer. Litera-
ture data obtained on AlGaN alloys with a similar Al-concentration suggest that
the oxidized layer is composed of Al2 O3 and Ga2 O3 [133–135]. The application of
such a controlled thermal oxidation process to GaN HEMTs resulted in a positive
shift of the threshold voltage V th , although a significant reduction of the device
current prevented its practical used in real devices [132].
Alternatively, Chang et al. [136] demonstrated the possibility to use local
plasma oxidation in the gate region to fabricate normally-off AlN/GaN HEMTs.
In this case, an oxygen plasma treatment with a small RF power range (20–40 W)
was used to convert the surface of the AlN layer into aluminum oxide, reducing
the thickness of the underlying AlN below the critical thickness, similarly to
Figure 4.21 High-resolution TEM

images of an AlGaN layer subjected
to a rapid thermal oxidation at
900 ∘ C for 10 minutes. The
formation of a thin (1.5 nm) oxidized
surface layer is visible. Source:
Reproduced with permission of
Greco et al. [132]. Copyright © 2014, an
ed AlG
IOP Publishing. Oxidiz
AlGan
2 nm
Lithography
O2 plasma
Photoresist
AlN AlN AlN
2DEG 2DEG 2DEG
GaN GaN GaN
(a) (b) (c)
Source Drain Source Gate Drain

Al2O3 AlN Al2O3 AlN Al2O3 AlN
2DEG 2DEG 2DEG
GaN GaN GaN
(d) (e) (f)
Figure 4.22 (a–f ) Fabrication process to obtain normally-off AlN/GaN HEMTs by a local oxygen
plasma treatment.
what happens in a recessed HEMT. This process is schematically illustrated in

Figure 4.22. Clearly, long oxidation treatments lead to a thicker oxide layer in the
gate area and to a further depletion of the 2DEG (more positive V th ). However,
the increase of the channel resistance, caused by the decrease of the 2DEG
density, results in a lower saturation drain current of the devices.
Mizutani et al. [137] used a p-In0.23 Ga0.77 N cap layer, instead of p-GaN, to raise
the conduction band at the AlGaN/GaN interface and to deplete the 2DEG in the
gate region. In this approach, the polarization-induced field in the InGaN cap and
the negative charge in the p-InGaN allowed to achieve a V th = +1.2 V. Moreover, a
reduction of the leakage current is expected in such devices because of the higher
barrier height observed in heterostructures using the InGaN cap layer.
Finally, another interesting possibility to obtain normally-off HEMT is using a
nickel oxide (NiOx ) layer onto AlGaN/GaN heterostructures. Crystalline nickel
oxide has been successfully used as an insulator to reduce the leakage current
in Schottky contacts on HEMTs structures [138, 139]. However, under certain
growth and post-annealing conditions, NiOx layers can exhibit a p-type semicon-
ductor behavior. Hence, this material could be a candidate to replace the p-GaN
in normally-off HEMTs. In particular, Kaneko et al. [140] demonstrated a GaN
HEMT with a V th = +0.8 V by the combination of NiO/Ni/Au gate with a recessed
AlGaN gate region. However, the postannealing condition to obtain p-type con-
ductivity in NiO films is difficult to control and can produce detrimental effects
for the 2DEG channel.
4.5 Summary
In this chapter, the main technological approaches to obtain normally-off GaN
HEMTs were presented. The development of a reliable normally-off HEMT
References 165
technology is a key step toward a massive introduction of GaN transistors in

power semiconductor market.
Normally-on HEMTs can be used in “cascode” with Si-MOSFET to obtain
normally-off chips. However, this configuration presents some drawback related
to the application voltage and the parasitic effects caused by the package
complexity.
The technologies to achieve “true” normally-off HEMTs are based on surface
modification of the AlGaN layer. The recessed-gate approach and the introduc-
tion of fluorine ions in the AlGaN barrier were the first concepts that triggered
the entire research on normally-off HEMTs. These studies clearly showed that
the increase of the threshold voltage and reduction of leakage current required
an additional improvement of the device layout.
Nowadays, the technology is oriented toward two main device concepts, i.e. the
p-GaN gate and the recessed-gate hybrid MISHEMT. The first one is currently the
only “true” normally-off GaN HEMT available on the market, whereas the second
one is intensively studied at R&D level. These approaches exhibit sill several open
issues that must be addressed to optimize the reliability and manufacturability.
Hence, the long-term choice of the normally-off technology will probably depend
on the targeted application, i.e. the p-GaN gate being more suitable for the low-
and medium-voltage applications and the recessed-gate hybrid MISHEMT for
higher voltage applications.
Acknowledgments
The authors would like to thank all the colleagues that contributed to the
research activity on normally-off GaN HEMT in these years: F. Giannazzo, R. Lo
Nigro, S. Di Franco, E. Schilirò, M. Spera (CNR-IMM, Italy), A. Patti, S. Reina
and A. Parisi (STMicroelectronics, Italy), M. Leszczyński, P. Prystawko and P.
Kruszewski (Unipress-PAS, Poland).
This work was partially supported by the Italian Ministry for Education,
University and Research (MIUR) in the framework of the National Project PON
EleGaNTe (Electronics on GaN-based Technologies), ARS01_01007.
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137

Technologies for Normally-oﬀ GaN HEMTs

Nitride Semiconductor Technology: Power Electronics and Optoelectronic Devices,

The ﬁrst approaches toward the achievement of “true” normally-oﬀ HEMTs

4.1.1 Threshold Voltage in AlGaN/GaN HEMTs

Figure 4.1 Schematic conduction band diagram of an AlGaN/GaN heterostructure in the

conduction band diagram of an AlGaN/GaN heterostructure in the Schottky

4.2 GaN HEMT “Cascode”

Figure 4.3 Percentage of on-resistance from Si

4.3 “True” Normally-oﬀ HEMT Technologies

Table 4.1 Collection of literature data obtained in recessed-gate AlGaN/GaN HEMTs.

Residual AlGaN Threshold

1 Figure 4.5 Experimental values of the threshold

Normally-on AlGaN/GaN HEMTs. Source: The data are taken

4.3.2 Fluorinated HEMT

2 Figure 4.7 Calculation of the threshold

Normally-off have been assumed for this calculation: an

To consider the eﬀect of ﬂuorine incorporation on the threshold voltage

Figure 4.8 Threshold voltage V th as a 2

Threshold voltage (V)

0 50 100 150 200

GaN GaN F-treated

4.3.3 Recessed-gate Hybrid MISHEMT

Source Drain Dielectric

250 Figure 4.12 Field eﬀect mobility 𝜇FE as

Source: The data are taken from Refs.

Figure 4.13 Peak values of the ﬁeld 2000

µFE (peak) (cm2/ (V s))

In particular, the diﬀerent temperature-dependent contributions to the mobility

4.3.4 p-GaN Gate HEMT

of a heterostructure with an AlGaN barrier layer thickness of 20 nm for two

Drain current (mA/mm)

Figure 4.17 (a) Schematic explanation of the operation principle of a normally-oﬀ

Table 4.2 Collection of literature data obtained on normally-oﬀ p-GaN HEMTs.

p-GaN p-GaN Threshold Maximum

Pd 100 (Al15 GaN) N A = 1 × 1018 1 6 [87]

Figure 4.18 Transfer characteristics (IDS vs. 104

Drain current (mA/mm)

12 Uemoto et al. 2007

Meneghini et al. 2017

the temperature. In fact, a positive temperature coeﬃcient of the gate breakdown

Standard p-Gan Standard p-Gan Figure 4.20 Schematic cross section

for other technologies, such as the fabrication of nonalloyed Ohmic contacts

4.4 Other Approaches

Figure 4.21 High-resolution TEM

GaN GaN GaN

(a) (b) (c)

Source Drain Source Gate Drain

GaN GaN GaN

(d) (e) (f)

what happens in a recessed HEMT. This process is schematically illustrated in

technology is a key step toward a massive introduction of GaN transistors in

Sel Top. Power Electron. 4: 707–719. https://doi.org/10.1109/JESTPE.2016

94 Efthymiou, L., Longobardi, G., Camuso, G. et al. (2017). On the physical

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