DLP3000

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DLP® 0.3 WVGA Series 220 DMD

Check for Samples: DLP3000

FEATURES
1

•
2 0.3-Inch (7.62 mm) Diagonal Micromirror Array • Package Mates to PANASONIC AXT550224
– 608 × 684 Array of Aluminum, Micrometer- Socket
Sized Mirrors
– 7.6-µm Micromirror Pitch APPLICATIONS
– ±12°Micromirror Tilt Angle (Relative to Flat • Machine Vision
State) • Industrial Inspection
– Side Illumination for Optimized Efficiency • 3D Scanning
– 3-µs Micromirror Cross Over Time • 3D Optical Metrology
• Highly Efficient in Visible Light (420 nm–700 • Automated Fingerprint Identification
nm): • Face Recognition
– Window Transmission 97% (Single Pass, • Augmented Reality
Through Two Window Surfaces) • Embedded Display
– Micromirror Reflectivity 88% • Interactive Display
– Array Diffraction Efficiency 86% • Information Overlay
– Array Fill Factor 92% • Spectroscopy
– Polarization Independent • Chemical Analyzers
• Up to WVGA Resolution (854x480) Wide • Medical Instruments
Aspect Ratio Display
• Photo-Stimulation
• Low Power Consumption, only 200 mW
• Virtual Gauges
(Typical)
• 15-Bit, Double Data Rate (DDR) Input Data Bus
• 60-MHz to 80-MHz Input Data Clock Rate
• Integrated Micromirror Driver Circuitry
• Supports –10 °C to 70 °C
• 16.6-mm by 7-mm by 5-mm Package Footprint
• Dedicated DLPC300 Controller for Reliable
Operation

DESCRIPTION
The DLP3000 digital micromirror device (DMD) is a digitally controlled MOEMS (micro-opto-electromechanical
system) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP3000 can be used
to modulate the amplitude and direction of incoming light. The DLP3000 creates light patterns with speed,
precision, and efficiency.
Architecturally, the DLP3000 is a latchable, electrical-in/optical-out semiconductor device. This architecture
makes the DLP3000 well suited for use in applications such as 3D scanning or metrology with structured light,
augmented reality, microscopy, medical instruments, and spectroscopy. The compact physical size of the
DLP3000 is well-suited for portable equipment where small form factor and lower cost are important. The
compact package compliments the small size of LEDs to enable highly efficient, robust light engines.
The DLP3000 is one of two devices in the DLP 0.3 WVGA chipset (see Figure 1). Proper function and reliable
operation of the DLP3000 requires that it be used in conjunction with the DLPC300 controller. See the DLP 0.3
WVGA Chip-set data sheet (TI literature number DLPZ005) for further details. Figure 2 shows a typical system
application using the DLP 0.3-inch WVGA chipset.
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 DLP is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DLPC300
DLP3000

DATA & CONTROL RECEIVER

PARALLEL
DATA(14:0)

RGB
Data
Interface LOADB
TRC CMOS
MICROMIRROR
MEMORY
SCTRL ARRAY
ARRAY
SCL SAC_BUS
SDA
CONTROL

SAC_CLK
PARK
RESET
GPIO4_INTF
PLL_REFCLK

MICROMIRROR ARRAY
DRC_BUS

RESET CONTROL
INTERFACE

DRC_OE
SDRAM

Memory DRC_STROBE
Interface
VOFFSET
VBIAS
VDD10 VRESET
VCC18
VCC_INTF
GND
VCC
VDD_PLL
LED DRIVER

VSS
RTN_PLL
Illumination
SPICLK Interface
INTERFACE

VCC Serial SPICSZ0

FLASH

VSS FLASH SPIDOUT

SPIDIN
VCC_FLSH CAMERA Camera
TRIGGER Trigger

Figure 1. DLP 0.3 WVGA Chip Set

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Mobile DDR RAM

Address
Control

Data
PCLK Red PWN,
Green PWM,
DVI Blue PWM LED
Digital Video Receiver
HSYNC,VSYNC LEDs
24-Bit RGB Data LED Strobes Drivers
(TVP5151)

Illumination
I22 C Optics
LED
Sensor
Control DLPC300
Control I22 C
Processor
DMD Control
(MSP430)
DLP3000
DMD Data
OSC

VBIAS

VOFF
CTL

VRST
SPIDOUT
SPIDIN,
SPICLK

DMD™
SPICS

Voltage
Supplies

SPI
FLASH

Figure 2. Typical Application

Electrically, the DLP3000 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of
608 memory cell columns by 684 memory cell rows. The CMOS memory array is addressed on column-by-
column basis, over a 15-bit double data rate (DDR) bus. Addressing is handled via a serial control bus. The
specific CMOS memory access protocol is handled by the DLPC300 digital controller.
Optically, the DLP3000 consists of 415,872 highly reflective, digitally switchable, micrometer-sized mirrors
(micromirrors) organized in a two-dimensional array. The micromirror array consists of 608 micromirror columns
by 684 micromirror rows in diamond pixel configuration (Figure 3). Due to the diamond pixel configuration, the
columns of each odd row are offset by half a pixel from the columns of the even row.
Each aluminum micromirror is approximately 7.6 microns in size (see Micromirror Pitch in Figure 3), and is
switchable between two discrete angular positions: –12° and +12°. The angular positions are measured relative
to a 0° flat reference when the mirrors are parked in their inactive state, parallel to the array plane (see Figure 4).
The tilt direction is perpendicular to the hinge-axis. The on-state landed position is directed toward the left side of
the package (see DLP3000 Active Mirror Array, Micromirror Pitch, and Micromirror Hinge-Axis Orientation in
Figure 3).
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–12° or +12°) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the
CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a mirror clocking
pulse results in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell
followed by a mirror clocking pulse results in the corresponding micromirror switching to a –12°position.

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Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the
CMOS memory. Second, application of a mirror reset to all or a portion of the micromirror array (depending upon
the configuration of the system). Mirror reset pulses are generated internally by the DLP3000 DMD, with
application of the pulses being coordinated by the DLPC300 controller. See SWITCHING CHARACTERISTICS
timing specifications.
Around the perimeter of the 608 × 684 array of micromirrors is a uniform band of border micromirrors. The border
micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been
applied to the device. There are 10 border micromirrors on each side of the 608 by 684 active array.

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837
82
544
 !62925
329

BC8DEEE7F39271244547F44
1234565

1234567

12348

12346
F8FDBFBFFFDB668DFDC7FB6

92A46 92A46
92A4B 92A4B
92A48 92A48
92A4C 92A4C

92A45F6 92A45F6
92A45FB 92A45FB
92A45F8 92A45F8
92A45FC 92A45FC
123456D

123456E

1234C

1234B

1234562445478293A 1234562445472F27429925
E"#7$6
%6
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1234567689 124567689
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E"#7$6 ABC6DEBF86B3 ABC6DEBF86B3

&D
%6

Figure 3. Micromirror Array, Pitch, and Hinge-Axis Orientation

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a±b –a ± b

Figure 4. Micromirror Landed Positions and Light Paths

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Related Documents
The following documents contain additional information related to the use of the DLP3000 device:

Table 1. Related Documents

TI LITERATURE
DOCUMENT
NUMBER
DLP 0.3 WVGA Chipset data sheet DLPZ005
DLPC300 Digital Controller data sheet DLPS023
DLPC300 Software Programmer's Guide DLPU004

Device Part Number Nomenclature

Figure 5 provides a legend for reading the complete device name for any DLP device.

DLP3000FQB
Package Type

Device Descriptor
Figure 5. Device Nomenclature

Device Marking
The device marking consists of the fields shown in Figure 6.
Lot Trace Code

GHJJJJKHVVVV

Encoded Device Part Number

Figure 6. Device Marking

Device Terminals
This section describes the input/output characteristics of signals that interface to the DLP3000, organized by
functional groups. Table 2 includes I/O, Type, Internal Termination, Clock Domain, and Data Rate characteristics
which are further described in subsequent sections.

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Figure 7. Package Connector Signal Names (Device Bottom View)

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Table 2. Connector Pins

TERMINAL CONNECTOR INTERNAL CLOCKED DATA
I/O/P TYPE DESCRIPTION
NAME PINS TERMINATION BY RATE
Data Inputs
DATA(0) D2 Input LVCMOS None DCLK DDR
DATA(1) D4 Input LVCMOS None DCLK DDR
DATA(2) D5 Input LVCMOS None DCLK DDR
DATA(3) D6 Input LVCMOS None DCLK DDR
DATA(4) D8 Input LVCMOS None DCLK DDR
DATA(5) D10 Input LVCMOS None DCLK DDR
DATA(6) D12 Input LVCMOS None DCLK DDR
DATA(7) D14 Input LVCMOS None DCLK DDR Input data bus
DATA(8) E16 Input LVCMOS None DCLK DDR
DATA(9) E14 Input LVCMOS None DCLK DDR
DATA(10) E12 Input LVCMOS None DCLK DDR
DATA(11) E10 Input LVCMOS None DCLK DDR
DATA(12) E5 Input LVCMOS None DCLK DDR
DATA(13) E6 Input LVCMOS None DCLK DDR
DATA(14) E8 Input LVCMOS None DCLK DDR
DCLK E18 Input LVCMOS None – – Input data bus clock
Data Control Inputs
LOADB E20 Input LVCMOS None DCLK DDR Parallel data load enable
TRC E4 Input LVCMOS None DCLK DDR Input data toggle rate control
SCTRL E2 Input LVCMOS None DCLK DDR Serial control bus
Stepped address control serial bus
SAC_BUS E24 Input LVCMOS None SAC_CLK –
data
Stepped address control serial bus
SAC_CLK D24 Input LVCMOS None – –
clock
Mirror Reset Control Inputs
DRC_BUS D22 Input LVCMOS None SAC_CLK DMD reset-control serial bus
Active-low output enable signal for
DRC_OE D20 Input LVCMOS None – –
internal DMD Reset driver circuitry
Strobe signal for DMD Reset
DRC_STROBE E22 Input LVCMOS None SAC_CLK
Control inputs
Power
VBIAS D16 Power Analog None – – Mirror reset bias voltage
VOFFSET D21 Power Analog None – – Mirror reset offset voltage
VRESET D18 Power Analog None – – Mirror reset voltage
Power supply for double-data-rate
VREF E21 Power Analog None – –
low-voltage CMOS logic terminals
D1, D13, D25, Power supply for single-data-rate
VCC Power Analog None – –
E1, E13, E25 LVCMOS logic terminals
D3, D7, D9,
D11, D15,
D17, D19, Common return for all power
VSS Power Analog None – –
D23, E3, E7, inputs
E9, E11, E15,
E17, E19, E23

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Table 2. Connector Pins (continued)

TERMINAL CONNECTOR INTERNAL CLOCKED DATA
I/O/P TYPE DESCRIPTION
NAME PINS TERMINATION BY RATE
A3, A5, A7,
A9, A11, A13,
A15, A17, A19,
A21, A23, A25,
A27, A29 A31,
B2, B4, B6,
B8, B10, B12,
B14, B16, B18,
B20, B22, B24,
B26, B28, B30,
C1, C3, C31,
F1, F3, F31, No connection (Any connection to
No connect G2, G4, G6, – – – – – these terminals may result in
G8, G10, G12, undesirable effects)
G14, G16,
G18, G20,
G22, G24,
G26, G28,
G30, H1, H3,
H5, H7, H9,
H11, H13,
H15, H17,
H19, H21,
H23, H25,
H27, H29, H31

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional
performance of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PARAMETER CONDITIONS MIN MAX UNIT
Electrical
VCC Voltage applied to VCC (1) (2) –0.5 4 V
VREF Voltage applied to VREF (1) (2) –0.5 4 V
(1) (2) (3)
VOFFSET Voltage applied to VOFFSET –0.5 8.75 V
VBIAS Voltage applied to VBIAS (1) (2) (3) –0.5 17 V
(1) (2)
VRESET Voltage applied to VRESET –11 0.5 V
(3)
Supply voltage delta |VBIAS – VOFFSET| 8.75 V
Voltage applied to all other input terminals (1) –0.5 VREF + 0.3 V
Current required from a high-level output VOH = 2.4 V –20 mA
Current required from a low-level output VOL = 0.4 V 15 mA
Environmental
Storage temperature range (4) (5) -40 80 °C
Storage humidity (4) (5) Non-condensing 0 95 % RH
< 420 nm 2
Illumination power density (4) (6) 420 nm to 700 nm See (7)
mW/cm2
> 700 nm 10
(8)
Electrostatic discharge immunity All pins 2000 V

(1) All voltages referenced to VSS (ground).

(2) Voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are required for proper DMD operation.
(3) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(4) Optimal, long-term performance of the Digital Micromirror Device (DMD) can be affected by various application parameters, including
illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case
temperature, ambient humidity (both storage and operating), and power on/off duty cycle. TI recommends that application-specific
effects be considered as early as possible in the design cycle. Contact your local Texas Instruments representative for additional
information related to optimizing the DMD performance.
(5) Simultaneous exposure to high storage temperature and high storage humidity may affect device reliability.
(6) Total integrated illumination power density, above or below the indicated wavelength threshold.
(7) Limited only by the resulting array temperature. Refer to the Thermal Characteristics for information related to calculating the micromirror
array temperature.
(8) Tested in accordance with JESD22-A114-B electrostatic discharge (ESD) sensitivity testing, human-body model (HBM).

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No
level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.
MIN NOM MAX UNIT
ELECTRICAL
VREF LVCMOS interface supply voltage (1) (2) 1.65 1.8 1.95 V
(1) (2)
VCC LVCMOS logic supply voltage 2.375 2.5 2.625 V
VOFFS (1) (2) (3)
Mirror electrode and HVCMOS supply voltage 8.25 8.5 8.75 V
ET
VBIAS Mirror electrode voltage (1) (2) (3) 15.5 16 16.5 V
VRESE
Mirror electrode voltage (1) (2) – 9.5 –10 –10.5 V
T
(3)
Delta supply voltage |VBIAS – VOFFSET| 8.75 V
0.4 × 0.7 ×
VT+ Positive-going threshold voltage V
VREF VREF
0.3 × 0.6 ×
VT– Negative-going threshold voltage V
VREF VREF
0.1 × 0.4 ×
Vhys Hysteresis voltage (VT+ – VT–) V
VREF VREF
fDCLK DCLK clock frequency 60 80 MHz
MECHANICAL
Static load applied to the package electrical connector
45 N
area (4) (5)
Static load applied to the DMD mounting area (6) (5)
100 N
ENVIRONMENTAL
Operating Case Temperature (7) (8) 26 °C
Operating Humidity (7) non-condensing 60 % RH
Operating Device Temperature Gradient (9) 10 °C
Operating Landed Duty-Cycle (7) (10) 25 %

(1) All voltages referenced to VSS (ground)

(2) Voltages VCC, VREF, VOFFSET, VBIAS, VRESET are required for proper DMD operation.
(3) Exceeding the recommended voltage difference between VBIAS and VOFFSET may result in excessive current draw. See the Absolute
Maximum Ratings for further details.
(4) Load should be uniformly distributed across the entire connector area.
(5) See Figure 8.
(6) Load should be uniformly distributed across the three datum-A surfaces.
(7) Optimal, long-term performance of the Digital Micromirror Device (DMD) can be affected by various application parameters, including
illumination spectrum, illumination power density, micromirror landed duty cycle, ambient temperature (both storage and operating), case
temperature, ambient humidity (both storage and operating), and power on/off duty cycle. TI recommends that application-specific
effects be considered as early as possible in the design cycle. Contact your local Texas Instruments representative for additional
information related to optimizing the DMD performance.
(8) Refer to the Thermal Characteristics for the calculation of the micromirror array temperature from the thermal test point TC3 shown in
Figure 15.
(9) As measured between any two points on the exterior of the package, or as predicted between any two points inside the micromirror
array cavity. Refer to the Thermal Characteristics for information related to calculating the micromirror array temperature.
(10) "Landed Duty-Cycle" refers to the percentage of time an individual micromirror spends landed in one state (+12 or -12 degrees) versus
the other state (-12 or +12 degrees).

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Datum ‘A’ Area (3 Places)

DMD Mounting Area (3 Places Opposite Datum ‘A’)

100 N Maximum Uniformly Distributed Over 3 Areas
(See Mechanical ICD for Dimensions of Datum ‘A’)

Connector Area
45 N Maximum

Figure 8. System Interface Loads

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ELECTRICAL CHARACTERISTICS
over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted)
PARAMETER CONDITIONS MIN MAX UNIT
(1)
VOH High-level output voltage VCC = 2.5 V, IOH = –21 mA 1.7 V
VOL Low-level output voltage (1) VCC = 2.5 V, IOH = 15 mA 0.4 V
IOH High-level output current VOH = 1.7 V –15 mA
IOL Low-level output current VOL = 0.4 V 14 mA
IIL Low-level input current VREF = 1.95 V, VI = 0 V –1.6 nA
IIH High-level input current VREF = 1.95 V, VI = VREF 1.9 nA
IREF Current into VREF terminal VREF = 1.95 V, fDCLK = 77 MHz 0.7 mA
ICC Current into VCC terminal VCC = 2.625 V, fDCLK = 77 MHz 55 mA
IOFFSET Current into VOFFSET terminal (2) VOFFSET = 8.75 V 1 mA
(2)
IBIAS Current into VBIAS terminal VBIAS = 17 V 1.6 mA
(2)
IRESET Current into VRESET terminal VRESET = –11 V 1.5 mA
PREF Power into VREF terminal (3) VREF = 1.95 V, fDCLK = 77 MHz 1.5 mW
(3)
PCC Power into VCC terminal VCC = 2.625 V, fDCLK = 77 MHz 144 mW
POFFSET Power into VOFFSET terminal (3) VOFFSET = 8.75 V 9 mW
PBIAS Power into VBIAS terminal (3) VBIAS = 17 V 27.2 mW
(3)
PRESET Power into VRESET terminal VRESET = –11 V 18 mW
CI Input capacitance f = 1 MHz 10 pF
CO Output capacitance f = 1 MHz 10 pF

(1) Applies to LVCMOS pins only

(2) Exceeding the maximum allowable absolute voltage difference between VBIAS and VOFFSET may result in excesses current draw. (See
Absolute Maximum Ratings for details.)
(3) In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See the Thermal
Characteristics for further details.

Measurement Conditions
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 9 shows an equivalent test load circuit for the output
under test. The load capacitance value stated is only for characterization and measurement of ac timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX
and VOH MIN for output clocks.

RL

From Output Tester Channel

Under Test
CL = 50 pF
CL = 5 pF for Disable Time

Figure 9. Test Load Circuit for AC Timing Measurements

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SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Setup time: DATA before rising or falling edge of DCLK 1
ts1 Setup time: TRC before rising or falling edge of DCLK 1 ns
Setup time: SCTRL before rising or falling edge of DCLK 1
ts2 Setup time: LOADB low before rising edge of DCLK 1 ns
ts3 Setup time: SAC_BUS low before rising edge of SAC_CLK 1 ns
ts4 Setup time: DRC_BUS high before rising edge of SAC_CLK 1 ns
ts5 Setup time: DRC_STROBE high before rising edge of SAC_CLK 1 ns
Hold time: DATA after rising or falling edge of DCLK 1
th1 Hold time: TRC after rising or falling edge of DCLK 1 ns
Hold time: SCTRL after rising or falling edge of DCLK 1
th2 Hold time: LOADB low after falling edge of DCLK 1 ns
th3 Hold time: SAC_BUS low after rising edge of SAC_CLK 1 ns
th4 Hold time: DRC_BUS after rising edge of SAC_CLK 1 ns
th5 Hold time: DRC_STROBE after rising edge of SAC_CLK 1 ns
tc1 Clock cycle: DCLK 12.5 16.67 ns
tc3 Clock cycle: SAC_CLK 12.5 16.67 ns
tw1 Pulse width high or low: DCLK 5 ns
tw2 Pulse width low: LOADB 7 ns
tw3 Pulse width high or low: SAC_CLK 5 ns
tw5 Pulse width high: DRC_STROBE 7 ns
Rise time: DCLK / SAC_CLK 2.5
tr ns
Rise time: DATA / TRC / SCTRL / LOADB 2.5
Fall time: DCLK / SAC_CLK 2.5
tf ns
Fall time: DATA / TRC / SCTRL / LOADB 2.5

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tc1
tf tr

DCLK tw1 tw1

ts2
th2
LOADB tw2 th1
ts1
th1
ts1

SCTRL

DATQA_(0:14)

TRC

tc3
tf tr

SAC_CLK tw3 tw3

SAC_BUS th3 ts3

DRC_BUS ts4 th4

DRC_STROBE tw5 ts5 th5

Figure 10. Switching Characteristics

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POWER SUPPLY SEQUENCING REQUIREMENTS

DLP3000 includes four voltage-level supplies (VCC, VREF, VOFFSET, VBIAS, and VRESET). For reliable operation of
DLP3000, the following power supply sequencing requirements must be followed.

CAUTION
Reliable performance of the DMD requires that the following conditions be met:
1. That the VCC, VREF, VOFFSET, VBIAS, and VRESET power supply inputs all be present
during operation.
2. That the VCC, VREF, VOFFSET, VBIAS, and VRESET power supplies be sequenced on
and off in the manner prescribed below.
Repeated failure to adhere to the prescribed power-up and power-down procedures
may affect device reliability

DMD Power Supply Power-Up Procedure

Step 1: Power up VCC and VREF in any order

Step 2: Wait for VCC and VREF to each reach a stable level within their respective recommended operating ranges.

Step 3: Power up VBIAS, VOFFSET, and VRESET in any order, provided that the maximum delta-voltage between VBIAS
and VOFFSET is not exceeded (see Absolute Maximum Ratings for details).

Note 1: During the power-up procedure, the DMD LVCMOS inputs should not be driven high until after Step 2
has been completed.

Note 2: Power supply slew rates during power up are unrestricted, provided that all other conditions are met.

DMD Power Supply Power-Down Procedure

Step 1: Command the chipset controller to execute a mirror-parking sequence. See the controller data sheet
(listed in Related Documents) for details.

Step 2: Power down VBIAS, VOFFSET, and VRESET in any order, provided that the maximum delta voltage between VBIAS
and VOFFSET is not exceeded (see Absolute Maximum Ratings for details).

Step 3: Wait for VBIAS, VOFFSET, and VRESET to each discharge to a stable level within 4 V of the reference ground.

Step 4: Power down VCC and VREF in any order.

Note 1: During the power-down procedure, the DMD LVCMOS inputs should be held at a level less than
VREF + 0.3 volts.

Note 2: Power-supply slew rates during power down are unrestricted, provided that all other conditions
are met.

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VBIAS , VOFFSET ,
Power
and VRESET
Off
Disabled by Software
Control

VCC/ VREF
Mirror Park Sequence
RESET

VSS

RESET AND PARK

VCC/ VREF

VCC/
VREF
VSS VSS
VBIAS ...… ... ...… ... ...… ... … …

VBIAS D V < 8.75 V DV < 8.75

Note1 Note1
VBIAS< 4 V
VSS VSS
VOFFSET ... … ... ...… ... ...… ...… …

VOFFSET

VOFFSET< 4 V
VSS VSS

VRESET< 0.5 V
VSS VSS

VRESET> - 4 V
VRESET

VRESET ... … ... ...… ... ...… ...… …

VCC/ VCCI

LVCMOS
Inputs
VSS VSS

NOTE 1: Delta supply voltage |VBIAS – VOFFSET| < 8.75 V

Figure 11. Power-Up / Power-Down Timing

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Micromirror Array Physical Characteristics

Physical characteristics of the micromirror array are provided in Table 3.

Table 3. Micromirror Array Physical Characteristics

PARAMETER VALUE UNITS
Number of active micromirror rows (1) 684 micromirrors
Number of active micromirror columns (1) 608 micromirrors
(2)
Micromirror pitch, diagonaL 7.637 µm
(2)
Micromirror pitch, vertical and horizontal 10.8 µm

(3)
684 micromirrors
Micromirror active array height
3.699 mm

(3)
604 micromirrors
Micromirror active array width
6.5718 mm
(4)
Micromirror array border 10 mirrors/side

(1) See Figure 14

(2) See Figure 12
(3) SeeFigure 13
(4) The mirrors that form the array border are hard-wired to tilt in the –12°(“Off”) direction once power is applied to the DMD (see Figure 3
and Figure 4).

10.8 mm
7.
10.8 mm

63
7
mm

mm
7
63
7.

Figure 12. DLP3000 Pixel Pitch Dimensions

Pin 1

6571.8 mm
(0,0)
3699 mm

Illumination
On Off
(607,683)

Figure 13. DLP3000 Micromirror Active Area

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Pin 1

Col 607

Col 606
Col 605
Col 604

Col 4

Col 3
Col 1
Col 0
Row 0
Row 1
Row 2
Row 3
Row 4
Row 5
Row 6
Row 7

Incoming Light

Row 607
Row 677
Row 678
Row 679
Row 680
Row 681
Row 682
Row 683

Figure 14. DLP3000 Pixel Arrangement

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Micromirror Array Optical Characteristics

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
See the related application reports (listed in Related Documents) for guidelines.

Table 4. Optical Parameters

MI
PARAMETER CONDITIONS NOM MAX UNIT
N
(1) (2) (3)
DMD parked state ,
0
see Figure 4
Micromirror tilt angle degrees
DMD “landed” state (1) (4) (5),
12
see Figure 4
(1) (4) (6) (7) (8)
Micromirror tilt angle variation See Figure 4 –1 1 degrees
Micromirror crossover time (9) 5 s
(9)
Micromirror switching time 16 s
Non-adjacent micromirrors 10 micromirr
Non-operating micromirrors (10)
Adjacent micromirrors 0 ors
(11)
Orientation of the micromirror axis-of-rotation 89 90 91 degrees
(12) (13) 420 nm to 700 nm,
Micromirror array optical efficiency 68%
with all micromirrors in the ON state
Mirror metal specular reflectivity (420 nm – 700 nm) 89.4%

(1) Measured relative to the plane formed by the overall micromirror array
(2) Parking the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by
the overall micromirror array).
(3) When the micromirror array is parked, the tilt angle of each individual micromirror is uncontrolled.
(4) Additional variation exists between the micromirror array and the package datums.
(5) When the micromirror array is landed, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS
memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in an nominal angular
position of +12 degrees. A binary value of 0 results in a micromirror landing in an nominal angular position of –12 degrees.
(6) Represents the landed tilt angle variation relative to the nominal landed tilt angle
(7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle varation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations and/or system contrast varations.
(9) Performance as measured at the start of life.
(10) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12 degree position to +12 degrees
or vice versa.
(11) Measured relative to the package datums B and C, shown in the Package Mechanical Data section at the end of this document.
(12) The minimum or maximum DMD optical efficiency observed in a specific application depends on numerous application-specific design
variables, such as:
(a) Illumination wavelength, bandwidth/line-width, degree of coherence
(b) Illumination angle, plus angle tolerance
(c) Illumination and projection aperture size, and location in the system optical path
(d) IIllumination overfill of the DMD micromirror array
(e) Aberrations present in the illumination source and/or path
(f) Aberrations present in the projection path
(g) Etc.

The specified nominal DMD optical efficiency is based on the following use conditions:
(a) Visible illumination (420 nm–700 nm)
(b) Input illumination optical axis oriented at 24°relative to the window normal
(c) Projection optical axis oriented at 0°relative to the window normal
(d) f/3 illumination aperture
(e) f/2.4 projection aperture

Based on these use conditions, the nominal DMD optical efficiency results from the following four components:
(a) Micromirror array fill factor: nominally 92.5%
(b) Micromirror array diffraction efficiency: nominally 86%
(c) Micromirror surface reflectivity: nominally 88%
(d) Window transmission: nominally 97% (single pass, through two surface transitions)
(13) Does not account for the effect of micromirror switching duty cycle, which is application dependant. Micromirror switching duty cycle
represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection
path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate.
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Table 4. Optical Parameters (continued)

MI
PARAMETER CONDITIONS NOM MAX UNIT
N
Illumination overfill (14) 10%
Window material Corning Eagle XG
Window refractive index At 546.1 nm 1.5119
See
Window aperture (15)

(14) The active area of the DLP7000 is surrounded by an aperture on the inside of the DMD window surface that masks structures of the
DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area
outside the active array can create artifacts from the mechanical features that surround the active array and other surface anomalies
that may be visible on the projected image. The illumination optical system should be designed to limit light flux incident anywhere
outside the active array less than 10% of the average flux level in the active area. Depending on the particular system's optical
architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause visible artifacts.
(15) See the Package Mechanical Characteristics for details regarding the size and location of the window aperture.

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Thermal Characteristics
Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the
maximum temperature of any individual micromirror in the active array, the maximum temperature of the window
aperture, and the temperature gradient between any two points on or within the package.
See the Absolute Maximum Ratings and Recommended Operation Conditions for applicable temperature limits.

Package Thermal Resistance

The DMD is designed to conduct the absorbed and dissipated heat back to the Series 220 package where it can
be removed by an appropriate system thermal management. The system thermal management must be capable
of maintaining the package within the specified operational temperatures at the Thermal Test Point location, see
Figure 15. The total heat load on the DMD is typically driven by the incident light absorbed by the active area;
although other contributions can include light energy absorbed by the window aperture, electrical power
dissipation of the array, and/or parasitic heating.

Table 5. Package Thermal Resistance

Min Nom Max Units
Thermal resistance from active micromirror array to TC3 5 °C/W

Case Temperature
The temperature of the DMD case can be measured directly. For consistency, a thermal test point location is
defined, as shown in Figure 15.

Figure 15. Thermal Test Point Location

Micromirror Array Temperature Calculation

Micromirror array temperature cannot be measured directly. Therefore, it must be computed analytically from:
Thermal test point location (See Figure 15)
Package thermal resistance
Electrical power dissipation
Illumination heat load
The relationship between the micromirror array and the case temperature is provided by the following equations:
TArray = TCeramic + (QArray × RArray-To-Ceramic)

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QArray = QElec + QIllum

QIllum = CL2W × SL
where the following elements are defined as:
TArray = computed micromirror array temperature (°C)
TCeramic = ceramic case temperature (°C) (TC3 location)
QArray = Total DMD array power (electrical + absorbed) (W)
RArray-to-Ceramic = thermal resistance of DMD package from array to TC3 (°C/W)
QElec = nominal electrical power (W)
QIllum = absorbed illumination heat (W)
CL2W = Lumens-to-watts constant, estimated at 0.00293 watt/lumen , based on array characteristics. It
assumes a spectral efficiency of 300 lumens/watt for the projected light, illumination distribution of 83.7% on
the active array, and 16.3% on the array border and window aperture.
SL = Screen lumens
These equations are based on traditional 1-chip DLP system with a total projection efficiency from the DMD to
the screen of 87%. An example calculation is provided below. DMD electrical power dissipation varies and is
dependent on the voltage, data rates, and operating frequencies. The nominal electrical power dissipation used
in this calculation is 0.15 watts. Screen lumens is nominally 20 lumens. The ceramic case temperature at TC3 is
55 °C. Using these values in the above equations, the following values are computed:
QArray = QElec + CL2W × SL = 0.144 W + (0.00293 W/Lumen × 20 Lumen) = 0.2026 W
TArray = TCeramic + (QArray * RArray-To-Ceramic) = 55°C + (0.2026 W × 5 °C/W) = 56.01°C
SPACER
REVISION HISTORY

Changes from Original (January 2012) to Revision A Page

• Corrected the Operating Case Temperature Typ value From: 25 to 26°C ......................................................................... 12
• Changed the Operating Humidity Typ value From: 50 to 60%RH ...................................................................................... 12
• Corrected the CL2W constant value from: 0.00274 to 0.00293 watt/lumen ......................................................................... 24

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 8 7 6 5 4 3 DWG NO.
2510388
SH
1 1
C COPYRIGHT 2009 TEXAS INSTRUMENTS REVI SI ONS
NOTES UNLESS OTHERWISE SPECIFIED: UN-PUBLISHED, ALL RIGHTS RESERVED. REV DESCRI PTION DATE BY
1 DIE PARALLELISM TOLERANCE APPLIES TO DMD ACTIVE ARRAY ONLY. A ECO 2097098 I NITIAL RELEASE 03/ 02/ 09 J. HOLM
2 ROTATION ANGLE OF DMD ACTIVE ARRAY IS A REFINEMENT OF THE LOCATION ECO 2098984 TIGHTEN DIE ROTATI ON, NOTE 2; ADD 'DD1'
B 08/ 27/ 09 BMH
TOLERANCE AND HAS A MAXIMUM ALLOWED VALUE OF 0.6 DEGREES. SUFFIX TO CONNECTOR PART# ; CHG DWG TO INVENTOR

3 BOUNDARY MIRRORS SURROUNDING THE DMD ACTIVE ARRAY.

4 DMD MARKING TO APPEAR ON BOTTOM OF CONNECTOR.
D 5 NOTCH DIMENSIONS ARE DEFINED BY UPPERMOST LAYERS OF CERAMIC, D
AS SHOWN IN SECTION A-A.
6 ENCAPSULANT TO BE CONTAINED WITHIN DIMENSIONS SHOWN I N VI EWS C
AND G (SHEET 2).

5 2X 0.8 `0.1
4X R0.2 `0.05

5
R0.6 `0.1
C (I LLUMINATION
5 2X R0.4 `0.1 C
DIRECTION)
90° `1° 5 3 `0.075
5
+ 0.3 A
7-
0.1
+ 0.2
3.5 -
0.1
+ 0.2 5
2X 2 -
A 0.1

5
+ 0.2
1 - 0.1 14.6 `0.08 (1)
5
+ 0.3
16.6 -
0.1

WINDOW APERTURE
5
(1.4) (3) D 6
B 1.359 `0.079 0.65 `0.05 2X ENCAPSULANT B
0 MIN
0.4 MIN

(2.139) 3 SURFACES INDICATED

A IN VIEW B (SHEET 2)
0.038 A
1 f
0.02 D
SECTION A-A 0.78 `0.063
NOTCH OFFSETS ACTIVE ARRAY
c 0.05
1.4 `0.1
E E
(SHEET 3) (SHEET 3)
(1.05)

(PANASONIC AXT650224DD1, 50-CONTACT,

0.4 mm PITCH BOARD-TO-BOARD HEADER)
INTERFACE TO PANASONIC AXT550224DD1 SOCKET

DRAWN DATE
UNLESS OTHERWISE SPECIFIED T
A DIMENSIONS ARE IN MILLIMETERS J. HOLM 2/ 25/ 2009 I A
TOLERANCES: ENGINEER Dallas Texas

ANGLES `1~ B. HASKETT 2/ 25/ 2009 TITLE

2 PLACE DECIMALS `0.25
QA/CE ICD, MECHANICAL, DMD,
P. KONRAD 3/ 9/ 2009
1 PLACE DECIMALS `0.50
CM
.3 WVGA DDR SERIES 220
DIMENSIONAL LIMITS APPLY BEFORE PROCESSES
INTERPRET DIMENSIONS IN ACCORDANCE WITH ASME 0.4 mm PITCH CONNECTOR
Y14.5M-1994 SIZE DWG NO REV
THIRD ANGLE
NONE 0314DA REMOVE ALL BURRS AND SHARP EDGES J. GRIMMETT 3/ 9/ 2009
PROJECTION

NEXT ASSY USED ON PARENTHETICAL INFORMATION FOR REFERENCE ONLY

APPROVED
D 2510388 B
APPLICATION SCALE 15:1 SHEET 1 OF 3
INV11-2006a
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 DWG NO.
2510388
SH
2 1

D 0.812 2X 14.6 3X (1)

D

A3 A2

3X 1.7

(3)

n1.5

B
3X (1.8)

6
6
VIEW B 0.812 14.6
C DATUMS A, B, AND C A1 C
(FROM SHEET 1)

( n1.5)

B
6
7.3

3.7
6

B VIEW C B
ENCAPSULANT MAXIMUM X/ Y DIMENSIONS
(FROM SHEET 1)

6
2X 40°

A VIEW G A
ENCAPSULANT HEIGHT LIMITS

DRAWN DATE SIZE DWG NO REV

T J. HOLM 2/ 25/ 2009 2510388
I
D B
Dallas Texas SCALE SHEET 2 OF 3
INV11-2006a
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 DWG NO.
2510388
SH
3 1

D D

3
5.188 `0.075 (6.5718) 4X (0.108)
2 ACTIVE ARRAY
1.624 `0.075

0.377 `0.0885
1.602 `0.05

(3.699) 3.946 `0.0885

(6.516)
WINDOW ACTIVE ARRAY (4.323)
(3)
( n1.5) APERTURE
4.914 `0.05 B F
C C

0.64 `0.0885 6.963 `0.0885

(7.603)
CL APERTURE CL
2.2 `0.05 8.039 `0.05 67X TEST PADS
n0.2 A BC
(10.239) j
n0.1 A
WINDOW
0.314 15 X 1.04 = 15.6
VI EW D (0.52)
4
WINDOW AND ACTIVE ARRAY ( n0.52) TYP. (0.47)
(FROM SHEET 1)
H
B CL G C B
F 2X 0.93

E
2.11

(42°) TYP.
4.22 (3)
25 20 15 10 5 1
( n1.5)
B D

(0.15) TYP. (42°) TYP. C 2X (1.86)

B j 0.4 A BC
A

2 X 0.47 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
(0.068) TYP. = 0.94 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 BACK INDEX MARK
CL 2.212 (11.8)
j 0.4 A BC
DETAI L F
A APERTURE SHORT EDGES VIEW E-E A
SCALE 50 : 1 TEST PADS AND
: CONNECTOR
S
A
C
E
L
5
1
(FROM SHEET 1)

DRAWN DATE SIZE DWG NO REV

T J. HOLM 2/ 25/ 2009 2510388
I
D B
Dallas Texas SCALE SHEET 3 OF 3
INV11-2006a
8 7 6 5 4 3 2 1
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Oct-2012

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
DLP3000FQB ACTIVE LCCC FQB 50 10 Green (RoHS Call TI Level-1-NC-NC
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
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