DLP301S

DLPS215A – JULY 2021 – REVISED SEPTEMBER 2022

DLP301S 0.3-Inch 3.6-Megapixel DMD for TI DLP® 3D Printers

1 Features 3 Description
• 0.3-Inch (7.93-mm) diagonal micromirror array The DLP301S digital micromirror device (DMD) is
– 1280 × 720 array of aluminum micrometer- a digitally controlled micro-opto-electromechanical
sized mirrors, in an orthogonal layout system (MOEMS) spatial light modulator (SLM).
– 3.6 Megapixels, 2560 × 1440 pixels on the When coupled to an appropriate optical system, the
resin DMD displays a very crisp and high-quality image.
– 5.4-micron micromirror pitch This DMD is a component of the chipset comprising
– ±17° micromirror tilt (relative to flat surface) the DLP301S DMD, DLPC1438 3D Print controller,
– Side illumination for optimal efficiency and and DLPA200x/DLPA300x PMIC/LED driver. The
optical engine size compact physical size of this DMD coupled with
– Polarization independent aluminum micromirror the controller and the PMIC/LED driver provides a
surface complete system solution that enables high output
• 8-Bit SubLVDS input data bus optical engines for fast, high resolution, reliable DLP
• Dedicated DLPC1438 3D print controller and 3D printers.
DLPA200x or DLPA300x PMIC/LED driver for Learn more about TI DLP(R) 3D printing technology
reliable operation on the 3D printing and direct imaging products page.
2 Applications The DLP advanced light control resources on ti.com
• TI DLP® 3D Printer accelerate time to market, which include reference
– Additive manufacturing designs, optical modules manufacturers, and DLP
– Vat polymerization design network partners.
– Masked stereolithography (mSLA 3D printer) Device Information(1)
• Dental DLP 3D printer PART NUMBER PACKAGE BODY SIZE (NOM)
• Light exposure: programmable spatial and
DLP301S FQS (99) 19.25 mm × 7.20 mm
temporal light exposure
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

DLPC1438 D_P(0)
Display D_N(0)
Controller VOFFSET DLPA2000
D_P(1) DLPA2005
DLPA3000
D_N(1)
DLPA3005
VBIAS
Power
600 MHz Management
SubLVDS D_P(6) VRESET
DDR
D_N(6) DLP301S DMD
Interface

D_P(7) Digital
Micromirror
D_N(7)
Device
VDDI
DCLK_P
DCLK_N
VDD
LS_WDATA
120 MHz LS_CLK
SDR
Interface LS_RDATA
VSS

DMD_DEN_ARSTZ
(System signal routing omitted for clarity)

Simplified Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................23
2 Applications..................................................................... 1 7.5 Optical Interface and System Image Quality
3 Description.......................................................................1 Considerations............................................................ 23
4 Revision History.............................................................. 2 7.6 Micromirror Array Temperature Calculation.............. 24
5 Pin Configuration and Functions...................................3 7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 25
6 Specifications.................................................................. 7 8 Application and Implementation.................................. 27
6.1 Absolute Maximum Ratings........................................ 7 8.1 Application Information............................................. 27
6.2 Storage Conditions..................................................... 8 8.2 Typical Application.................................................... 27
6.3 ESD Ratings............................................................... 8 9 Power Supply Recommendations................................31
6.4 Recommended Operating Conditions.........................8 9.1 DMD Power Supply Power-Up Procedure................ 31
6.5 Thermal Information..................................................10 9.2 DMD Power Supply Power-Down Procedure........... 31
6.6 Electrical Characteristics...........................................10 9.3 Power Supply Sequencing Requirements................ 32
6.7 Timing Requirements................................................ 11 10 Layout...........................................................................34
6.8 Switching Characteristics..........................................15 10.1 Layout Guidelines................................................... 34
6.9 System Mounting Interface Loads............................ 16 10.2 Layout Example...................................................... 34
6.10 Micromirror Array Physical Characteristics............. 16 11 Device and Documentation Support..........................35
6.11 Micromirror Array Optical Characteristics............... 18 11.1 Device Support........................................................35
6.12 Window Characteristics.......................................... 19 11.2 Receiving Notification of Documentation Updates.. 35
6.13 Chipset Component Usage Specification............... 19 11.3 Support Resources................................................. 35
6.14 Software Requirements.......................................... 20 11.4 Trademarks............................................................. 35
7 Detailed Description......................................................21 11.5 Electrostatic Discharge Caution.............................. 36
7.1 Overview................................................................... 21 11.6 Glossary.................................................................. 36
7.2 Functional Block Diagram......................................... 22 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................23 Information.................................................................... 36

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (July 2021) to Revision A (September 2022) Page

• Changed the device status from Advance Information to Production Data ....................................................... 1
• Updated the Absolute Maximum Ratings disclaimer to the latest TI standard................................................... 7
• Updated Micromirror Array Optical Characteristics ......................................................................................... 18
• Changed Micromirror tilt angle tolerance to ±1.4° in Section 6.11 ...................................................................18
• Changed Micromirror crossover and switching time specification in Section 6.11 to match actual operation
values............................................................................................................................................................... 18
• Added Third-Party Products Disclaimer ...........................................................................................................35

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5 Pin Configuration and Functions

1 3 5 7 17 19 21 23
2 4 6 8 18 20 22 24

A
B
C
D
E
F
G
H

Figure 5-1. FQS Package 99-Pin LGA (Bottom View)

Table 5-1. Pin Functions – Connector Pins(1)

PIN PACKAGE NET
TYPE SIGNAL DATA RATE DESCRIPTION
NAME NO. LENGTH(2) (mm)

DATA INPUTS
D_N(0) C6 I SubLVDS Double Data, Negative 3.15
D_P(0) C5 I SubLVDS Double Data, Positive 3.09
D_N(1) D7 I SubLVDS Double Data, Negative 3.24
D_P(1) D6 I SubLVDS Double Data, Positive 3.29
D_N(2) D5 I SubLVDS Double Data, Negative 2.00
D_P(2) D4 I SubLVDS Double Data, Positive 1.97
D_N(3) F7 I SubLVDS Double Data, Negative 3.96
D_P(3) F6 I SubLVDS Double Data, Positive 4.04
D_N(4) F5 I SubLVDS Double Data, Negative 1.39
D_P(4) F4 I SubLVDS Double Data, Positive 1.39
D_N(5) G6 I SubLVDS Double Data, Negative 2.85
D_P(5) G5 I SubLVDS Double Data, Positive 2.90
D_N(6) H5 I SubLVDS Double Data, Negative 2.37
D_P(6) H4 I SubLVDS Double Data, Positive 2.37
D_N(7) H7 I SubLVDS Double Data, Negative 3.22
D_P(7) H6 I SubLVDS Double Data, Positive 3.26
DCLK_N E6 I SubLVDS Double Clock, Negative 2.33
DCLK_P E5 I SubLVDS Double Clock, Positive 2.33
CONTROL INPUTS
LS_WDATA B3 I LPSDR(1) Single Write data for low speed interface. 17.1
LS_CLK B5 I LPSDR Single Clock for low-speed interface 15.28
Asynchronous reset DMD signal. A low signal
places the DMD in reset. A high signal releases
DMD_DEN_ARSTZ B2 I LPSDR 17.91
the DMD from reset and places it in active
mode.
LS_RDATA B7 O LPSDR Single Read data for low-speed interface 12.29
POWER (3)
VBIAS A6 Power Supply voltage for positive bias level at
VBIAS A22 Power micromirrors

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Table 5-1. Pin Functions – Connector Pins(1) (continued)

PIN PACKAGE NET
TYPE SIGNAL DATA RATE DESCRIPTION
NAME NO. LENGTH(2) (mm)

VOFFSET B21 Power Supply voltage for HVCMOS core logic. Supply
voltage for stepped high level at micromirror
VOFFSET G2 Power address electrodes.
Supply voltage for offset level at micromirrors.
VRESET A5 Power Supply voltage for negative reset level at
VRESET A23 Power micromirrors.

VDD C2 Power
VDD A19 Power
VDD A20 Power
VDD A21 Power
Supply voltage for LVCMOS core logic. Supply
VDD B20 Power voltage for LPSDR inputs.
VDD C2 Power Supply voltage for normal high level at
micromirror address electrodes.
VDD D2 Power
VDD D3 Power
VDD D23 Power
VDD E2 Power
VDD F2 Power
VDD F3 Power
VDD F23 Power
VDDI B6 Power
VDDI B19 Power
VDDI C3 Power
VDDI C23 Power
Supply voltage for SubLVDS receivers.
VDDI E3 Power
VDDI E23 Power
VDDI G3 Power
VDDI G23 Power
VSS A2 Ground
VSS A3 Ground
VSS A4 Ground
VSS A7 Ground
VSS A24 Ground
VSS B22 Ground
VSS B23 Ground
VSS B24 Ground Common return. Ground for all power
VSS C4 Ground
VSS C7 Ground
VSS C19 Ground
VSS C22 Ground
VSS E4 Ground
VSS E7 Ground

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Table 5-1. Pin Functions – Connector Pins(1) (continued)

PIN PACKAGE NET
TYPE SIGNAL DATA RATE DESCRIPTION
NAME NO. LENGTH(2) (mm)

VSS E19 Ground

VSS E22 Ground
VSS G4 Ground
Common return. Ground for all power
VSS G7 Ground
VSS G19 Ground
VSS G22 Ground
VSS G24 Ground
VSS H2 Ground
VSS H3 Ground
VSS H23 Ground
VSS H24 Ground

(1) Low speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQS ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769 inches/ns.
Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm.
(3) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.

Table 5-2. Pin Functions – No Connect

NUMBER SYSTEM BOARD
TEST PADS
A1 Do not connect.
A17 Do not connect.
A18 Do not connect.
B8 Do not connect.
B17 Do not connect.
B18 Do not connect.
C8 Do not connect.
UNUSED PINS
B4 Do not connect.
C20 Do not connect.
C21 Do not connect.
D19 Do not connect.
D20 Do not connect.
D21 Do not connect.
D22 Do not connect.
E20 Do not connect.
E21 Do not connect.
F19 Do not connect.
F20 Do not connect.
F21 Do not connect.
F22 Do not connect.
G20 Do not connect.
G21 Do not connect.
H19 Do not connect.
H20 Do not connect.

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Table 5-2. Pin Functions – No Connect (continued)

NUMBER SYSTEM BOARD
H21 Do not connect.
H22 Do not connect.

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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
Supply voltage for LVCMOS core logic(2)
VDD –0.5 2.3 V
Supply voltage for LPSDR low speed interface
VDDI Supply voltage for SubLVDS receivers(2) –0.5 2.3 V
Supply voltage for HVCMOS and micromirror
VOFFSET –0.5 11 V
electrode(2) (3)
Supply voltage VBIAS Supply voltage for micromirror electrode(2) –0.5 19 V
VRESET Supply voltage for micromirror electrode(2) –15 0.5 V
| VDDI–VDD | Supply voltage delta (absolute value)(4) 0.3 V
| VBIAS–VOFFSET | Supply voltage delta (absolute value)(5) 11 V
| VBIAS–VRESET | Supply voltage delta (absolute value)(6) 34 V
Input voltage for other inputs LPSDR(2) –0.5 VDD + 0.5 V
Input voltage
Input voltage for other inputs SubLVDS(2) (7) –0.5 VDDI + 0.5 V
| VID | SubLVDS input differential voltage (absolute value)(7) 810 mV
Input pins
IID SubLVDS input differential current 10 mA

Clock ƒclock Clock frequency for low speed interface LS_CLK 130 MHz
frequency ƒclock Clock frequency for high speed interface DCLK 560 MHz
Temperature – operational (8) –20 90 °C
TARRAY and TWINDOW
Temperature – non-operational(8) –40 90 °C

Environmental TDP Dew Point Temperature - operating and non-operating

81 °C
(non-condensing)
Absolute Temperature delta between any point on the
|TDELTA| 30 °C
window edge and the ceramic test point TP1(9)

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:
VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.
(3) VOFFSET supply transients must fall within specified voltages.
(4) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current
draw.
(6) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current
draw.
(7) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential
inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(8) The highest temperature of the active array (as calculated in Section 7.6) or of any point along the Window Edge as defined in Section
7.6. The locations of thermal test points TP2 and TP3 in Section 7.6 are intended to measure the highest window edge temperature. If
a particular application causes another point on the window edge to be at a higher temperature, that point should be used.
(9) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Section 7.6. The window test points TP2 and TP3 shown in Section 7.6 are intended to result in the worst case delta. If a particular
application causes another point on the window edge to result in a larger delta temperature, that point should be used.

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6.2 Storage Conditions

applicable for the DMD as a component or non-operational in a system
MIN MAX UNIT
TDMD DMD storage temperature –40 85 °C
TDP-AVG Average dew point temperature, (non-condensing)(1) 24 °C
TDP-ELR Elevated dew point temperature range, (non-condensing)(2) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 6 Months

(1) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.

6.3 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN NOM MAX UNIT
SUPPLY VOLTAGE RANGE(3)
Supply voltage for LVCMOS core logic
VDD 1.65 1.8 1.95 V
Supply voltage for LPSDR low-speed interface
VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V
VOFFSET Supply voltage for HVCMOS and micromirror electrode(4) 9.5 10 10.5 V
VBIAS Supply voltage for mirror electrode 17.5 18 18.5 V
VRESET Supply voltage for micromirror electrode –14.5 –14 –13.5 V
|VDDI–VDD| Supply voltage delta (absolute value)(5) 0.3 V
|VBIAS–VOFFSET| Supply voltage delta (absolute value)(6) 10.5 V
|VBIAS–VRESET| Supply voltage delta (absolute value)(7) 33 V
CLOCK FREQUENCY
ƒclock Clock frequency for low speed interface LS_CLK(8) 108 120 MHz
ƒclock Clock frequency for high speed interface DCLK(9) 300 540 MHz
Duty cycle distortion DCLK 44% 56%
SUBLVDS INTERFACE(9)
SubLVDS input differential voltage (absolute value) Figure 6-9,
| VID | 150 250 350 mV
Figure 6-10
VCM Common mode voltage Figure 6-9, Figure 6-10 700 900 1100 mV
VSUBLVDS SubLVDS voltage Figure 6-9, Figure 6-10 575 1225 mV
ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω
ZIN Internal differential termination resistance Figure 6-11 80 100 120 Ω
100-Ω differential PCB trace 6.35 152.4 mm

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6.4 Recommended Operating Conditions (continued)

Over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN NOM MAX UNIT
ENVIRONMENTAL
Array Temperature – long-term operational(10) (11) (12) 0 40
TARRAY Array Temperature - short-term operational, 25 hr max(11) (13) –20 –10 °C
Array Temperature - short-term operational, 500 hr max(11) (13) –10 0
Absolute Temperature difference between any point on the window
|TDELTA | 15 °C
edge and the ceramic test point TP1 (14)
TWINDOW Window temperature – operational(15) 85 °C
TDP-AVG Average dew point temperature (non-condensing)(16) 24 °C
TDP-ELR Elevated dew point temperature range (non-condensing)(17) 28 36 °C
CTELR Cumulative time in elevated dew point temperature range 6 Months
QAP-ILL Illumination overfill in critical area(19) (20) 0 W/cm2
ILLUV Illumination wavelengths < 380 nm(10) 2 mW/cm2
ILL380 - 390 nm Illumination wavelengths between 380 nm and 390 nm 55 mW/cm2
ILL390 - 400 nm Illumination wavelengths between 390 nm and 400 nm 450 mW/cm2
ILL400 - 550 nm Illumination wavelengths between 400 nm and 550 nm 3 W/cm2
ILL> 550 nm Illumination wavelengths > 550 nm 10 mW/cm2
ILLθ Illumination marginal ray angle(18) 55 deg

(1) Section 6.4 is applicable after the DMD is installed in the final product.
(2) The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by
Section 6.4. No level of performance is implied when operating the device above or below the Section 6.4 limits.
(3) All voltage values are with respect to the ground pins (VSS).
(4) VOFFSET supply transients must fall within specified maximum voltages.
(5) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(6) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(7) To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.
(8) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.
(9) Refer to the SubLVDS timing requirements in Section 6.7.
(10) Simultaneous exposure of the DMD to the maximum limits in Section 6.4 for temperature and UV illumination will reduce device
lifetime.
(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Section 7.6 and the Package Thermal Resistance using Section 7.6.
(12) Long-term is defined as the usable life of the device.
(13) Short-term is the total cumulative time over the useful life of the device.
(14) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge shown in
Section 7.6. The window test points TP2 and TP3 shown in Section 7.6 are intended to result in the worst case delta temperature. If a
particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
(15) Window temperature is the highest temperature on the window edge shown in Section 7.6. The locations of thermal test points TP2
and TP3 in Section 7.6 are intended to measure the highest window edge temperature. If a particular application causes another point
on the window edge to result in a higher temperature, that point should be used.
(16) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
(18) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(19) The active area of the device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD
device assembly from normal view. The window aperture is sized to anticipate several optical operating conditions. Overfill light directly
illuminating the window aperture can create adverse imaging effects, and additional device heating leading to reduced device lifetime.
Direct incident illumination should be prevented from striking the DMD window aperture.
(20) Applies to the region in red in Figure 6-1, at the inside plane of the glass window where the physical aperture is located.

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4X 0.52 mm critical area on aperture

Array
Window

Window

Figure 6-1. Illumination Overfill Diagram—Critical Area

6.5 Thermal Information

DLP301S
THERMAL METRIC(1) FQS (LGA) UNIT
99 PINS
Thermal resistance Active area to test point 1 (TP1)(1) 2.7 °C/W

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by
the incident light absorbed by the active area although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(10)
PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT
CURRENT
VDD = 1.95 V 60.5
IDD Supply current: VDD(3) (5) mA
VDD = 1.8 V 54
VDDI = 1.95 V 16.5
IDDI Supply current: VDDI(3) (5) mA
VDD = 1.8 V 11.3
VOFFSET = 10.5 V 2.2
IOFFSET Supply current: VOFFSET(4) (6) mA
VOFFSET = 10 V 1.5
VBIAS = 18.5 V 0.6
IBIAS Supply current: VBIAS(4) (6) mA
VBIAS = 18 V 0.3
VRESET = –14.5 V 2.4
IRESET Supply current: VRESET(6) mA
VRESET = –14 V 1.7
POWER(1)
VDD = 1.95 V 118
PDD Supply power dissipation: VDD(3) (5) mW
VDD = 1.8 V 95
VDDI = 1.95 V 32
PDDI Supply power dissipation: VDDI(3) (5) mW
VDD = 1.8 V 20

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6.6 Electrical Characteristics (continued)

Over operating free-air temperature range (unless otherwise noted)(10)
PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT

Supply power dissipation: VOFFSET = 10.5 V 23

POFFSET mW
VOFFSET(4) (6) VOFFSET = 10 V 15
VBIAS = 18.5 V 11
PBIAS Supply power dissipation: VBIAS(4) (6) mW
VBIAS = 18 V 6
VRESET = –14.5 V 35
PRESET Supply power dissipation: VRESET(6) mW
VRESET = –14 V 24
PTOTAL Supply power dissipation: Total 160 219 mW
LPSDR INPUT(7)
VIH(DC) DC input high voltage(9) 0.7 × VDD VDD + 0.3 V
VIL(DC) DC input low voltage(9) –0.3 0.3 × VDD V
VIH(AC) AC input high voltage(9) 0.8 × VDD VDD + 0.3 V
VIL(AC) AC input low voltage(9) –0.3 0.2 × VDD V
∆VT Hysteresis ( VT+ – VT– ) Figure 6-12 0.1 × VDD 0.4 × VDD V
IIL Low–level input current VDD = 1.95 V; VI = 0 V –100 nA
IIH High–level input current VDD = 1.95 V; VI = 1.95 V 100 nA
LPSDR OUTPUT(8)
VOH DC output high voltage IOH = –2 mA 0.8 × VDD V
VOL DC output low voltage IOL = 2 mA 0.2 × VDD V
CAPACITANCE
Input capacitance LPSDR ƒ = 1 MHz 10 pF
CIN
Input capacitance SubLVDS ƒ = 1 MHz 10 pF
COUT Output capacitance ƒ = 1 MHz 10 pF

(1) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.
(4) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
(5) Supply power dissipation based on non-compressed commands and data
(6) Supply power dissipation based on three global resets in 200 µs
(7) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(8) LPSDR specification is for pin LS_RDATA.
(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) Device electrical characteristics are over Section 6.4 unless otherwise noted.

6.7 Timing Requirements

Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN NOM MAX UNIT
LPSDR
tr Rise slew rate(1) (30% to 80%) × VDD, Figure 6-3 1 3 V/ns
tƒ Fall slew rate(1) (70% to 20%) × VDD, Figure 6-3 1 3 V/ns
tr Rise slew rate(2) (20% to 80%) × VDD, Figure 6-4 0.25 V/ns
tƒ Fall slew rate(2) (80% to 20%) × VDD, Figure 6-4 0.25 V/ns
tc Cycle time LS_CLK, Figure 6-2 7.7 8.3 ns
tW(H) Pulse duration LS_CLK high 50% to 50% reference points, Figure 6-2 3.1 ns
tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 6-2 3.1 ns
LS_WDATA valid before LS_CLK ↑,
tsu Setup time 1.5 ns
Figure 6-2

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6.7 Timing Requirements (continued)

Device electrical characteristics are over Section 6.4 unless otherwise noted.
MIN NOM MAX UNIT
LS_WDATA valid after LS_CLK ↑, Figure
th Hold time 1.5 ns
6-2
tWINDOW Window time(1) (4) Setup time + Hold time, Figure 6-2 3 ns
For each 0.25 V/ns reduction in slew rate
tDERATING Window time derating(1) (4) 0.35 ns
below 1 V/ns, Figure 6-6
SubLVDS
tr Rise slew rate 20% to 80% reference points, Figure 6-5 0.7 1 V/ns
tƒ Fall slew rate 80% to 20% reference points, Figure 6-5 0.7 1 V/ns
tc Cycle time DCLK, Figure 6-7 1.79 1.85 ns
tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6-7 0.79 ns
tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6-7 0.79 ns
D(0:3) valid before
tsu Setup time
DCLK ↑ or DCLK ↓, Figure 6-7
D(0:3) valid after
th Hold time
DCLK ↑ or DCLK ↓, Figure 6-7
Setup time + Hold time, Figure 6-7,
tWINDOW Window time 0.3 ns
Figure 6-8
tLVDS-
Power-up receiver(3) 2000 ns
ENABLE+REFGEN

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3.
(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-4.
(3) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.
(4) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

tC
tw(H) tw(L)

50%

LS_CLK

tSU| tH|

50%

LS_WDATA
tWINDOW|

Low-speed interface is LPSDR and adheres to the Section 6.6 and AC/DC Operating Conditions table in JEDEC Standard No. 209B,
Low Power Double Data Rate (LPDDR) JESD209B.

Figure 6-2. LPSDR Switching Parameters

LS_CLK and LS_WDATA

100
VDD Voltage (%)

VIH(AC)
80
VIH(DC)
70

VIL(DC)
30
VIL(AC)
20

tR tF

Time

Figure 6-3. LPSDR Input Slew Rate

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DMD_DEN_ARSTZ
100

VDD Voltage (%)

80

VIL(AC)
20

tR tF

Time

Figure 6-4. LPSDR Input Slew Rate

VDCLK_P and VDCLK_N

VD_P(0:3) and VD_N(0:3)
100
VID Voltage (%)

80
70

VCM
50

20

tR tF

Time

Figure 6-5. SubLVDS Input Rise and Fall Slew Rate

VIH MIN
LS_CLK Midpoint
VIL MAX

tSU tH

VIH MIN
LS_WDATA Midpoint
VIL MAX

tWINDOW

VIH MIN
LS_CLK Midpoint
VIL MAX
tDERATING
tSU tH

VIH MIN
LS_WDATA Midpoint
VIL MAX

tWINDOW
Figure 6-6. Window Time Derating Concept

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tC
tw(L) tw(H)

DCLK_P

50%

DCLK_N

tSU| tH|
D_P(0:7)

50%
D_N(0:7)
tWINDOW|

Figure 6-7. SubLVDS Switching Parameters

tC
(1)
tWINDOW |
DCLK_P

50%

DCLK_N

¼ tC| ¼ tC|
D_P(0:7)

50%
D_N(0:7)

(1) High-speed training scan window

(2) Refer to Section 7.3.3 for details

Figure 6-8. High-Speed Training Scan Window

+ (VIP + VIN)
VCM =
± 2
DCLP_P, D_P(0:7)

VID
DCLP_N, D_N(0:7)
SubLVDS
Receiver

VCM VIP VIN

Figure 6-9. SubLVDS Voltage Parameters

1.255 V

VLVDS(max)

VCM VID

VLVDS(min)

0.575 V

Figure 6-10. SubLVDS Waveform Parameters

VSubLVDS(max) = VCM(max) + ½ × |VID(max)|

VSubLVDS(min) = VCM(min) – ½ × |VID(max)|

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DCLP_P, D_P(0:7)

ESD
Internal
Termination
SubLVDS
DCLP_N, D_N(0:7) Receiver

ESD

Figure 6-11. SubLVDS Equivalent Input Circuit

LS_CLK and LS_WDATA

VCC18 Voltage (%)

VIH
VT+

'VT

VT±
VIL

Time

Figure 6-12. LPSDR Input Hysteresis

LS_CLK

LS_WDATA Stop Start

tPD

LS_RDATA
Acknowledge

Figure 6-13. LPSDR Read Out

Timing specification reference point

Device pin
Tester channel
output under test
CL

See Section 7.3.4 for more information.

Figure 6-14. Test Load Circuit for Output Propagation Measurement

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CL = 5 pF 11.1 ns
Output propagation, Clock to Q, rising
tPD edge of LS_CLK input to LS_RDATA CL = 10 pF 11.3 ns
output. Figure 6-13
CL = 85 pF 15 ns
Slew rate, LS_RDATA 0.5 V/ns

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Over operating free-air temperature range (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output duty cycle distortion, LS_RDATA 40% 60%

6.9 System Mounting Interface Loads

PARAMETER MIN NOM MAX UNIT
Maximum system mounting interface load to Thermal Interface Area (see Figure 6-15) 60 N
be applied to the:
Clamping and Electrical Interface Area (see 110 N
Figure 6-15)

Datum 'A' Areas

(3 Places)

Datum 'E' Area

(1 Place)

Thermal Interface Area

Electrical Interface Area

Figure 6-15. System Interface Loads

6.10 Micromirror Array Physical Characteristics

PARAMETER VALUE UNIT
Number of active columns See Figure 6-16 1280 micromirrors
Number of active rows See Figure 6-16 720 micromirrors
ε Micromirror (pixel) pitch See Figure 6-17 5.4 µm
Micromirror pitch × number of active
Micromirror active array width 6.912 mm
columns; see Figure 6-16
Micromirror pitch × number of active rows;
Micromirror active array height 3.888 mm
see Figure 6-16
micromirrors/
Micromirror active border Pond of micromirror (POM)(1) 20
side

(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.

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Width .

Mirror 719
Mirror 718
Mirror 717
Mirror 716

Illumination 1280 × 720 mirrors

Height

Mirror 3
Mirror 2
Mirror 1
Mirror 0
Mirror 0
Mirror 1
Mirror 2
Mirror 3

Mirror 1276
Mirror 1277
Mirror 1278
Mirror 1279
Figure 6-16. Micromirror Array Physical Characteristics

H°

H° H°

H°

Figure 6-17. Mirror (Pixel) Pitch

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6.11 Micromirror Array Optical Characteristics

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Micromirror tilt angle DMD landed state(1) 17 degree
Micromirror tilt angle tolerance(2) (3) (4) (5) –1.4 1.4 degree
Landed ON state 180
Micromirror tilt direction (6) (7) degree
Landed OFF state 270
Micromirror crossover time(8) Typical performance 1 3
µs
Micromirror switching time(9) Typical performance 10
Bright pixel(s) in active area
(11) Gray 10 Screen (12) 0

Bright pixel(s) in the POM (13) Gray 10 Screen (12) 1

Image Dark pixel(s) in the active
White Screen 4 micromirrors
performance(10) area (14)
Adjacent pixel(s) (15) Any Screen 0
Unstable pixel(s) in active
Any Screen 0
area (16)

(1) Measured relative to the plane formed by the overall micromirror array.
(2) Additional variation exists between the micromirror array and the package datums.
(3) Represents the landed tilt angle variation relative to the nominal landed tilt angle.
(4) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result
in colorimetry variations, system efficiency variations, or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON state
direction. A binary value of 0 results in a micromirror landing in the OFF state direction. See Figure 6-18.
(7) Micromirror tilt direction is measured as in a typical polar coordinate system: Measuring counter-clockwise from a 0° reference which is
aligned with the +X Cartesian axis.
(8) The time required for a micromirror to nominally transition from one landed state to the opposite landed state.
(9) The minimum time between successive transitions of a micromirror.
(10) Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions:
Test set degamma shall be linear
Test set brightness and contrast shall be set to nominal
The diagonal size of the projected image shall be a minimum of 20 inches
The projections screen shall be 1X gain
The projected image shall be inspected from a 38 inch minimum viewing distance
The image shall be in focus during all image quality tests
(11) Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels
(12) Gray 10 screen definition: All areas of the screen are colored with the following settings:
Red = 10/255
Green = 10/255
Blue = 10/255
(13) POM definition: Rectangular border of off-state mirrors surrounding the active area
(14) Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels
(15) Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster
(16) Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable
pixel appears to be flickering asynchronously with the image.

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(1279, 719)

Incident
illumination
light path On-state Tilted axis of
landed edge pixel rotation

Off-state
(0, 0) landed edge

Off-state
light path
Bond pad 1

Figure 6-18. Landed Pixel Orientation and Tilt

6.12 Window Characteristics

PARAMETER(3) MIN TYP MAX UNIT
Window material Corning Eagle
XG
Window aperture(1) See (1)
Illumination overfill(2) See (2)
Window transmittance, single-pass Minimum within the wavelength range 390
93% 99%
through both surfaces and glass (4) nm to 450 nm, 0-30° AOI.
Average within the wavelength range 390 nm
98% 99%
to 450 nm, 0-30° AOI.
Minimum within the wavelength range 450
75% 90%
nm to 550 nm. 0-30° AOI.

(1) See the package mechanical characteristics for details regarding the size and location of the window aperture.
(2) The active area of the DLP301S device is surrounded by an aperture on the inside of the DMD window surface that masks structures
of the DMD device assembly from normal view. The window aperture is sized to anticipate several optical operating conditions. Overfill
light directly illuminating the window aperture can create adverse imaging effects, and additional device heating leading to reduced
device lifetime. Direct incident illumination should be prevented from striking the DMD window aperture.
(3) See Section 7.5 for more information.
(4) See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP DMD Window.

SPACER
6.13 Chipset Component Usage Specification
The DLP301S is a component of one or more TI DLP® chipsets. Reliable function and operation of the DLP301S
requires that it be used in conjunction with the other components of the applicable DLP chipset, including
those components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP DMD.

Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.

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6.14 Software Requirements

CAUTION
The DLP301S DMD has mandatory software requirements. Refer to Software Requirements for TI
DLP®Pico® TRP Digital Micromirror Devices application report for additional information. Failure to
use the specified software will result in failure at power up.

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7 Detailed Description
7.1 Overview
The DLP301S DMD is a 0.3 inch diagonal spatial light modulator of aluminum micromirrors. Pixel array size
is 1280 columns by 720 rows in a square grid pixel arrangement. The fast switching speed of the DMD
micromirrors combined with advanced DLP image processing algorithms enable each micromirror to display 4
distinct pixels on the resin during every frame, resulting in a full 3.6MP image being projected upon the resin.
The electrical interface is Sub Low Voltage Differential Signaling (SubLVDS) data.
This DMD is part of the chipset that includes the DLP301S DMD, DLPC1438 display and light controller and
DLPA200x/DLPA300x PMIC/LED driver. To ensure reliable operation, this DMD must always be used with
DLPC1438 display and light controller and DLPA200x/DLPA300x PMIC/LED driver.

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7.2 Functional Block Diagram

A. Details are omitted for clarity.

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B. Orientation is not representative of optical system.

C. Scale is not representative of layout.

7.3 Feature Description

7.3.1 Power Interface
The power management IC, DLPA200x/DLPA300x, contains 3 regulated DC supplies for the DMD reset circuitry:
VBIAS, VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC1438 controller.
7.3.2 Low-Speed Interface
The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is
the low–speed clock, and LS_WDATA is the low speed data input.
7.3.3 High-Speed Interface
The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed
DDR transfer and compression techniques to save power and time. The high-speed interface is composed of
differential SubLVDS receivers for inputs, with a dedicated clock.
7.3.4 Timing
The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics
and its transmission line effects must be considered. Test Load Circuit for Output Propagation Measurement
shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as
a precise representation of any particular system environment or depiction of the actual load presented by a
production test. TI recommends that system designers use IBIS or other simulation tools to correlate the timing
reference load to a system environment. The load capacitance value stated is intended for characterization and
measurement of AC timing signals only. This load capacitance value does not indicate the maximum load the
device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC1438 controller. See the DLPC1438 controller data sheet or
contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
Note
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system
operating conditions exceeding limits described previously.

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
is typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless
appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from
the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from
any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

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than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts
in the display border or active area may occur.
7.5.1.2 Pupil Match
The optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border or active area. These artifacts may require additional system apertures to control,
especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.1.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside of the DMD window surface that masks
structures of the DMD device assembly from normal view. The window aperture is sized to anticipate several
optical operating conditions. Overfill light directly illuminating the window aperture can create adverse imaging
effects, and additional device heating leading to reduced device lifetime. Direct incident illumination should be
prevented from striking the DMD window aperture.
7.6 Micromirror Array Temperature Calculation
Array TP2

TP4
TP5
Illumination
Direction

2X 3.76

TP3
2X 8.70
Off-state
Light
Window Edge
TP4 (4 surfaces) TP3 (TP2) TP5

TP1

TP1 8.70

1.00

Figure 7-1. Thermal Test Point Location—FQS Package

Micromirror array temperature cannot be measured directly, therefore it must be computed analytically from
measurement points on the outside of the package, the package thermal resistance, the electrical power, and
the illumination heat load. The relationship between array temperature and the reference ceramic temperature
shown as TP1 in Figure 7-1 is provided by the following equations:

TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC) (1)

QARRAY = QELECTRICAL + QILLUMINATION (2)

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where
• TARRAY = Computed micromirror array temperature (°C)
• TCERAMIC = Measured ceramic temperature (°C) (TP1 location)
• RARRAY-TO-CERAMIC = Thermal resistance of package specified in Section 6.5 from array to ceramic TP1
(°C/W)
• QARRAY = Total DMD power on the array (electrical + absorbed) (W)
• QELECTRICAL = Nominal electrical power (W)
• QINCIDENT = measured total illumination optical power at DMD (W)
• QILLUMINATION = (QINCIDENT × DMD average thermal absorptivity) (W)
• DMD average thermal absorptivity = 0.40
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.1 W. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for each DMD chip in a system. It
assumes illumination distribution of 83.7% on the active array and 16.3% on the area outside the array.

QELECTRICAL = 0.1 W (3)

QINCIDENT = 0.9 W (measured) (4)

TCERAMIC = 35.0 °C (measured) (5)

QARRAY = 0.1 W + (0.9 W x 0.40) = 0.46 W (6)

TARRAY = 35.0 °C + (0.46 W x 2.7 °C /W) = 36.2°C (7)

7.7 Micromirror Landed-On/Landed-Off Duty Cycle

7.7.1 Definition of Micromirror Landed-On and Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the
time (and in the OFF state 25% of the time), whereas 25/75 indicates that the pixel is in the OFF state 75% of
the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time.
When assessing landed duty cycle, the time spent switching from the current state to the opposite state is
considered negligible and is thus ignored.
Because a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
nominally add to 100. In practice, image processing algorithms in the DLP chipset can result a total of less that
100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the micromirror array (also called the active array) to an asymmetric landed duty
cycle for a prolonged period of time can reduce the usable life of the DMD.
The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being
equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0
or 0/100 is perfectly asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect the usable life of the DMD. This interaction
can be used to reduce the impact that an asymmetrical landed duty cycle has on the useable life of the DMD.

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7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel depends on the image content being
displayed by that pixel. To enhance reliability, when coupled with the DLPC1438 controller, the DLP301S DMD
operates at a maximum 78/22 duty cycle and a minimum of 22/78 duty cycle.
In the simplest case for example, when the system displays maximum full scale brightness on a given pixel for a
given time period, that pixel operates very close to a 78/22 landed duty cycle during that time period. Likewise,
when the system displays a pixel value of zero, the pixel operates very close to a 22/78 landed duty cycle.
The nominal landed duty cycle is additionally biased from the worst case above toward 50/50 during the time
between print layers. The duty cycle approaches 50/50 when the illuminated print time is the same as the
between layer time.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of
two directions, with the primary direction being into a projection or collection optic. Each application depends
primarily on the optical architecture of the system and format of the data coming into the DLPC1438 controller.
Applications include:
• DLP 3D Printer
– Additive manufacturing
– Vat polymerization
– Masked stereolithography (mSLA 3D printer)
• Light exposure: programmable spatial and temporal light exposure
DMD power-up and power-down sequencing is strictly controlled by the DLPA200x/DLPA300x. Refer to Section
9 for power-up and power-down specifications. For reliable operation, the DLP301S DMD must be used with the
DLPC1438 controller and DLPA200x/DLPA300x PMIC/LED driver.
8.2 Typical Application
Figure 8-1 and Figure 8-2 show typical DLP 3D printer system block diagrams using the DLP301S DMD,
DLPC1438 controller, and DLPA200x PMIC/LED driver.

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1.1 V
1.1 Reg L3

SYSPWR L2
DC
Supplies
1.8 V external 1.8 V

L1
DLPA200x
VLED
1.8 V VSPI
PROJ_ON

LED_SEL (2)
PROJ_ON GPIO_8 SPI1 SPI (4)
2
I C RESETZ RLIM
Video PARKZ INTZ Thermistor
HOST_IRQ
Front End CMP_OUT
2 VDDLP12
SPI_RDY I C
Parallel (12) VDD 1.1 V Illumination
SPI (4) FPGA
System FPGA_READY DLPC1438 optics
Controller ACT_SYNC SPI0 GPIO_10 RC_
CHARGE
VBIAS, VOFFSET,
Flash 1.8 V VCC_18 VRESET
VCC_INTF CTRL DMD
Frame VCC_FLSH Sub-LVDS DATA
Memory SPI (4) 1.8 V
Flash
TI DLP Chipset
Actuator
Actuator Non-TI Device
Driver

Optional Non-TI Device

Figure 8-1. With FPGA

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1.1 V
1.1 Reg L3

SYSPWR L2
DC
Supplies
1.8 V external 1.8 V

L1
DLPA200x
VLED
1.8 V VSPI
PROJ_ON

LED_SEL (2)
PROJ_ON GPIO_8 SPI1 SPI (4)
2
I C RESETZ RLIM
PARKZ INTZ Thermistor
HOST_IRQ
CMP_OUT
Front End VDDLP12
Processor Parallel (12) VDD 1.1 V Illumination
DLPC1438 optics
SPI0 GPIO_10 RC_
CHARGE
VBIAS, VOFFSET,
1.8 V VCC_18 VRESET
VCC_INTF CTRL DMD
VCC_FLSH Sub-LVDS DATA
SPI (4) 1.8 V
Flash
TI DLP Chipset

Non-TI Device

Figure 8-2. Without FPGA

8.2.1 Design Requirements

A DLP 3D printer can be created using the DLP301S, DLPC1438, and DLPA200x/DLPA300x PMIC/LED driver.
In addition to the DLP chipset, other IC components may be needed including a flash device to store the
software and firmware to control the DLPC1438.
A 405nm LED typically supplies the illumination for the DMD. In addition to LEDs, other light sources are
supported.
8.2.2 Detailed Design Procedure
The optical engine, which includes the LED, DMD, and sometimes the electronics is typically supplied by an
optical OEM who specializes in designing optics for DLP projectors.
8.2.3 Application Curve
This device drives current though the LED(s). As the LED current increases, the brightness of the optical engine
increases. This increase is somewhat non-linear, and the curve for typical optical output power changes with
LED currents as shown in Figure 8-3.
SPACE

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1
0.9
0.8
0.7

Luminance
0.6
0.5
0.4
0.3
0.2
0.1
0
0 100 200 300 400 500 600 700
Current (mA) D001

Figure 8-3. Optical Output vs LED Current

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9 Power Supply Recommendations

The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VDD
• VDDI
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLPAxxxx device.

CAUTION
For reliable operation of the DMD, the following power supply sequencing requirements must be
followed. Failure to adhere to any of the prescribed power-up and power-down requirements may
affect device reliability. See the DMD power supply sequencing requirements in Figure 9-1.
VBIAS, VDD, VDDI, VOFFSET, and VRESET power supplies must be coordinated during power-up and
power-down operations. Failure to meet any of the below requirements will result in a significant
reduction in the DMD reliability and lifetime. Common ground VSS must also be connected.

9.1 DMD Power Supply Power-Up Procedure

• During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are
applied to the DMD.
• During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Section 6.4. Refer to Table 9-1 for power-up delay requirements.
• During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS and VOFFSET.
• Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in Section 6.1, in Section 6.4, and in Section 9.3.
• During power-up, LPSDR input pins must not be driven high until after VDD /VDDI have settled at operating
voltages listed in Section 6.4.
9.2 DMD Power Supply Power-Down Procedure
• Power-down sequence is the reverse order of the previous power-up sequence. During power-down, VDD and
VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground.
• During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Section 6.4.
• During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS and
VOFFSET.
• Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in Section 6.1, in Section 6.4, and in Section 9.3.
• During power-down, LPSDR input pins must be less than VDD /VDDI specified in Section 6.4.

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9.3 Power Supply Sequencing Requirements

DLP Display Controller and DLP Display Controller and PMIC
PMIC control start of DMD Mirror Park disable VBIAS, VOFFSET and
operation Sequence VRESET
Note 4
Power Off
VDD / VDDI VDD / VDDI

VDD / VDDI VSS VSS

VBIAS VBIAS

ûV < Specification Limit

ûV < Specification Limit

ûV < Specification Limit

VBIAS
VDD < VBIAS <6V
VBIAS < 4 V

VSS VSS
Note 1
Note 2

Note 3

Note 2
VOFFSET VOFFSET

VDD < VOFFSET < 6 V

VOFFSET VOFFSET < 4 V

VSS VSS

VRESET < 0.5 V

VSS VSS

VRESET > - 4 V

VRESET

VRESET VRESET

VDD VDD

DMD_DEN_ARSTZ VSS VSS

INITIALIZATION VDD VDD

LS_CLK
VSS VSS
LS_WDATA

VID VID
D_P(0:3), D_N(0:3)
VSS VSS
DCLK_P, DCLK_N

A. Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements.
B. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Section 6.4. OEMs may find that
the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during
power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements.
C. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Section 6.4.
D. When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the
Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the Micromirror Park Sequence through
software control.
E. Drawing is not to scale and details are omitted for clarity.

Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down)

Table 9-1. Power-Up Sequence Delay Requirement

PARAMETER MIN MAX UNIT
tDELAY Delay requirement from VOFFSET power up to VBIAS power up 2 ms
VOFFSET Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V

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Table 9-1. Power-Up Sequence Delay Requirement (continued)

PARAMETER MIN MAX UNIT
VBIAS Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V

VOFFSET Voltage (V)

12 VOFFSET

8
9'' ” 92))6(7 ” 6 V
4
VSS
0
tDELAY
20 VBIAS

16
VBIAS Voltage (V)

12

8
9'' ” 9%,$6 ” 6 V
4
VSS
0
Time

A. Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay.

Figure 9-2. Power-Up Sequence Delay Requirement

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10 Layout
10.1 Layout Guidelines
There are no specific layout guidelines for the DMD as typically DMD is connected using a board to board
connector to a flex cable. Flex cable provides the interface of data and control signals between the DLPC1438
controller and the DLP301S DMD. For detailed layout guidelines refer to the layout design files. Some layout
guideline for the flex cable interface with DMD are:
• Match lengths for the LS_WDATA and LS_CLK signals.
• Minimize vias, layer changes, and turns for the HS bus signals. Refer Top Layer.
• Minimum of two 100-nF decoupling capacitor close to VBIAS. Capacitor C6 and C7 in Top Layer.
• Minimum of two 100-nF decoupling capacitor close to VRESET. Capacitor C9 and C8 in Top Layer.
• Minimum of two 220-nF decoupling capacitor close to VOFFSET. Capacitor C5 and C4 in Top Layer.
• Minimum of four 100-nF decoupling capacitor close to VDDI and VDD. Capacitor C1, C2, C3 and C10 in Top
Layer.
10.2 Layout Example

Top Layer Layer 2

Layer 3 Bottom Layer

Figure 10-1. DMD Signal Routing

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Device Nomenclature

DLP301S FQS
Package Type
Device Descriptor

Figure 11-1. Part Number Description

11.1.3 Device Markings

The device marking includes the legible character string GHJJJJK DLP301SFQS. GHJJJJK is the lot trace code.
DLP301SFQS is the orderable device number.

Two-dimension matrix code

DMD part number and lot Lot Trace Code
trace code

GHJJJJK

DLP301SFQS

Part Marking

Figure 11-2. DMD Marking

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.

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DLP® and Pico® are registered trademarks of Texas Instruments.

All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DLP301SFQS ACTIVE CLGA FQS 99 120 RoHS & Green NI/AU N / A for Pkg Type 0 to 40 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
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