An Ultra-Low-Power ADPLL for

WPAN Applications
Design, Implementation, and Validation

Vamshi Krishna Chillara

Master of Science Thesis

Electronics
An Ultra-Low-Power ADPLL for WPAN
Applications
Design, Implementation, and Validation

Master of Science Thesis

For the degree of Master of Science in Electrical Engineering

at Delft University of Technology

Vamshi Krishna Chillara

November 15, 2013

Faculty of Electrical Engineering Mathematics and Computer Science (EEMCS) ·

Delft University of Technology
Copyright c Electrical Engineering
All rights reserved.
 Delft University of Technology
Department of
Electrical Engineering

The undersigned hereby certify that they have read and recommend
to the Faculty of Electrical Engineering Mathematics and Computer
Science (EEMCS) for acceptance a thesis entitled
An Ultra-Low-Power ADPLL for WPAN Applications
by
Vamshi Krishna Chillara
in partial fulfillment of the requirements for the degree of
Master of Science Electrical Engineering

Dated: November 15, 2013

Supervisor(s):
Prof. Dr. Robert Bogdan Staszewski

Dr. Yao-Hong Liu

Reader(s):
Dr. Ir. Wouter A. Serdijn

Prof. Dr. Edoardo Charbon

Ir. Ying Wu
 Abstract

RF PLLs for frequency synthesis and modulation consume a significant share of

the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios.
Compared to analog PLLs, all-digital phase-locked loops (ADPLLs) are preferred in
nanoscale CMOS, as they offer benefits of smaller area, programmability, capability
of extensive self-calibrations, and easy portability. However, analog PLLs dominate
the ulp arena, since the time-to-digital converter (TDC) of an ADPLL has tradi-
tionally been power hungry. In this work [1], an ultra-low power 2.1 GHz – 2.7 GHz
fractional-N ADPLL is presented for wireless personal area network (WPAN) applica-
tions. A DTC-assisted snapshot TDC and a DC-coupled DCO buffer with a tunable
voltage transfer characteristic (VTC) are proposed to lower the power consumption.
The ADPLL prototype fabricated in TSMC LP 40 nm CMOS process consumes only
860 µW at 1 V supply, and has a measured rms jitter of 1.71 ps (integrated from
1k to 100MHz), leading to a state-of-the-art jitter2 -power FoM of -236 dB. The
frequency modulation capability is also demonstrated with a 2 Mcps HS-OQPSK
modulation for IEEE 802.15.4 (ZigBee) and 1 Mbps GFSK for Bluetooth Smart. This
work presents the first-ever wireless ADPLL to break the 1mW barrier and consumes
at least five-times lower power compared to state-of-the-art ADPLLs. The presented
low-power techniques enable the adoption of ADPLLs in the emerging ultra-low-power
applications.

Master of Science Thesis i Vamshi Krishna Chillara

ii Abstract

Vamshi Krishna Chillara Master of Science Thesis

 Acknowledgements

I would like to thank my supervisor, Prof. Robert Bogdan Staszewski, who intro-
duced me to this exciting field of Digital-RF. Needless to say, his constant guidance,
encouragement, and immense knowledge were indispensable for successful comple-
tion of this work. I am glad (rather relieved) that I did not mar his immaculate
record of first-time silicon success with ADPLLs.
I want to thank Dr. Wouter Serdijn, Prof. Edoardo Charbon, and Ying Wu for
reading my thesis and serving on my committee.
I would like to thank Dr. Kathleen Philips for providing the opportunity to work
at imec-nl. My daily-supervisors, Dr. Maja Vidojković and Dr. Yao-Hong Liu, had
been of great support and guidance through out, and I cannot thank them enough.
Maja got me started, helped me with the layout during the tape-out crunch, and was
always there for any advice—technical or otherwise. Yao-Hong was the go-to guy
for most part of my work, and we spent a lot of time having detailed discussions on
every conceivable issue. He coordinated this two-student project, and also brought
delicious home-cooked lunches when we had to work over weekends.
I owe special thanks to Bindi Wang for her meticulous design of the TDC and DTC,
and importantly, for being a great company during times we had to work long. I
should thank Xiongchuan (Coby) Huang and Ao Ba for their help in designing the
DCO. Ao also designed the PA used in this work. I want to acknowledge the generous
support of Benjamin Büsze in synthesizing the digital logic. I am grateful to Sandra
and Marion for helping with the administrative tasks.
Ini and Sangan deserve special mention, for one cannot endure microelectronics at
Delft, and remain sane without amazing friends. Also, Satoshi should be thanked
for organizing get-togethers, visits, and ensuring we felt at home amidst all the
dutch-eccentricities.
Last thanks, as always, goes to my family for their unconditional love and support.
My brother has been a great friend and mentor through out my life, and I will always
strive to emulate him. My mom and dad did all they could to ensure I have a better
life; I am fortunate to have them in my life. I should acknowledge Google Hangouts
for connecting us from across three continents.

Master of Science Thesis iii Vamshi Krishna Chillara

 Table of Contents

Abstract i

Acknowledgements iii

1 Introduction 1
1-1 Frequency synthesis in wireless transceivers . . . . . . . . . . . . . . . . 1
1-1-1 Metrics of a frequency synthesizer . . . . . . . . . . . . . . . . . 2
1-1-2 Impact of phase noise on transceiver operation . . . . . . . . . . 3
1-2 PLL based frequency synthesis . . . . . . . . . . . . . . . . . . . . . . . 5
1-2-1 Charge-pump phase-locked loop . . . . . . . . . . . . . . . . . . 5
1-3 Motivation and thesis objectives . . . . . . . . . . . . . . . . . . . . . . 7
1-3-1 Target specifications . . . . . . . . . . . . . . . . . . . . . . . . 8
1-4 Research contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1-5 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 All-digital phase-locked loops 11

2-1 Existing architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2-1-1 Divider-less ADPLL . . . . . . . . . . . . . . . . . . . . . . . . . 11
2-1-2 Divider-based ADPLL . . . . . . . . . . . . . . . . . . . . . . . . 13
2-1-3 Comparison of divider-less and divider-based architectures . . . . 13
2-2 Requirements on TDC and DCO . . . . . . . . . . . . . . . . . . . . . . 14
2-2-1 Impact of TDC on phase noise . . . . . . . . . . . . . . . . . . . 14
2-2-2 Impact of DCO on phase noise . . . . . . . . . . . . . . . . . . . 15
2-3 Direct frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . 16
2-3-1 Two-point frequency modulation . . . . . . . . . . . . . . . . . 16
2-4 Challenges for ultra-low-power applications . . . . . . . . . . . . . . . . 17
2-4-1 Reducing the TDC detection range . . . . . . . . . . . . . . . . 17
2-4-2 Lowering the operating frequency of TDC . . . . . . . . . . . . . 18
2-5 DTC-assisted snapshot TDC based ADPLL . . . . . . . . . . . . . . . . . 19
2-5-1 Phase prediction . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2-5-2 Snapshotting and CKR generation . . . . . . . . . . . . . . . . . 23
2-5-3 Low-speed digital logic . . . . . . . . . . . . . . . . . . . . . . . 24

Master of Science Thesis v Vamshi Krishna Chillara

vi Table of Contents

3 RTL design 27
3-1 RTL design of low-speed digital logic . . . . . . . . . . . . . . . . . . . 27
3-1-1 Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . 28
3-1-2 TX interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3-1-3 TDC readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3-1-4 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3-1-5 Loop filter—PVT bank . . . . . . . . . . . . . . . . . . . . . . . 34
3-1-6 Loop filter—Acquisition bank . . . . . . . . . . . . . . . . . . . 36
3-1-7 Loop filter—Tracking bank . . . . . . . . . . . . . . . . . . . . 36
3-2 System simulation in Verilog . . . . . . . . . . . . . . . . . . . . . . . . 39
3-3 Estimated power consumption . . . . . . . . . . . . . . . . . . . . . . . 41

4 Circuit design 43
4-1 Digitally controlled oscillator (DCO) . . . . . . . . . . . . . . . . . . . . 43
4-1-1 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4-1-2 Active part and biasing . . . . . . . . . . . . . . . . . . . . . . 46
4-1-3 Capacitor banks . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4-1-4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4-2 DCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4-2-1 Self-biased inverter . . . . . . . . . . . . . . . . . . . . . . . . . 59
4-2-2 DC coupled buffer with tunable VTC . . . . . . . . . . . . . . . 60
4-3 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4-3-1 Transmission-gate based dynamic divider . . . . . . . . . . . . . 63
4-3-2 Tri-state inverter based dynamic divider . . . . . . . . . . . . . . 64
4-3-3 Post-layout simulations . . . . . . . . . . . . . . . . . . . . . . 64
4-4 Phase incrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5 Measurements 69
5-1 ADPLL test plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5-2 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5-2-1 Open-loop DCO measurements . . . . . . . . . . . . . . . . . . . 70
5-2-2 Loop-locking behavior . . . . . . . . . . . . . . . . . . . . . . . 73
5-2-3 Spectral purity and phase noise . . . . . . . . . . . . . . . . . . 74
5-2-4 Direct frequency modulation . . . . . . . . . . . . . . . . . . . . 76
5-2-5 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . 79
5-2-6 Performance summary and comparison . . . . . . . . . . . . . . 79

6 Conclusions 81
6-1 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

A Chip pinout, bonding diagram, and measurement setup 83

B Simulations 87
B-1 Simulations of the capacitor banks . . . . . . . . . . . . . . . . . . . . 87

Vamshi Krishna Chillara Master of Science Thesis

Table of Contents vii

Bibliography 93

Glossary 99
List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Master of Science Thesis Vamshi Krishna Chillara

viii Table of Contents

Vamshi Krishna Chillara Master of Science Thesis

 List of Figures

1-1 Low-power transceiver architecture. . . . . . . . . . . . . . . . . . . . . 2

1-2 Frequency synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1-3 Phase noise and spurious tones. . . . . . . . . . . . . . . . . . . . . . . 4
1-4 Effect of tx phase noise. . . . . . . . . . . . . . . . . . . . . . . . . . 4
1-5 Effect of LO phase noise on receiver. . . . . . . . . . . . . . . . . . . . 4
1-6 PLL based frequency synthesizer. . . . . . . . . . . . . . . . . . . . . . 5
1-7 Simplified block diagram of charge-pump phase-locked loop (CP-PLL). . . 6
1-8 Benchmark of fractional-N ADPLLs. . . . . . . . . . . . . . . . . . . . . 8

2-1 Architecture of divider-less ADPLL. . . . . . . . . . . . . . . . . . . . . 12

2-2 Architecture of divider-based ADPLL. . . . . . . . . . . . . . . . . . . . 13
2-3 Two-point frequency modulation in divider-less ADPLL architecture. . . . 16
2-4 Principle of phase-prediction to reduce fractional-phase detection range. . 18
2-5 Top-level block diagram of the ADPLL. . . . . . . . . . . . . . . . . . . 21
2-6 Idea of digital-to-time converter (DTC) gain calibration [48]. . . . . . . . 22
2-7 tdc snapshotting and ckr generation. . . . . . . . . . . . . . . . . . . 23

3-1 Top-level block diagram of low-speed logic. . . . . . . . . . . . . . . . . 28

3-2 FSM of the implemented ADPLL. . . . . . . . . . . . . . . . . . . . . . 29
3-3 Implementation of tx interface block. . . . . . . . . . . . . . . . . . . 30
3-4 Implementation of TDC readout block. . . . . . . . . . . . . . . . . . . 31
3-5 Decoding the output of TDC. . . . . . . . . . . . . . . . . . . . . . . . 32
3-6 Implementation of phase detector block. . . . . . . . . . . . . . . . . . 33
3-7 Loop filter—top level block diagram. . . . . . . . . . . . . . . . . . . . 34
3-8 Loop filter and normalization for PVT bank. . . . . . . . . . . . . . . . . 35
3-9 Loop filter and normalization for acquisition bank. . . . . . . . . . . . . 37
3-10 Loop filter and normalization for tracking bank. . . . . . . . . . . . . . . 38
3-11 First order Σ∆ modulator. . . . . . . . . . . . . . . . . . . . . . . . . . 39

Master of Science Thesis ix Vamshi Krishna Chillara

x List of Figures

3-12 System level ADPLL simulation. . . . . . . . . . . . . . . . . . . . . . . 40

3-13 System level ADPLL simulation—PVT state. . . . . . . . . . . . . . . . . 40
3-14 System level ADPLL simulation—acquisition state. . . . . . . . . . . . . 40
3-15 System level ADPLL simulation—tracking state. . . . . . . . . . . . . . . 40

4-1 RLC model of the LC tank. . . . . . . . . . . . . . . . . . . . . . . . . 44

4-2 Inductance vs frequency across process corners. . . . . . . . . . . . . . . 45
4-3 Q-factor vs frequency across process corners. . . . . . . . . . . . . . . . 46
4-4 Circuit schematic of the implemented DCO. . . . . . . . . . . . . . . . . 47
4-5 Layout of the active part of the DCO. . . . . . . . . . . . . . . . . . . . 48
4-6 Switched MOM configuration. . . . . . . . . . . . . . . . . . . . . . . . 49
4-7 Circuit schematic of the unit cell of PVT bank. . . . . . . . . . . . . . . 50
4-8 Layout of the PVT bank. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4-9 Capacitance range of the PVT bank. . . . . . . . . . . . . . . . . . . . . 51
4-10 Layout of the acquisition bank. . . . . . . . . . . . . . . . . . . . . . . 52
4-11 Capacitance range of the acquisition bank. . . . . . . . . . . . . . . . . 53
4-12 Circuit schematic of the unit cell of tracking bank. . . . . . . . . . . . . 53
4-13 Circuit schematic of the MSB cell of tracking bank. . . . . . . . . . . . 55
4-14 Physical layout of the unit cell of tracking bank . . . . . . . . . . . . . . 55
4-15 Physical layout of the tracking bank. . . . . . . . . . . . . . . . . . . . 56
4-16 Capacitance range of the tracking bank. . . . . . . . . . . . . . . . . . 56
4-17 Layout of the DCO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4-18 Transient simulation of the DCO. . . . . . . . . . . . . . . . . . . . . . 58
4-19 Phase-noise simulation of the DCO. . . . . . . . . . . . . . . . . . . . . 58
4-20 Self-biased inverter as the DCO buffer. . . . . . . . . . . . . . . . . . . . 59
4-21 Biasing the self-biased inverter. . . . . . . . . . . . . . . . . . . . . . . 59
4-22 Tuning the VTC of the inverter. . . . . . . . . . . . . . . . . . . . . . . 60
4-23 Schematic of the proposed VTC-tunable buffer. . . . . . . . . . . . . . . 61
4-24 Operation of the buffer across process corners and phase-noise. . . . . . 62
4-25 Transmission-gate based dynamic CMOS divider. . . . . . . . . . . . . . 63
4-26 Tri-state inverter based dynamic CMOS divider. . . . . . . . . . . . . . 64
4-27 Simplified schematic of the implemented divider. . . . . . . . . . . . . . 65
4-28 Transient simulation of the divider at 1 V and 0.9 V supply. . . . . . . . 65
4-29 Phase noise of the divider at 1 V and 0.9 V supply. . . . . . . . . . . . . 66
4-30 Timing waveforms of ckvd2, ckr, and phase incrementer output. . . . 67
4-31 Circuit schematic of the phase incrementer. . . . . . . . . . . . . . . . . 68

5-1 Chip-micrograph of the ADPLL prototype. . . . . . . . . . . . . . . . . . 69

5-2 Block diagram of ADPLL test setup. . . . . . . . . . . . . . . . . . . . . 70
5-3 Measured tuning range of the DCO at 1 V supply. . . . . . . . . . . . . . 71
5-4 Measured tuning range of the tracking bank of the DCO. . . . . . . . . . 72
5-5 Measured phase noise of the DCO. . . . . . . . . . . . . . . . . . . . . . 73

Vamshi Krishna Chillara Master of Science Thesis

List of Figures xi

5-6 Measured phase noise of the DCO versus current. . . . . . . . . . . . . . 74

5-7 Measured settling behavior of the ADPLL. . . . . . . . . . . . . . . . . . 74
5-8 Output spectrum of the ADPLL for FCW = 37.5. . . . . . . . . . . . . . 75
5-9 Fractional spur over Bluetooth Smart channels. . . . . . . . . . . . . . . 75
5-10 Measured phase noise of the synthesizer for FCW = 38.125. . . . . . . . 75
5-11 Measured phase noise of the synthesizer for FCW = 37.5. . . . . . . . . . 76
5-12 Measured ZigBee modulation accuracy. . . . . . . . . . . . . . . . . . . 77
5-13 Measured ZigBee spectrum. . . . . . . . . . . . . . . . . . . . . . . . . 77
5-14 Measured Bluetooth Smart modulation accuracy. . . . . . . . . . . . . . 78
5-15 Measured Bluetooth Smart spectrum. . . . . . . . . . . . . . . . . . . . 78
5-16 Jitter variance-power plot of state-of-the-art PLLs. . . . . . . . . . . . . 80

6-1 FoM versus power consumption of state-of-the-art PLLs. . . . . . . . . . 82

A-1 Bonding diagram of the ADPLL IC. . . . . . . . . . . . . . . . . . . . . 83

A-2 Photograph of the test PCB. . . . . . . . . . . . . . . . . . . . . . . . . 85
A-3 Photograph of the test bench setup. . . . . . . . . . . . . . . . . . . . 85

B-1 C–V curve of the unit cell of the PVT bank. . . . . . . . . . . . . . . . . 87

B-2 Quality factor of the unit cell of the PVT bank. . . . . . . . . . . . . . . 88
B-3 C–V curve of the unit cell of the acquisition bank. . . . . . . . . . . . . 88
B-4 Quality factor of the unit cell of the acquisition bank. . . . . . . . . . . 89
B-5 C–V curve of the LSB cell of the tracking bank. . . . . . . . . . . . . . 89
B-6 Quality factor of the LSB cell of the tracking bank. . . . . . . . . . . . . 90
B-7 C–V curve of the MSB cell of the tracking bank. . . . . . . . . . . . . . 90
B-8 Quality factor of the MSB cell of the tracking bank. . . . . . . . . . . . 91

Master of Science Thesis Vamshi Krishna Chillara

xii List of Figures

Vamshi Krishna Chillara Master of Science Thesis

 List of Tables

1-1 Target specifications of the frequency synthesizer. . . . . . . . . . . . . 9

3-1 Estimated power breakdown of the low-speed digital logic. . . . . . . . . 41

4-1 Summary of capacitor banks. . . . . . . . . . . . . . . . . . . . . . . . 56

5-1 Measurement results of capacitor banks at around 2.4 GHz . . . . . . . 72

5-2 Measured power break-down of the ADPLL. . . . . . . . . . . . . . . . . 79
5-3 Comparison with the state-of-the-art. . . . . . . . . . . . . . . . . . . . 80

A-1 Chip pinout of the ADPLL prototype. . . . . . . . . . . . . . . . . . . . 84

Master of Science Thesis xiii Vamshi Krishna Chillara

xiv List of Tables

Vamshi Krishna Chillara Master of Science Thesis

 Chapter 1

Introduction

Wireless communications have seen an explosive growth in the last decade. Anytime
anyplace connectivity is now a reality with smart phones becoming integral to our
daily lives. Although proliferation of smart mobile devices will continue to propel
the semiconductor market, many untapped opportunities exist in the realm of short-
range low-cost wireless networks. These small, low-cost autonomous sensor-nodes
have applications ranging from health care monitoring to home automation and
environment sensing. It is these networks of tiny sensor-nodes that have the potential
to trigger the next wireless revolution after cell phones and internet. Low-cost high-
volume requirements of these sensor nodes fare well with the integration and scaling
trends of CMOS. However, the autonomous operation requires the power consumption
to be as low as possible. Power budget analysis of such sensor nodes reveals that the
wireless transceiver dominates the overall power. This, together with the need for
large volume, low-cost, highly integrated solutions warrant the need for ultra-low-
power RF transceivers in nanometer scale digital CMOS technologies. This thesis is
an effort in that direction and deals with the design of an ultra-low power all-digital
phase-locked loop (ADPLL) for frequency synthesis in wireless transceivers.

1-1 Frequency synthesis in wireless transceivers

Figure 1-1 shows a simplified block diagram of a typical low-power transceiver. A
low-IF receiver and direct modulation transmitter are typically the preferred ar-
chitectures in low-power low-cost applications owing to their power and cost effi-
ciency [2–5].
In a low-IF receiver, the received radio frequency (RF) signal from the antenna is
down-converted to a low intermediate frequency (IF) by a quadrature mixer after
amplification by a low-noise amplifier (LNA). After low pass filtering and boosting
the signal amplitude to the required level by means of a programmable gain amplifier
(PGA), the signal is fed to an analog-to-digital converter (ADC). The digitized data
is then processed by the digital baseband which recovers the transmitted bits. On
the transmit side, the digital baseband converts the user data to symbols, which are

Master of Science Thesis 1 Vamshi Krishna Chillara

2 Introduction

Mixer Low-pass filter

I
PGA ADC
RX data
LOI
LNA

LOQ
Q
PGA ADC
RX data

Frequency FM
PA
synthesizer
TX data
AM

Figure 1-1: Low-power transceiver architecture.

pulse shaped to obtain I and Q digital samples. These I and Q samples are then
transformed to polar form with amplitude and phase components. The frequency
data—obtained from differentiating1 the phase data—then modulates the synthesizer
while the amplitude data controls the power amplifier. Thus, polar architecture
avoids the need for up-conversion mixers and instead uses direct modulation, thereby
saving power and area. Thus, a frequency synthesizer is an integral part of the
transceiver and plays a key role in both receive path—to generate local oscillator
(LO) signal for down-conversion—as well as in the transmit path, for direct frequency
modulation.

1-1-1 Metrics of a frequency synthesizer

A local oscillator (LO) that generates a signal with programmable frequency enables
up/down conversion in a wireless transceiver. A frequency synthesizer is normally
used as it can provide signals with high spectral purity over wide range of fre-
quencies. Moreover, it enables direct frequency modulation in polar transmitters.
Figure 1-2 shows the functional block diagram of such a frequency synthesizer. A

Frequency Fout
XTAL
Fref synthesizer

FCW

Figure 1-2: Frequency synthesis.

frequency synthesizer takes a low frequency clean reference from a crystal oscillator2
implemented as difference between consecutive samples.
1

On chip replacements for crystal oscillators such as thermal diffusivity based [6] and MEMS
2

based [7] references is an active area of research but crystal based references currently dominate [8].

Elec
Vamshi Krishna Chillara Master of Science Thesis
1-1 Frequency synthesis in wireless transceivers 3

as an input and generates an output signal with a frequency determined by the

frequency command word (FCW). Some common metrics to gauge the performance
of a frequency synthesizer are discussed here.

Frequency tuning range and resolution

This denotes the range of frequencies that the synthesizer can generate with accept-
able spectral purity and resolution. For instance, a frequency synthesizer designed for
a 2.4 GHz Bluetooth Smart transceiver should cover the frequencies from 2.402 GHz
to 2.480 GHz with a step of 2 MHz. Moreover, the accuracy with which the required
channel frequency can be acquired is also crucial and is specified as parts-per-million.
Variations over process, voltage, and temperature (PVT) should be considered while
formulating the synthesizer specifications.

Channel switching time

Another important constraint on the synthesizer is its switching time—the time it

takes to switch from one channel to another with a required accuracy. This can
be crucial for some applications requiring fast switching such as frequency hopping
spread spectrum. Moreover, the PLL consumes more power in the transient state
compared to the locked state. Thus, fast switching helps to save power in ultra-low-
power applications such as Bluetooth Smart.

Spectral purity

The required spectral purity is usually specified as a spectral mask that the syn-
thesizer should satisfy. Both random and periodic fluctuations corrupt the spectral
purity of a frequency synthesizer. The output of a frequency synthesizer can be
represented in time-domain by Eq. (1-1).

v(t) = A sin(ωc t + ψ(t)) (1-1)

where A represents the amplitude of the synthesized signal with frequency ωc . ψ(t)
captures the phase fluctuations. The impact of amplitude noise is generally neglected
as it can be alleviated by a limiter circuit. Phase fluctuations in turn are divided
into random and periodic variations as shown in Eq. (1-2).

ψ(t) = ∆ψ sin(ωm t) + φ(t) (1-2)

The first term denotes the periodic variations, which appear as a spurious tone at a
frequency ωm from the carrier. The random fluctuations, φ(t), manifest themselves
as a noise-skirt around the desired frequency (see Figure 1-3).

1-1-2 Impact of phase noise on transceiver operation

Both the spurious tones and the noise skirt degrade the performance of the transceiver.
The spot value of the phase noise spectrum at a particular frequency and the integral

Master of Science Thesis Vamshi Krishna Chillara

4 Introduction

Noise-skirt

spur spur

ωc ω
ωm ωm
Figure 1-3: Phase noise and spurious tones.

of phase spectral density over a frequency range can both impair the performance
of the transceiver. On the transmit side, noise-skirt on the LO signal can make it a
potential interferer (blocker) to a near-by receiver detecting a signal in the adjacent
frequency channel (see Figure 1-4).
Figure 1-5 shows the impact of the phase noise of the frequency synthesizer on the
receiver in the presence of a large blocker in the near-by frequency channel. If the

Near-by TX
Wanted
signal

ω
Figure 1-4: Effect of tx phase noise.

blocker

blocker
signal

ωRF ωRF + ωm ω ωIF ωIF + ωm ω

ωLO ω

Figure 1-5: Effect of LO phase noise on receiver.

LO is ideal and has a spectrum of Dirac delta function, δ, then the down-converted
blocker is at offset ωm from the wanted signal and hence can be filtered off. However,
if LO signal has a phase-noise skirt or a spectral tone at that offset, the blocker and

Vamshi Krishna Chillara Master of Science Thesis

1-2 PLL based frequency synthesis 5

wanted signal are down-converted to the same IF frequency, thereby degrading the
signal-to-noise ratio (SNR).

1-2 PLL based frequency synthesis

Although other methods such as direct digital synthesis or look-up table synthesis
exist, phase-locked loop (PLL) based indirect frequency synthesis is widely used in
wireless applications owing to its spectral purity and energy efficiency. Figure 1-6
depicts a simple block diagram of a PLL based frequency synthesizer.
PLL is a negative feedback system that ensures that the phase of the desired output
signal is locked to that of a known stable reference. The phase detector compares the
phase of the reference signal with the output signal and generates the phase error.
This phase difference is processed by the loop filter—to set the loop dynamics—and
is then used to control the oscillator. In the steady state, the error signal in the loop
is forced to a constant value ensuring that the phases of two signals are locked and
hence the frequencies.3 In some implementations, a frequency divider is placed in
the feedback path so that a high frequency signal can be generated from a lower
reference frequency.
The frequency synthesis in wireless transceivers is dominated by charge-pump phase-
locked loops (CP-PLLs) and all-digital phase-locked loops (ADPLLs), which differ
in the implementation of the aforementioned building blocks. With the advent of
nano-scale CMOS, ADPLLs have begun to supplant the traditional CP-PLLs in most
applications.

phase OTW Controlled FLO

Fref detector oscillator
Loop filter

Fdiv Frequency
divider
Figure 1-6: PLL based frequency synthesizer.

1-2-1 Charge-pump phase-locked loop

Figure 1-7 shows a simplified block diagram of the conventional CP-PLL. The con-
trolled oscillator of Figure 1-6 is implemented as a voltage-controlled oscillator
(VCO)—controlled by an analog input voltage. The phase frequency detector (PFD)
compares the phase of the reference signal and the divided down output signal, Fdiv ,
to generate an up/down pulse with a width proportional to the phase error. The
3
frequency being the derivative of phase, a constant phase difference translates to zero frequency
difference.

Master of Science Thesis Vamshi Krishna Chillara

6 Introduction

output of the phase detector controls the magnitude and direction of the charge-
pump current that is pumped into or out of the loop filter. The passive loop-filter
converts this current into a tuning voltage for the VCO while suppressing the noise
from the reference signal and the phase frequency detector. The output frequency
of the VCO is adjusted such that the steady-state phase difference becomes constant
and the output frequency is N times the input reference frequency.
In integer-N synthesizers, the reference frequency limits the frequency resolution. A
fine frequency resolution requires a small reference frequency which limits the maxi-
mum loop-bandwidth that can be attained owing to the concerns of loop stability [9].
Loop-bandwidth is usually chosen not greater than one-tenth of the reference fre-
quency. A wide loop bandwidth might be needed for higher suppression of oscillator
phase noise or for faster switching speeds. Also, a small reference frequency needs
a large multiplying factor N. Noise on the reference signal is amplified by N2 and
hence a very large value of N is not desired.
To decouple this bandwidth-resolution trade-off, fractional-N synthesizers evolved.
The division ratio of the multi-modulus divider toggles between two integer values
e.g., N and N+1, to achieve the required fractional division on average. The divider
control is generated by a Σ∆ modulator to scramble the control pattern so that the
resulting quantization noise is high-pass shaped. Consequently, Σ∆ control of the
divider ratio enables a fine frequency resolution with a large reference frequency.
However, the bandwidth cannot be too large since the quantization induced phase
noise should be sufficiently filtered.
Charge-pump

VDD

Phase/freqeuncy IP
detector VCO
up
Loop filter
FREF Fvco
PFD
IN
down C2 R1

C1

Fdiv
÷(N + b)
Frequency
divider
b(t)
Σ∆
modulator

Figure 1-7: Simplified block diagram of charge-pump phase-locked loop (CP-PLL).

Implementation difficulties in nanoscale CMOS

CP-PLLs with sub-mW power consumption have been realized for use in ultra-low-
power applications [5]. However, the analog intensive nature of the CP-PLL makes

Vamshi Krishna Chillara Master of Science Thesis

1-3 Motivation and thesis objectives 7

its implementation difficult in advanced process nodes. Technology scaling shrinks

the transistor dimensions to enable high integration densities. Supply voltages are
also reduced to limit the electric fields so as to ensure reliable operation. However,
this supply reduction makes it challenging to design traditional analog circuits such
as a cascoded current source used in the charge-pump. Moreover, short channel
effects such as drain-induced barrier lowering (DIBL) lead to reduced drain-source
impedance of the transistor further complicating the design of current sources. Also,
the smallest transistor dimensions are usually not used in the charge-pump design to
minimize noise and to achieve good matching between up and down current sources.
Hence a charge-pump occupies a significant area. Also, since the passives do not
scale well with the technology, the loop-filter used in CP-PLL occupies large area,
increasing the overall system costs. In addition, the reduced gate-oxide thickness in
the nanoscale CMOS technologies results in significant current leakage through the
integration capacitor of the loop-filter. This leakage current increases the total PLL
jitter, thereby degrading the performance.

1-3 Motivation and thesis objectives

The need for low-power low-cost transceivers in large volumes favors the realization
in the most advanced CMOS node available. The problems with analog design in low-
voltage nano-meter scale CMOS processes and the possibility to integrate RF front-
end with baseband processor favors the digitally intensive approach. Furthermore,
a digital intensive approach provides numerous other benefits—better testability,
reconfigurability, lower area, and high degree of integration. Moreover, the digital
approach allows for extensive calibrations; for instance it is possible to track and
correct the variations of the digitally controlled oscillator (DCO) gain over process,
voltage, and temperature (PVT) [10]. This enables to accurately implement two-point
frequency modulation required for a polar transmitter.
Accordingly, a digitally intensive PLL architecture called ADPLL emerged for fre-
quency synthesis in wireless applications. Since its inception in [11], ADPLLs have
garnered the attention of numerous researchers because of their financial benefits and
amenability to scaling. ADPLLs for frequency synthesis in different wireless standards
namely Bluetooth, GSM, and EDGE have been successfully demonstrated [12–14]
with a performance comparable to or even better than that of conventional charge-
pump phase-locked loops (CP-PLLs). DCO and time-to-digital converter (TDC) be-
ing the main bottle-necks justifiably have seen a number of efforts to counter the
limitations arising from their finite resolution. While [15–17] improve the DCO’s
performance, [18–21] address the problems that arise from TDC non-idealities. The
fractional spurs that impede the realization of a wide-band ADPLL are the focus
of [22,23]. Thanks to these improvements, nearly one-third of the new mobile phones
produced use ADPLLs [24].
In contrast, ADPLLs are hardly used in the ultra-low power arena with charge-pump
PLLs dominating the frequency synthesis in these transceivers [25–29]. This is evident
from Figure 1-8 which shows a plot of fractional-N ADPLLs published in the last five
years at ISSCC and VLSI symposium. The published works are plotted with power
consumption in mW as abscissa and the jitter variance in ps2 as the ordinate. The

Master of Science Thesis Vamshi Krishna Chillara

8 Introduction

jitter2 -power FoM4 is also indicated in the graph. It can be noticed that there are no
fractional-N ADPLLs in the sub-mW vicinity, a key requirement for Bluetooth Smart
and ZigBee applications. The main objective of this thesis is to break the sub-mW
barrier for ADPLLs so as to enable their adoption in ultra-low-power applications.
The targeted specifications and scope of this thesis are discussed in the next section.

Figure 1-8: Benchmark of fractional-N ADPLLs.

1-3-1 Target specifications

The specifications of the targeted frequency synthesizer are shown in Table 1-1. In
addition to generating the LO signal with the required frequency, this ADPLL should
also act as a direct frequency modulator in the transmitter path. Accordingly, an
ADPLL with a two-point modulation capability satisfying the tabulated specifications
is targeted.
This all-digital synthesizer designed in 40 nm digital CMOS technology targets Blue-
tooth Smart and ZigBee standards around the 2.4 GHz ISM band. It is desirable if
this very synthesizer can also support 400 MHz medical implant communication ser-
vice (MICS) applications. The MICS standard has two bands of frequencies: 402–405
MHz and 420–450 MHz. Hence, the synthesizer is targeted to cover the frequency
range of 2.4–2.7 GHz (400–450 MHz after division by 6) to accommodate all the
three aforementioned standards. In addition, the synthesizer should be able to han-
dle data rates of up to 1 Mbps for Bluetooth Smart when acting as a frequency


F oM = 10log10 P
[30]
4 2


σjitter ∗ 1mW

Vamshi Krishna Chillara Master of Science Thesis

1-4 Research contribution 9

Table 1-1: Target specifications of the frequency synthesizer.

Parameter Requirement
Frequency range 2.4–2.7 GHz
Frequency accuracy 60 KHz
Switching time 40 µs
Phase noise @ 1 MHz offset -110 dBc/Hz
Integrated RMS phase error 2◦
Modulation data rate 1 Mbps
Reference frequency 32 MHz
Power consumption <1 mW
Technology 40 nm digital CMOS

modulator. Finally, sub-mW power consumption is crucial to accommodate its use

in the autonomous sensors deployed in wireless personal area networks (WPANs) or
wireless body area networks (WBANs).

1-4 Research contribution

It is clear from the earlier discussion that the analog charge-pump phase-locked loops
(CP-PLLs) dominate the ultra-low-power landscape. ADPLLs not only ease the design
challenges in advanced process nodes but also facilitate additional benefits that
accrue from digitization. However, ADPLLs have not been explored for the ultra-low-
power applications, which require sub-mW power consumption. This work presents
the first-ever multi GHz sub-mW fractional-N ADPLL by using a combination of
digital-to-time converter (DTC) and TDC for fractional phase detection.

A TDC in a conventional ADPLL [31] needs to cover one full DCO period sensing the
DCO clock at its full rate, thus consuming several mW. In this work, TDC snapshot-
ting is implemented to reduce the sampling rate to FREF, while the DTC reduces
the detection range to less than one-tenth of the DCO clock period, leading to a
significant power reduction.

In addition, a power efficient DCO buffer with a tunable voltage transfer character-
istic (VTC) is presented. It is DC coupled to the low-swing output of the DCO to
avoid driving bulky resistor-biased decoupling capacitors. This approach reduces the
overall power consumption of the DCO plus buffers.

In this two-student ultra-low-power ADPLL project at imec-nl, my work deals with

the system level analysis of ADPLL, rtl and back-end design of low-speed digital
circuitry, and circuit-level design of DCO and other high frequency blocks. The TDC,
DTC, and the necessary calibration circuitry are designed by a colleague, Bindi Wang.
A silicon prototype that can support Bluetooth Smart and ZigBee standards while
consuming just 860 µW is implemented to demonstrate the feasibility of adapting
ADPLLs for frequency synthesis in ultra-low power transceivers.

Master of Science Thesis Vamshi Krishna Chillara

10 Introduction

1-5 Thesis organization

This thesis is organized as follows. Chapter 2 begins with a background on ADPLLs
while reviewing the current state-of-the-art and highlighting the challenges in adapt-
ing ADPLLs for ultra-low-power applications. Then the DTC assisted snapshot TDC
based ADPLL implemented in this work is presented. Chapter 3 describes the rtl
design of this ADPLL. The circuit design of DCO and other high speed blocks—
divider-by-2, phase incrementer, and DCO buffer—is described in Chapter 4 along
with simulation results. The measurement set-up, pcb layout, and the measurement
results of the implemented silicon prototype are presented in Chapter 5. Chapter 6
is reserved for conclusions and provides suggestions for future work.

Vamshi Krishna Chillara Master of Science Thesis

 Chapter 2

All-digital phase-locked loops

This chapter reviews the common architectures of all-digital phase-locked loops

(ADPLLs) from the literature. The power consumption of each of these architectures
is analyzed to identify the power-hungry blocks. The possible solutions to reduce the
power at architectural level are explored. Finally, the digital-to-time converter (DTC)
assisted snapshot time-to-digital converter (TDC) based ADPLL implemented in this
work is described.

2-1 Existing architectures

Digital processing is cheaper, faster, and consumes less power in advanced CMOS
nodes. However, scaling is less attractive for analog circuits as they are limited by
the electronic noise and low supply voltages make it difficult to meet the accuracy
requirements. ADPLLs evolved to address the challenges of implementing the tradi-
tional charge-pump phase-locked loops (CP-PLLs) in advanced process nodes.
In an ADPLL all the analog blocks of the CP-PLL are replaced either by their dig-
ital equivalents or by mixed signal blocks with digital interfaces at the input and
output. A voltage-controlled oscillator (VCO) of the conventional CP-PLL is replaced
by a digitally controlled oscillator (DCO), which deliberately avoids any analog tun-
ing. The DCO produces a frequency proportional to its input digital word plus an
offset. The charge-pump/phase-frequency detector combination got replaced by a
TDC, which digitizes the time difference (phase) between its input signals. Since the
phase error is digitized, a bulky passive loop filter of the CP-PLL can be replaced
by a compact digital one, resulting in considerable cost savings. A review of current
literature reveals various implementations to realize an ADPLL, mostly differing in
the way phase to digital conversion is achieved. They can be broadly classified into
the following two types: divider-less and divider-based ADPLLs.

2-1-1 Divider-less ADPLL

This is the architecture that triggered the research in digital-intensive frequency
synthesis for wireless transceivers and is first presented in [31]. Figure 2-1 shows

Master of Science Thesis 11 Vamshi Krishna Chillara

12 All-digital phase-locked loops

a simplified block-diagram of the divider-less ADPLL [32]. The output frequency

termed as the variable frequency, Fv , is set by the frequency command word (FCW).

Fv
F CW = (2-1)
F REF
Equivalently, FCW denotes the number of clock cycles of variable clock (CKV) in
one reference clock. Hence, accumulating the FCW at reference rate provides the
reference phase (ΦR ) that is normalized to CKV clock period. The variable phase,
ΦV , is obtained by counting the number of output clock cycles. Phase incrementer
gives the integer part of the variable phase, ΦV _int . A TDC is used to detect the
phase with a resolution finer than one integer cycle.
A typical TDC consists of a chain of delay elements that delay the CKV signal. The
delayed versions of the CKV are sampled by fref to obtain the time delay between
the edges in terms of number of delay elements [18]. Hence the resolution of the
fractional phase detection is limited by the intrinsic delay of the unit cells in the
TDC. The fractional phase is obtained by normalizing the output of the TDC to the
CKV period.

The variable phase and reference phase, which are available as digital words can
now be subtracted by digital logic to generate the phase error. This phase error
is passed through a digital loop filter to obtain the oscillator tuning word (OTW).
OTW controls the DCO frequency in a negative feedback configuration such that the
phases of the CKV and reference clock fref are either equal or have a constant
difference in the steady state, depending on the type of loop. The frequency of the
variable clock (CKV) is hence equal to FCW times the reference frequency.

DLF DCO
FCW ΦR ΦE OTW CKV
Σ
CKR
ΦV
ΦV_int Phase
Incrementer

ΦV_frac
TDC FREF

Figure 2-1: Architecture of divider-less ADPLL.

Since the clock signals CKV and fref are asynchronous, re-timing is needed to
avoid metastability. The re-timed reference clock CKR is generated by sampling the
reference clock fref with the variable clock (CKV). Since this re-sampling itself may
introduce metastability, sampling is done both at the rising edge and the falling edge
of CKV, and the one farthest from the metastability is picked [32]. The re-timed
reference clock CKR is then used as the clock for the low frequency digital logic:
phase detector, digital loop filter, and gain normalization blocks.

Vamshi Krishna Chillara Master of Science Thesis

2-1 Existing architectures 13

2-1-2 Divider-based ADPLL

The divider-based ADPLL architecture, shown in Figure 2-2, is an exact block-by-

block replacement of the analog blocks in a traditional CP-PLL with their digital
equivalents. In this architecture, the variable clock (CKV) is passed through a frac-
tional divider before it is fed to the TDC. The required output frequency is set by
the divider ratio. To realize a fractional division ratio, a Σ∆ modulator dithers the
divider ratio between two integer values. The TDC compares the time difference be-
tween the significant (rising or falling) edges of the stable reference clock fref and
the divided down output clock Fdiv to generate the phase error directly as a digi-
tal word. After passing through a digital filter, the phase error controls the DCO
frequency to align it to the reference clock.

DLF DCO
FREF OTW
TDC

Multi-modulus
divider

FCW
ΣΔ

Figure 2-2: Architecture of divider-based ADPLL.

2-1-3 Comparison of divider-less and divider-based architectures

The phase incrementer and the divider play a similar role and consume comparable
power and area, leading to a similar performance in either architecture. However,
multi-modulus divider is accompanied with fractional spurs requiring additional
circuitry to mitigate them [33]. Moreover, divider-based architectures do not operate
in phase-domain and hence should be realized as type-II1 systems to ensure the
divided down CKV and fref edges are closely aligned. On the other hand, the
divider-less architectures [31,34] operate in the phase-domain but both the TDC and
phase incrementer operate at the high output frequency (typically in the GHz range)
consuming significant power. The reduced operating frequency of TDC in a divider-
based architecture is offset by its increased range requirement—one reference clock
period—as opposed to one CKV duration in a divider-less architecture. Thus, in
either architecture, TDC consumes a significant power. Section 2-4 explores different
approaches in the literature to tackle this issue.
1
type indicates the number of poles at the origin

Master of Science Thesis Vamshi Krishna Chillara

14 All-digital phase-locked loops

2-2 Requirements on TDC and DCO

Like any mixed-signal system, ADPLL also suffers from the effects of the inevitable
quantization noise resulting from analog-to-digital and digital-to-analog conversion.
The TDC which converts the analog phase of the CKV to a digital word limits the in-
band phase-locked loop (PLL) noise, while the DCO that converts the digital control
word to an analog signal with desired frequency affects the out-of-band noise. For-
tunately, both the TDC resolution—usually limited by the inverter delay—and the
DCO frequency step improve with technology scaling and hence the performance of
the ADPLL improves with each advanced node. The requirements on the resolution
of TDC and DCO for targeted applications are calculated here.

2-2-1 Impact of TDC on phase noise

The finite resolution of TDC results in quantization noise whose power is given by
Eq. (2-2) [35], where ∆T DC is the quantization step of the time-to-digital converter
(TDC).
σt2 = ∆2T DC /12 (2-2)
This noise is distributed over the frequency band (0, f2s ), where fs is the sampling
frequency which is the reference frequency, fR , of the ADPLL. By normalizing it to
the unit interval and multiplying by 2π radians phase noise is obtained [32].
σt
σΦ = 2π (2-3)
Tv
Assuming an ideal TDC, the noise distribution can be considered white giving rise
to a single-sided noise spectral density of
σΦ2
L= (2-4)
fR
From Eq. (2-3) and Eq. (2-4), the single sided phase noise of the ADPLL due to
quantization of TDC is given by
(2π)2 ∆T DC 1
 2
L= (2-5)
12 Tv fR
This noise from the TDC has a low pass transfer function and hence dominates
the in-band PLL noise. In addition to the quantization noise, the finite TDC step
and mismatch between the delay elements also result in spurs at the frequency,
F CWf rac ∗ F REF , further degrading the phase noise of the ADPLL [22].
In the TSMC 40 nm process in which the targeted synthesizer is implemented, an
inverter delay of 20 ps is achievable without consuming too much power. For this
value of ∆T DC = 20 ps, the in-band PLL noise floor given by Eq. (2-5) is equal
to -95 dBc/Hz with 2.7 GHz operating frequency. This value is sufficient for the
targeted applications and hence a delay-line based TDC suffices. Note that, it is
possible to achieve sub-inverter delay resolution, although at the expense of increased
power consumption. In [19] time amplification is used to achieve sub-ps resolution
but consumes a staggering 60 mW power. Vernier delay-line based architecture [36]
uses the difference between individual delay elements to achieve fine resolution but
requires a large number of cells and hence consumes a lot of power.

Vamshi Krishna Chillara Master of Science Thesis

2-2 Requirements on TDC and DCO 15

2-2-2 Impact of DCO on phase noise

DCO is the core of the ADPLL and produces an output frequency proportional to its
input digital word in addition to an offset. The frequency resolution of the DCO also
adds additional quantization noise which can be modeled with white noise spectral
characteristics provided the input tuning word spans multiple quantization levels.
The variance of the quantization error in output frequency is then given by

σf2 = ∆fres
2
/12 (2-6)

Since this phase noise power is spread uniformly from DC to Nyquist frequency, the
single sided spectral density is given by

1 σf2
S∆f = (2-7)
2 fR

This can be converted to phase variation by multiplying the DCO’s frequency to

phase conversion transfer function, 2π
s
. The single-sided phase noise power spectral
density at the output is then given by

1 ∆fres 1
 2
L(∆f ) = (2-8)
12 ∆f fR

Since the DCO input tuning word is held constant between two different values, the
white noise assumption is not fully justified. Hence, the above equation is multiplied
by sinc function to account for the zero-order hold operation on the input tuning
word of DCO [32].
1 ∆fres 2 1 ∆f 2
   
L(∆f ) = sinc (2-9)
12 ∆f fR fR

The quantization noise of the DCO has a 20 dB/decade attenuation, similar to that
of the up-converted thermal noise from the oscillator. As long as this quantization
noise is kept sufficiently low compared to the inherent phase noise of the oscillator
(resulting from thermal and flicker noise of active part or the passive LC tank), the
overall phase noise is not significantly affected. The noise from the DCO is high-
pass filtered by the loop and hence has a band-pass characteristic, degrading the
out-of-band phase noise of the synthesizer.
A spot noise of -110 dBc/Hz at 1 MHz offset from the carrier frequency is targeted
indicating that the phase noise from the DCO quantization should be lower than
-120 dBc/Hz. A 50 kHz accuracy is required in channel selection, which corresponds
to a DCO quantization noise of -112 dBc/Hz from Eq. (2-9), which is comparable
to the targeted phase noise. Hence a 5-bit Σ∆ modulator is used to dither the DCO
control word to minimize the quantization noise [17]. In this way, the quantization
step is reduced to ∆f res /25 and so is the quantization noise. However, the Σ∆-
modulator itself introduces spurs somewhat limiting its improvement. Either a high
dithering rate or higher order dithering can be employed to counter the issue of
spurs.

Master of Science Thesis Vamshi Krishna Chillara

16 All-digital phase-locked loops

2-3 Direct frequency modulation

Direct frequency modulation of the frequency synthesizer simplifies the transmitter
architecture, saving power and area. In traditional fractional-N synthesizers, the
divider ratio is modulated by the TX data, achieving the desired frequency deviation.
However, the maximum rate of modulation is limited by the loop bandwidth as the
modulation signal is filtered by the low-pass characteristic of the PLL. A narrow
loop bandwidth is usually chosen to minimize the high frequency quantization noise
injected by the Σ∆ divider as well as to filter off the noise from phase detector or the
reference clock. Thus it is difficult to achieve high data rates by directly modulating
the divider ratio. To overcome this issue, techniques such as pre-emphasis [37] and
two-point modulation [38, 39] are used.
In the approach using pre-emphasis, the frequency control is multiplied by inverse
of the PLL transfer function to compensate the low-pass filtering by the loop. How-
ever, it requires accurate knowledge of the loop transfer function to ensure the pre-
emphasis does not distort the transmission data. In two-point modulation method,
the modulation data is added directly to the oscillator control signal in addition to
the divider. If the oscillator gain is accurately known, this method removes the loop
dynamics from the transmitted data path. The digital implementation of the PLL
eases the implementation challenges of both these approaches. However, since the
pre-emphasis method needs extra hardware it is not preferred.

2-3-1 Two-point frequency modulation

Figure 2-3 shows the implementation of the two-point modulation in the divider-less
ADPLL architecture. The modulation data is added to the FCW in the low frequency

TX data gain
Low frequency High frequency

DLF DCO
FCW ΦR ΦE OTW CKV
Σ
CKR
ΦV
ΦV_int Phase
Incrementer

ΦV_frac
TDC FREF

Figure 2-3: Two-point frequency modulation in divider-less ADPLL architecture.

path and directly to the DCO control word in the high frequency path. The scaling
factor in the high-frequency path ensures that the LSB of the modulation data
corresponds to same frequency step in both high and low frequency paths. The
step in the low-frequency path is set accurately by the reference frequency and is

Vamshi Krishna Chillara Master of Science Thesis

2-4 Challenges for ultra-low-power applications 17

independent of the variations in process, voltage, and temperatures (PVTs). On the

other hand, the frequency step of the high frequency path depends on the resolution
of DCO, KDCO , and hence is different to that of the low-frequency path.
When the modulation data increases, the frequency of the DCO and hence the vari-
able phase, ΦV , becomes higher. On the low-frequency path, the FCW is also in-
creased which increases the reference phase, ΦR , keeping the phase error unchanged.
However, the calculation of the gain factor on the high frequency path of the TX
data requires the knowledge of the DCO gain, KDCO . It can be calculated just-in-time
as discussed in [10]. Since the OTW is available as a digital signal, the change in OTW
for a known deviation in frequency can be observed to estimate the value of KDCO
over PVT variations. Thus ADPLL can perform direct frequency modulation with
a data-rate independent of the loop band-width while consuming little additional
hardware.

2-4 Challenges for ultra-low-power applications

DCO and TDC consume most of the power in an ADPLL. The power consumption
of DCO depends on its phase noise requirements, and hence can be scaled down in
short-range wireless applications. The design of DCO is discussed in Chapter 4. On
the other hand, the power consumption of TDC is large, mainly owing to its high
frequency operation or large range requirement depending on the architecture.
The similarity of TDC to that of an analog-to-digital converter (ADC) inspired re-
search in the lines of Σ∆ data-conversion. However, a coarser TDC resolution re-
quirement does not necessarily translate to lower power beyond that available from
minimally sized inverter delays. As a result, Σ∆ frequency discriminator based ar-
chitectures [40, 41] do not help unless a bang-bang phase detector is adopted or
sub-inverter delay resolutions are required. Also, this approach does not take ad-
vantage of the high resolution inverter delays available in the advanced CMOS nodes
and expends considerable power in digital processing. A fine resolution TDC allows
wide loop bandwidth, thereby filtering more noise from DCO. Since the power con-
sumption of DCO is proportional to its phase noise, total ADPLL power can thus be
reduced for a given jitter requirement.
In this work, the techniques to reduce the required phase detection range and oper-
ating frequency of TDC are explored instead and are discussed here.

2-4-1 Reducing the TDC detection range

TDC needs to cover a range equal to the CKV period with a fine resolution, thereby
consuming considerable power. A bang-bang phase detector is adopted in [42] to
replace the TDC, thereby alleviating the issue of large range requirement. A bang-
bang phase detector is essentially a D flip flop determining whether the reference
signal leads or lags the divided down signal. The spurs that are inherent to the bang-
bang phase-locked loops (BBPLLs) are minimized by operating it in the random-noise
regime. To achieve this, a true fractional divider using a 10-bit DTC is proposed.

Master of Science Thesis Vamshi Krishna Chillara

18 All-digital phase-locked loops

Compared to a TDC, DTC consumes less power as it does not need power-hungry
sense-amplifier based flip-flops [18] required by a TDC. That architecture achieves
an impressive figure-of-merit (FoM)2 of -238 dB while consuming 4.5 mW. However,
the integrated jitter cannot be traded to achieve the sub-mW power levels required
for our targeted applications as it would mean moving away from the random-noise
regime, thereby exacerbating the issue of spurious tones resulting from limit cycles.
Moreover, the loop bandwidth of that circuit depends on the noise at the input of
the bang-bang phase detector and hence additional circuitry is required for loop
bandwidth regulation and frequency acquisition.
A divider-less ADPLL with DTC and a bang-bang phase detector is presented in
[43]. In [44], the authors propose to use the DTC in order to reduce the required
TDC range rather than replacing it by a bang-bang phase detector. In both these
architectures, the accumulated value of fractional FCW is used to delay the reference
signal fref such that the delayed reference signal, frefdly is almost aligned to the
CKV once the loop is locked. This idea of phase prediction is depicted in Figure 2-4
for the case when FCW = 2.25. As can be seen, the required delay to align the FREF
edge to the next CKV edge can be obtained by subtracting the accumulated value of
fractional FCW from 1. The delayed reference signal and the CKV can be then fed to
the narrow-range TDC, the output of which directly gives the fractional phase error.
This approach helps in reducing the TDC range by as much as ten times.

FCW = 2.25

0 1 2 3 4 5 6 7 8 9 10 11 12

CKV edges

0 2.25 4.5 6.75 9 11.25

FREF edges

Delay needed
0 0.75 0.5 0.25 0 0.75

Figure 2-4: Principle of phase-prediction to reduce fractional-phase detection range.

In yet another approach [45], the quadrature phases of the DCO are used to reduce
the operating range of TDC. Again, the accumulated value of FCWfrac is used to
select one of the four CKV phases that is closest to the FREF signal. In this way,
the required detection range is reduced to one-fourth of CKV period. However, the
TDC is clocked at CKV frequency (usually in the order of GHz), thereby increasing
the power consumption.

2-4-2 Lowering the operating frequency of TDC

The TDC compares the phase difference between the CKV signal and fref and
hence operates at high frequency, consuming significant power. However, the phase


F oM = 10log10 P
[30]
2 2


σjitter ∗ 1mW

Vamshi Krishna Chillara Master of Science Thesis

2-5 DTC-assisted snapshot TDC based ADPLL 19

difference is calculated only close to the rising edge of fref i.e., the TDC needs to
operate only at the reference rate, typically tens of MHz. This is the basis of the
time-windowed TDC based architecture presented in [46] where the TDC is gated
to reduce its operating frequency and hence power consumption. However, this ap-
proach requires a TDC with a detection range equal to the CKV period and hence
cannot be combined with one of the methods that reduce the detection range. In [44],
DTC based phase-prediction is used to simultaneously reduce the operating frequency
and detection range. Since the phase-prediction maintains a fixed phase difference
between the frefdly and CKV signals, the first CKV pulse after the rising edge of
frefdly is picked and is fed to the TDC for phase detection. In this way, total power
consumption can be reduced by FCW times—typically on the order of 30–40 from
the reduced operating frequency and nearly ten times from the reduced detection
range.

2-5 DTC-assisted snapshot TDC based ADPLL

Figure 2-5 depicts the top-level block diagram of the ADPLL with two-point frequency
modulation capability designed in this work. The blocks with gray background—
TDC, DTC, snapshotting, KDTC calibration, and power amplifier (PA)—are designed
by colleagues at imec-nl and the description of their implementation is not a part
of this thesis. The blocks with blue background are the analog/high-speed blocks
that warrant custom design whose circuit level implementation and layout are de-
scribed in Chapter 4. The remaining blocks comprise the low-speed digital logic
responsible for processing the phase information to generate the appropriate control
signals for the DCO. The functional description of the implemented low-speed digital
blocks is provided in this section. The detailed rtl-level description is deferred until
Chapter 3.
A divider-less ADPLL architecture with a difference mode phase detector [32] is used.
To meet stringent sub-mW PLL power constraints, three low-power techniques are
employed:

1. The biggest power-saving is obtained by using a DTC assisted snapshot TDC

for fractional phase detection. DTC helps in reducing the detection range of
DTC by using the principle of phase-prediction described in Section 2-4-1.
Snapshotting reduces the operating frequency to reference rate.

2. Secondly, a power efficient DCO buffer with a tunable voltage transfer char-
acteristic (VTC) is used to isolate the DCO from load variations in PA as well
as to boost the low-swing DCO output to rail-to-rail voltage levels. Unlike the
conventional approach, the buffer is DC-coupled to the DCO to avoid driving
bulky resistor-biased decoupling capacitors. The implementation details of the
DC-coupled DCO buffer are presented in Section 4-2-2.

3. Finally, a frequency divider (/2) reduces the operation of phase detection cir-
cuitry to half the DCO rate, ckvd2. This saves power at the expense of dou-
bling the required detection range.

Master of Science Thesis Vamshi Krishna Chillara

20 All-digital phase-locked loops

2-5-1 Phase prediction

By virtue of phase-prediction discussed in Section 2-4-1, DTC helps in reducing
the required detection range of TDC. Thus, the DTC/TDC combination acts as a
coarse-fine structure with the coarse DTC assisting the fine TDC. A 64-stage DTC is
implemented so as to cover the maximum value of ckvd2 period with sufficient
margin over PVT variations. The digitally controlled delay line of the DTC is similar
to the one in [47]. The control word of the DTC is obtained from the accumulated
value of fcwfrac , phrF , according to Eq. (2-10). The DTC gain, KDTC , is the ratio
of time-step of the DTC to the time period of ckvd2 .
1 − P HRF
DT Cctrl = (2-10)
KDT C

For correct phase prediction, the value of KDTC should be tracked accurately over
PVT variations. Even with incorrect phase prediction, the ADPLL can lock but will
have an increased phase noise as it tries to track the incorrectly predicted ref-
erence phase. The estimation is accomplished by the KDTC calibration block of
Figure 2-5 which monitors the sign of the phase error to correct the estimated value
of KDTC [48].
The basic idea of estimation is as follows: When the DTC gain is underestimated, the
predicted variable phase is a saw tooth waveform with a slope larger than the ideal
(i.e., reference) phase and a frequency fPE equal to fR ∗ min(F CWf rac , 1 − F CWf rac )
as shown in Figure 2-6. Similarly, when overestimated, the predicted phase has a
slope smaller than the ideal one. Consequently, the polarity of ((PHRF -0.5)∗PHE)
can be used to predict if the DTC gain is under/overestimated and thus can be
corrected using least mean square algorithm.

Residue correction

Even when the DTC gain is correctly estimated, the accuracy of phase prediction
is limited by the quantization step of the DTC. From Eq. (2-10), it can be seen
that the DTCctrl can be a fractional number. However, only integer part is used to
control the DTC delay and the residue that is left behind results in an error in phase
prediction. However, since this error is known beforehand, it can be corrected by
subtracting it from the output of the TDC. Thus this residue correction ensures that
the quantization step of DTC has no impact on the overall phase noise. The exact
implementation is described in Section 3-1-3.

Vamshi Krishna Chillara Master of Science Thesis

 TX Modulation 1/KDCO_HF
FCW data 2.1-2.7 GHz

FMLF FMHF
PA

DCO

Master of Science Thesis

FCWInt
dPHR Digital loop DCO
Σ filter buffer
CKR
CKV
CKR
CKR 1/KDCO_LF
FCWfrac
/2
2-5 DTC-assisted snapshot TDC based ADPLL

Σ Phase
sampler
CKR PHRF
PHEF PHV Phase
1-z-1 1-z-1 Incrementer
1/KDTC
CKVD2
1/KTDC
KDTC DTCctrl CKR CKR
calibration TDCout

Fref FREFdly CKVD2S

64 stage DTC 16 stage TDC
Snapshot &
CKR gen

Vamshi Krishna Chillara

21

Figure 2-5: Top-level block diagram of the ADPLL.

22 All-digital phase-locked loops

CKV phase ideal-prediction

CKV phase actual-prediction
6π

4π
PHRF<0.5 PHRF>0.5
PE>0 PE<0
2π
(PHRF−0.5)*PE<0

TPE 2TPE 3TPE

KDTC underestimation

CKV phase ideal-prediction

CKV phase actual-prediction
6π

4π

PHRF<0.5 PHRF>0.5
PE<0 PE>0
2π
(PHRF−0.5)*PE>0

TPE 2TPE 3TPE

KDTC overestimation

Figure 2-6: Idea of DTC gain calibration [48].

Vamshi Krishna Chillara Master of Science Thesis

2-5 DTC-assisted snapshot TDC based ADPLL 23

2-5-2 Snapshotting and CKR generation

TDC snapshotting is implemented to reduce the operating frequency of TDC from
ckvd2 to fref. The delayed reference, frefdly , which is aligned to ckvd2 by
means of phase prediction is used to trigger the snapshot circuit. As shown in Fig-
ure 2-7, frefdly deasserts the ckvenb signal which takes the snapshot of the first
ckvd2 edge, ckvd2S . Thus, at every rising edge of the delayed reference clock

FREFdly

CKVENB

CKVD2

CKVD2S

CKR

Figure 2-7: tdc snapshotting and ckr generation.

frefdly , the snapshot of the ckvd2 rising edge is taken. Hence, the frequency of
the snapshot signal is equal to the reference rate.
The snapshot signal ckvd2S and the delayed reference frefdly are fed to the TDC.
Since these two signals are aligned by the DTC, a narrow range TDC suffices. Also,
the two inputs to the TDC—frefdly and ckvd2S —toggle at reference rate, reducing
the operating frequency and hence power consumption of the TDC. When the ADPLL
is locked, the phase prediction is accurate and hence the two inputs to the TDC have
a constant phase difference. Any deviation from this phase difference indicates an
incorrect output frequency and the TDC output directly gives the fractional phase
error PHEF . Note that in the conventional architecture [31], the output of the TDC
gives the fractional value of variable phase which is then compared to the fractional
reference phase to obtain the phase error. In this architecture, the fractional reference
phase is used to delay the reference clock and the TDC output directly gives the
phase error. The output of the TDC (PHEF ) is assigned zero when the time (phase)
difference between its inputs is equal to half the TDC range. A smaller time difference
gives a negative phase error and a larger time difference results in a positive phase
error.
The snapshot signal ckvd2S has some constant offset from the original ckvd2 sig-
nal, which can be greater than the narrow range of the TDC used. To compensate
this propagation delay, a constant delay offset is introduced in the frefdly path
before it is fed to the TDC. A set of inverters implement this offset delay. The value
of the required offset delay is estimated from post-layout simulations and ensures
the operation of TDC at the midpoint of its range in steady state. Before the ADPLL
locks, the phase prediction is not accurate. Consequently, the time difference be-
tween frefdly and ckvd2S is greater than the narrow range of the TDC. Thus, the
TDC acts as a bang-bang phase detector, and brings the output frequency to the
neighborhood of the target frequency. Eventually, the phase difference between the

Master of Science Thesis Vamshi Krishna Chillara

24 All-digital phase-locked loops

TDC inputs falls within its linear range. To avoid long settling-time due to the initial
bang-bang operation of the TDC, a 16-stage TDC covering one-fifth of ckvd2 period
is implemented. Once the ADPLL is locked, the phase difference of the TDC inputs is
small as the DTC aligns the FREFdly and ckvd2S accurately, and hence falls within
its range. The TDC is realized by pseudo-differential inverter based delay lines and
sense-amplifier based flip-flops with identical rising and falling edge metastability
windows [18].

Reference clock retiming

As discussed in Section 2-1-1, the reference clock should be retimed by the ckvd2 to
avoid metastability arising from multiple clock domains. In the conventional archi-
tecture [32], the fref signal is sampled by both the rising and falling edges of the
ckvd2 and the one farthest from metastability is selected. This increases the com-
plexity and hence power consumption. In this work, the ckr generation circuitry
is simplified to just a flip-flop, since frefdly and ckvd2s are synchronized owing
to phase prediction. Thus, frefdly is sampled directly by ckvd2s to generate ckr
two ckvd2 delays after its rising edge. This provides enough processing time for
TDC and phase incrementer.

2-5-3 Low-speed digital logic

The low-speed digital logic is qualitatively discussed here. Chapter 3 provides a

detailed description of each of the building blocks of the low-speed logic. The low-
speed logic comprises a finite state machine, interface to tx data, phase detector, and
a loop filter for each of the DCO’s three banks: PVT, acquisition, and tracking. The
DCO is made of three banks to cover a wide frequency range with a fine resolution.
The required frequency is achieved successively with PVT bank bringing the output
frequency to the neighborhood of the required channel, followed by acquisition bank
which acquires the required channel with a medium resolution (~2 MHz in this
work). Finally, the tracking bank locks to the required frequency channel with fine
resolution. The state machine (not shown in Figure 2-5) controls the sequence in
which the banks are activated and the duration for which they remain active.
The FCW is used to generate the required frequency according to Eq. (2-11).

Fout = F CW ∗ F REF (2-11)

The integer part of the FCW poses an upper-limit on the frequency that the ADPLL
can generate for a given reference clock. In this work, a 32 MHz reference is used
and a maximum frequency of 2.7 GHz is required. Since the loop operates at half
the DCO frequency ckvd2, Fout = 2.7 2GHz . Thus the required number of integer bits
of FCW is obtained as 2.7e9/2
32e6
= 42.2, implying that 6 integer bits suffice. However, to
enable the use of a lower reference frequency if required, 7 integer bits are allotted
to the integer part of FCW. The number of fractional bits of FCW determine the
average resolution with which the loop can lock to the required frequency. For a
1 kHz resolution, 16 fractional bits are used (2∗32e6/216 ).

Vamshi Krishna Chillara Master of Science Thesis

2-5 DTC-assisted snapshot TDC based ADPLL 25

The TX modulation data is added to the FCW in the low frequency path (FMLF )
and to the DCO control word in the high frequency path (FMHF ). This two-point
modulation allows the modulation bandwidth to exceed the PLL loop bandwidth.
A scaling factor is added in the high frequency path to ensure the modulation data
corresponds to same frequency deviation in both high and low frequency paths. It
is required to compensate for the variations in the DCO gain, which is susceptible to
PVT variations.

A difference-mode architecture is used for the phase detector. It is functionally

similar to the one described in Section 2-1-1 except for the separation of phase error
accumulation from the phase detection. In this structure, the variable frequency
is obtained first from the variable phase, phv, to compute the frequency error.
The phase error is then obtained by accumulating the frequency error. It eases
the implementation of zero-phase restart which is required at the mode switch-over
from PVT to acquisition bank and from acquisition to tracking bank (see Section 3-
1-4). Moreover, unwanted perturbations on the frequency error can be neglected by
freezing the phase error.
The DTC control is generated from the accumulated fractional FCW, PHRF . The
required delay is normalized to the loop-operation frequency ckvd2 using KDTC
obtained from the DTC gain calibration block. The digital loop-filter of Figure 2-5
is actually a set of three loop-filters, one for each bank. The loop filter for PVT and
acquisition banks is simply a proportional path leading to a type-I PLL operation
in these modes. Type-I operation results in a faster frequency acquisition but poor
phase-noise. Since the phase noise is not important in this interval, type-I operation
is preferred to improve settling time. The loop-filter for the tracking bank has pro-
portional and an integral path, leading to a type-II operation in this mode. An iir
filter is also implemented to provide an additional out-of-band noise filtering. All
three banks have gain normalization blocks to remove the impact of the DCO gain
on the loop parameters.

Master of Science Thesis Vamshi Krishna Chillara

26 All-digital phase-locked loops

Vamshi Krishna Chillara Master of Science Thesis

 Chapter 3

RTL design

This chapter describes the RTL design of the low-speed digital logic in Verilog. The
synthesizable low-speed logic takes the variable phase, frequency command word
(FCW) and other parameters for loop filter as the input and generates the control
word for digital-to-time converter (DTC) and digitally controlled oscillator (DCO).

3-1 RTL design of low-speed digital logic

The digital logic of the Figure 2-5 required for processing the variable phase infor-
mation to generate appropriate control signals is described at the RTL level here.
Verilog HDL and VHDL are the two primary hardware languages predominantly
used for digital design. Verilog HDL is chosen for this project as it is easy to syn-
thesize the logic using the existing design flow at imec-nl. A top level block diagram
of the low-speed logic is shown in Figure 3-1.
The low-speed logic comprises a finite state machine, interface to tx data, phase
detector, and a loop filter for each of the DCO’s three banks: PVT, acquisition, and
tracking. The state machine generates appropriate control signals to the rest of the
blocks. It determines the duration and order in which each of the three banks of
DCO are activated after the frequency search is triggered. Also, it ensures that only
one of three banks of DCO is active at any given instant.
The block "tx interface" receives the tx data and the FCW from the digital base-
band and generates the input control to the low-frequency and high frequency paths
to facilitate two-point frequency modulation (see Figure 2-5). The phase detector
generates the integer phase error by comparing the integer part of variable phase
from the phase incrementer with the required reference phase. In addition, the phase
detector also computes the value of DTC control from the fractional part of FCW
as discussed in Section 2-5-1 and reads the fractional phase error from the time-
to-digital converter (TDC). A separate loop filter for each of the three banks then
processes the phase error to generate the appropriate control words for the DCO. The
implementation details of each of these blocks is described in the following section.

Master of Science Thesis 27 Vamshi Krishna Chillara

28 RTL design

ZPRA
ZPRP

PHE[22:16]
TX data[9:0]
inv_Kdco_P [2:0]
dly_dco path[2:0]
mem_dcoP [4:0]
SPI_FCW[22:0]
TX alphaP V T [1:0] OTWP V T [4:0]
Kdco _modn[5:0] Loop filterP V T
Interface bank_en[2]
CKR
CKR
modn._on
bank_sel[2]

bank_sel[1]

FCW[22:0] PHE[22:15]

DTCctrl _extn DTCctrl [5:0]

TDC out[15:0] DTCctrl _SPI[5:0] mem_dcoA [5:0] OTWAB [5:0]
Phase
inv_Ktdc [15:0] inv_Kdtc [8:0] inv_Kdco_A [2:0] Loop filterAB
Detector
residue_dly[1:0] PHVI [6:0] alphaAB [1:0]
TDC
residue_corr_on
read-out CKR bank_en[1]

CKR PHEF [16:0] CKR

DTCresidue [1:0]
srst

PHE[22:0]

OTW_data[10:0]

mem_dcoT [8:0] OTWT B_I [8:0]

PVTmode [2:0]
alphaT B [2:0]
ABmode [2:0]
bank_sel[2:0] rho[3:0]
CH_SW FSM
bank_sel[0] OTWT B_F [4:0]
CKR Loop filterT B
inv_Kdco_T [7:0]

lambda[2:0]

IIR_EN

CKR
bank_en[0]

Figure 3-1: Top-level block diagram of low-speed logic.

3-1-1 Finite state machine

Figure 3-2 shows the flow chart that represents the functional behavior of the state
machine.
The input channel switch, ch_sw, triggers the frequency search of the ADPLL. It is
negative edge sensitive and starts the state machine in state: "000". The state ma-
chine waits for two ckr cycles in this state and moves to state: "001" while asserting
the synchronous reset signal "srst". The state machine then moves to pvt mode af-
ter two ckr cycles. In the PVT mode, represented by state: "010" in the Figure 3-2,
the srst signal is deasserted and the bank_en signal is set to "100". The msb of the
bank_en signal enables the PVT bank while the bit 1 enables acquisition bank and
the lsb enables the tracking bank. In the PVT mode, PVT bank is enabled while the
other two banks are disabled. The input, pvt_mode determines the duration of the
ADPLL in PVT mode according to Eq. (3-1).

1
T imeP V T = (PVT_mode + 1) ∗ ∗ 30 (3-1)
F REF

Vamshi Krishna Chillara Master of Science Thesis

3-1 RTL design of low-speed digital logic 29

"111" "001"
Wait for 2
CKR cycles
sw
ch_ As
"101"

if "1"
if ser
t tp
s rs vt
ert
if ss
"1 A
"110" "
if "1" "010"
"000" if ch_sw
start Wait for 2
Wait for
pvt_mode
CKR cycles
CKR cycles

if c ab
if ch_sw h_ rt
sw s se
A

Assert tb "011"
"100" Wait for
stay here ab_mode
CKR cycles

Figure 3-2: FSM of the implemented ADPLL.

In this work, a 32 MHz reference is used which corresponds to a period of around

30 ns. Thus with a 3 bit control, the duration of PVT mode can vary from 1 µs
to 8 µs with a step of 1 µs and is typically set to the smallest value. After this
time, the state changes to acquisition mode, state: "011". In this mode, only the
acquisition bank is activated by setting the bank_en signal to "010". The input to
the PVT bank is held at the previous state and the input to the acquisition bank now
changes depending on the phase error. The duration of this state is controlled in a
way similar to the PVT mode, with a three bit word, ab_mode. After the specified
duration the state changes to tracking mode denoted as state: "100".
In the tracking mode, tracking bank is activated by setting the bank_en signal to
"001" while disabling the other two banks. The inputs to the other two banks are
frozen at the preceding value. The ADPLL remains in this state until the ch_sw
signal is activated to acquire a new channel.
Activating the ch_sw signal, switches the ADPLL to initial state irrespective of the
current state. Also, ADPLL transitions to the initial state from the unused states,
"101"–"111" to avoid undefined states.

3-1-2 TX interface

Figure 3-3 shows the implementation details of the "TX interface" block of Figure 3-
1. The inputs to this block are the 10-bit modulation data, "tx data", and the
channel FCW that selects the channel frequency. Using these inputs, it generates
appropriate inputs to the high frequency and low frequency paths.
On the low-frequency path, the tx data is added to the FCW directly to modulate Elec
the frequency. On the high frequency path, a DCO with a 60 kHz resolution and a

Master of Science Thesis Vamshi Krishna Chillara

30 RTL design

D Q D Q D Q D Q D Q D Q D Q D Q
10’b0 0
TX data[9:0] Q Q Q Q Q Q Q Q
1 nrst nrst nrst nrst nrst nrst nrst nrst

modn_on
nrst
CKR

1
<< dly_dco-path[2:0]
Mux
SPI_FCW[22:0]
inv_Kdco _modn[5:0]

FCW[22:0]
low-frequency path

OTW_data[10:0]
high frequency path

Figure 3-3: Implementation of tx interface block.

5-bit Σ∆ modulator that dithers the DCO input are used. This corresponds to an
effective resolution of roughly 2 kHz (60/25 ). Consequently, 10-bit modulation data
can support a frequency deviation of ±1 MHz with a 2 kHz resolution. Since 1 lsb
of FCW corresponds to 1 kHz, the modulation data is shifted left by 1 bit before it
is added to the FCW on the low frequency path. The figure below illustrates how
the modulation data controls the low and high frequency paths.

32 15.36 7.68 3.84 1.92 0.96 480 240 120 60 30 15 7.5 3.75 1.9 0.98 dco
MHz MHz MHz MHz MHz MHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz 9I 5F
32 16 8 4 2 1 500 250 125 62.5 31.25 15.6 7.8 3.9 1.95 0.98 pll 16F
MHz MHz MHz MHz MHz MHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz

tx data [9:0]

The frequency corresponding to the modulation data on the low-frequency path is

fixed by the reference frequency and is independent of PVT variations. However, the
same is not true of the high frequency path as the DCO resolution is sensitive to
PVT variations. Hence the modulation data is scaled by inv_Kdco _modn before it is
added to the DCO control word. The scaling factor is calculated from the DCO gain
according to Eq. (3-2). A 6-bit word with 5 fractional bits is used to cover a range
of 0.75–2.7 with 3% resolution. Since value of Kdco typically reduces compared to
the simulation results, more margin is kept on the higher side by adding an offset
of 0.75 to the scaling factor.

62.5 kHz
inv_Kdco _modn = (3-2)
Kdco

Vamshi Krishna Chillara Master of Science Thesis

3-1 RTL design of low-speed digital logic 31

Additional delay elements (D flip-flops) are placed in the high frequency path to
ensure the delay of the modulation data is same via both the paths. The 3-bit input
control "dly_dco_path" selects the appropriate delayed version to be sent to the
DCO in the high frequency path.

3-1-3 TDC readout

Figure 3-4 shows the internal details of the TDC readout block of Figure 3-1.
dtcres [1:0]
D Q D Q D Q

Q Q Q
nrst nrst nrst
ckr
nrst
TDC_out[15:0] tdc tdc_code[3:0]
decoder

Append ’00’ at lsb 0 1 2 3 res_dly[1:0]

1
dtc_res_out[1:0] 1
<<
0
3’b0
tdc_res[5:0]

residue_corr_on

inv_ktdc [15:0] PHEF [16:0]

Figure 3-4: Implementation of TDC readout block.

The TDC gives the time difference between the snapshot of the ckvd2 signal,
ckvd2S , and the delayed reference signal FREFdly . In the TDC, FREFdly signal
is delayed by a series of inverters and the output of each inverter is sampled by the
ckvd2S signal. Figure 3-5 shows the internal waveforms of an eight-stage TDC. The
actual waveforms could be inverted when inverters are used as the delay elements.
The output of the TDC is "11110000". The transition from ’1’ to ’0’ indicates the
rising edge of the delayed FREFdly signal which occurs after four inverters in this
example. Hence, the snapshot signal lags the FREFdly signal by a delay equal to 4
inverter delays.
In this architecture, the snapshot signal is generated by the rising edge of FREFdly
signal and hence always lags behind it. Hence the TDC decoder output is assigned
a value of 0 when the time difference is equal to half the TDC range (shown in
Figure 3-5). Time difference less than this corresponds to negative phase error and
more corresponds to a positive error. In the actual implementation, a 16-stage TDC
is used and the output of TDC decoder, tdc_code[3:0], ranges from -8 to 7.
As discussed in Section 2-5-1, residue correction is employed to eliminate the impact
of DTC quantization step on the phase noise of ADPLL. The residue corresponds to
the fractional part of delay normalized to the DTC step. The DTC employs a cascade
of two inverters as the delay element while the TDC uses a single inverter. Thus
the DTC step is roughly twice that of the TDC and tracks over PVT variations.

Master of Science Thesis Vamshi Krishna Chillara

32 RTL design

CKVD2S

FREFdly0

FREFdly1

FREFdly2

FREFdly3

FREFdly4

FREFdly5

FREFdly6

FREFdly7

TDC range

Figure 3-5: Decoding the output of TDC.

Consequently, the residue is shifted left by 1 place (multiply by 2) and two zeros
(corresponding to fractional bits) are appended to the lsb of the "tdc_code" signal
before they are added together. Moreover, to ensure that both the residue and the
TDC output have same delay, a set of three D flip-flops are used to delay the residue.
The signal, "res_dly" selects one of these delayed versions. Residue correction can
be turned off by setting the res_corr_on signal to ’0’.
Finally, the corrected output of TDC is normalized to the ckvd2 period to obtain
the phase error. This is accomplished by multiplying it by "inv_ktdc " which is the
ratio of tdc step to ckvd2 period. Since, a fixed relation (2 times) exists between
the TDC step and that of DTC, inv_ktdc can be deduced from the value of inv_kdtc
which is estimated by the kdtc calibration block.

3-1-4 Phase detector

The phase detector implemented in this ADPLL is shown in Figure 3-6. A difference
mode architecture is used in which the frequency information is first extracted from
the phase to generate frequency error which is then accumulated to produce the
phase error. The integer part of the variable frequency, dPHVI , is obtained from the
difference of two successive samples of the phase incrementer. It is compared with
FCW to obtain the frequency error which is accumulated to produce the integer part
of phase error.
For the fractional part, a combination of DTC and TDC is used. As discussed in
Section 2-5-1, the accumulated value of the fcwf rac is used to generate the dtcctrl
as well as the residue that needs to be corrected from the output of TDC. The
overflow resulting from the accumulation of fcwf rac is added to the integer FCW.
The scaling by "inv_kdtc " is required to convert the normalization factor of the delay
from ckvd2 period to the DTC unit delay. To cover the required range with 1%

Vamshi Krishna Chillara Master of Science Thesis

3-1 RTL design of low-speed digital logic 33

PHVI [6:0] + dPHVI [5:0] dPHEI [7:0]

dPHEaccum [8:0]
D Q

+ {PHEI [8:0],16’b0}
− ckr Q
D Q nrst

ckr Q
nrst

trst
−
srst srst PHE[22:0]
D Q

ckr Q ZPRA
FCWI1 [6:0] dPHRI [6:0] nrst
FCW[22:16] D Q ZPRP
PHEF [16:0]
ckr Q
nrst
FCWaccum [16] dtcctrl1 [10:9] DTCresidue [1:0]
srst

dtcctrl1 [16:11]
carry-out FCWaccum [15:8] − 0 DTCctrl [5:0]
FCW[15:0]
1
D Q dtcctrl _SPI[5:0]
FCWaccum [15:0] +

ckr Q 8’d255 inv_kdtc [8:0] dtcctrl _extn

nrst
srst

Figure 3-6: Implementation of phase detector block.

resolution, 6 integer bits and 3 fractional bits are chosen. This value of "inv_kdtc "
is obtained from the kdtc calibration block whose basic principle is described in
Section 2-5-1. The total phase error is obtained by adding the output of TDC to the
integer part of the phase error.

An additional signal "dtcctrl _extn" is used to facilitate the stand-alone measurements

of DTC. When set to ’1’, the external control to the DTC, dtcctrl _SPI, overrides the
control signal generated by the phase detect logic.

Zero-phase restart

The wide tuning range is covered with fine frequency resolution (60 kHz) by dividing
the DCO into three banks: PVT, acquisition, and tracking with increasing resolutions
and decreasing tuning ranges. Only one of the three banks is active at a time and
the inputs to the banks are frozen at their previous values once the DCO mode is
switched. Thus each successive bank operates on the excess phase error left by its
immediate coarse-bank. Consequently, the phase error that maintains the input to
the coarser bank is not needed as this input is frozen at the instant of mode switch-
over. Hence, the accumulator that integrates the frequency error (see Figure 3-6) is
reset when the DCO mode is switched from PVT to acquisition or from acquisition to
tracking. The signals, "ZPRP " and "ZPRA " indicate the mode switchover and reset
the accumulator accordingly. The flip-flop used to delay the integer variable phase,
PHVI is reset by a synchronous reset signal which is delayed by 1 ckr period to
generate "trst". This delayed reset signal, trst, resets the accumulator that integrates
the frequency error. This ensures that the accumulator starts to add only after the
correct frequency error is available, irrespective of the instant at which the phase
incrementer is reset.

Master of Science Thesis Vamshi Krishna Chillara

34 RTL design

3-1-5 Loop filter—PVT bank

Since the three banks of the DCO have different range and resolution, different bits
of the phase error are used to generate their input control words. The tuning word
of the PVT bank depends on the msb bits of the phase error while that of the
tracking bank is derived from the lsb bits. Also, since the PVT bank and acquisition
bank are used only for frequency acquisition, the locking time is crucial while the
phase noise does not matter during this time. Hence these two banks have just
a proportional path resulting in a type-I PLL. Compared to a type-II PLL with
an additional integral path, type-I systems lock faster but the DCO phase noise
is suppressed to a lesser extent. A type-II system suppresses the DCO phase noise
with a 40 dB/decade slope whereas a type-I system does so with a 20 dB/decade.
Figure 3-7 shows top-level view of the loop filter implemented for each bank. The
Loop filterP V T

Gain OTWP
PROP CTRL
norm.

Loop filterAB

Gain OTWA
PROP CTRL
norm.

Phase
detect Loop filterT B

PROP

Gain IIR OTWT

CTRL
norm. filter

INT

Figure 3-7: Loop filter—top level block diagram.

PVT and acquisition banks have a proportional path followed by a normalization

and a control block. The tracking bank has an IIR filter and an integral path in
addition. The gain normalization blocks normalize the DCO control word with the
Kdco of the corresponding bank to avoid the impact of DCO gain variations on the
loop transfer function. The control blocks implement the functionality to generate
the zero-phase restart signals at mode switch-over and also to freeze the tuning word
once the DCO mode is changed.
Figure 3-8 shows the implementation of the proportional, normalization, and control
blocks of the PVT bank. The proportional constant, α, is chosen as a negative power
of 2 as this reduces the hardware complexity by replacing the multiplication by a
simple right shift. The number of right shifts can be programmed from 1 to 3 by
setting the value of "alphaP ". The fractional bits of the phase error are neglected as
they do not change the tuning word even with the minimum value of α = 1/23 .
The DCO gain normalization is done by multiplying the output of proportional path
with inv_kdco_P = F REF/kdco_P . The value of kdco should be evaluated at half
the DCO frequency as the loop operates at ckvd2. This normalizes the frequency

Vamshi Krishna Chillara Master of Science Thesis

3-1 RTL design of low-speed digital logic 35

PROP Gain norm.

phe_d2[7:0]
PHE[22:16] tempalpha [7:0] 0
>> >>
1
8’b0

1 tuneP [4:0]
alphaP <<
inv_kdco [1]

inv_kdco [0]
0
8’b0
1

CTRL inv_kdco [2]

OTWP V T [4]
reg_dco[4:0]

0 D Q OTWP V T [3:0]
tuneP [4:0]
1 banken ckr Q
nrst
nrst

banksel ZPRP mem_dcoP [4:0]

D Q

ckr Q
nrst
nrst

invisible

Figure 3-8: Loop filter and normalization for PVT bank.

information to reference frequency and decouples the loop transfer function from PVT
variations. Since high accuracy is not required in the PVT bank, this normalization
is implemented by a mantissa multiplier. A series of shifters and adders comprise
the multiplier as shown in Figure 3-8. It implements the following relation:
inv_kdco_P [1]  inv_kdco_P [0]
multiplier = inv_kdco_P [2] + ∗2 (3-3)

2
The LSB of the normalization factor is the exponent while the two MSB form
the mantissa. For typical values of fref = 32 MHz and kdco_P = 21.5/2 MHz,
inv_kdco_P is around 3.
The control block has the following three functions:

Freeze the PVT input on mode switch-over

The signal banksel , when deasserted, freezes the value of tuning word at reg_dco.
It is held permanently until reset or banksel is reasserted.
Generate zero-phase restart signal
The output of the OR gate in the Figure 3-8 is always ’1’ except the instants
when the value of banksel changes. Thus, a negative pulse of width equal to
the ckr period is generated to indicate the mode switch-over. This negative
pulse is used to clear the contents of the phase error accumulator.

Master of Science Thesis Vamshi Krishna Chillara

36 RTL design

Facilitate open-loop testing of the DCO

The signal banken , when zero, sets the value of tuning word calculated by the
preceding blocks to 0. Consequently, the loop has no effect on the control word
of DCO and is effectively open. The DCO can then be tested by varying the
value of mem_dcoP externally for instance via SPI. mem_dcoP can also be
used to start the DCO at a frequency different from the center frequency on
reset, thereby reducing the lock time.

Finally, the msb of the tuning word is inverted to convert the signed data into
unsigned which then controls the PVT bank of the DCO.

3-1-6 Loop filter—Acquisition bank

To generate the tuning word of acquisition bank, only the msb of the fractional
phase error is used along with 3 integer lsb bits. Before the PLL is locked, the edge
prediction is not accurate and hence the TDC goes out of its narrow range, thereby
behaving like a bang-bang phase detector. Hence, only the msb indicating the sign
of the fractional phase error is used. The proportional, normalization, and control
blocks are similar to those of the PVT bank except for changes in bit lengths (see Fig-
ure 3-9). Since the value of "alphaA " is at least 1, it is absorbed into inv_kdco_A to
reduce its bit length. The normalization factor is hence FREF/(2*kdco_A ), where
kdco_A should be evaluated at half the DCO frequency. The proportional path then
shifts the input phase error right by (alphaA -1).

The multiplication is similar to that of Eq. (3-1-5), except for an additional offset
of 4.
inv_kdco_A [1]  inv_kdco_A [0]
multiplier = 4 + inv_kdco_A [2] + ∗2 (3-4)

2
The control block is also similar and generates the zero-phase restart signal on mode
switch-over, freezes the tuning word at the instant of switch-over, and facilitates the
open-loop testing.

3-1-7 Loop filter—Tracking bank

After the acquisition bank is disabled, the frequency is locked to within one lsb of
the acquisition bank. The tracking bank then remains active until a new frequency
channel is required. The phase noise of the ADPLL is crucial in this interval and hence
a type-II loop filter is used. The control word for the tracing bank is generated by
the 9 msb bits of the fractional phase error. Figure 3-10 shows the implementation
details of the loop filter, normalization, and control block for the tracking bank.
Z-domain analysis of the phase-locked loop (PLL) gives the dependence of loop
bandwidth on the proportional constant, α, according to the Eq. (3-5) [32]. This
assumes that the DCO again is accurately estimated.
α
BW = fR (3-5)
2π

Vamshi Krishna Chillara Master of Science Thesis

3-1 RTL design of low-speed digital logic 37

Gain norm.

<<
PROP
2

phe_d2[6:0]
{PHE[22],PHE[18:15]} tempalpha [6:0] 0
>> >> tuneA [5:0]
1
8’b0

alphaA -1 1 <<
inv_kdco [1]

inv_kdco [0]
0
8’b0
1

CTRL inv_kdco [2]

OTWAB [5]
reg_dco[5:0]

0 D Q OTWAB [4:0]
tuneA [5:0]
1 banken ckr Q
nrst
nrst

banksel ZPRA mem_dcoA [5:0]

D Q

ckr Q
nrst
nrst
invisible

Figure 3-9: Loop filter and normalization for acquisition bank.

In this work, α = 2−alphaT and is restricted to negative powers of 2 to simplify the

hardware implementation. It can take values from 2−3 –2−7 . Accordingly, the loop
bandwidth can vary from 637 kHz–40 kHz. The value of integral loop constant, ρ,
affects the settling behavior of the PLL. The damping factor ζ of the system is given
by:
1 α
 
ζ= √ (3-6)
2 ρ
√
For an optimum settling behavior, ζ = 1/ 2, and hence ρ should vary from 2−7 –2−15 .
The value of ρ = 2−rho is made programmable and can take only negative powers of
2. The integral path can be disabled by setting the signal T2 to zero.
Since the lowest value of alphaT is fixed at 3, these 3 right shifts are absorbed into
the value of inv_kdco_T to reduce its bit length. Hence, the value of normalization
factor is divided by 23 as shown in Eq. (3-7). The alphaT and rho are accordingly
subtracted by three before they shift the input tuning word.
fR
inv_kdco_T = (3-7)
8 ∗ kdco_T
An additional IIR filter is used to further suppress the out-of-band phase noise. The
IIR filter implements the following difference equation and the implementation is

Master of Science Thesis Vamshi Krishna Chillara

38 RTL design

invisible
inv_kdco [8:0]
lambda[2:0]
{PHE[22],PHE[18:7]} tunet [15:0]
>> 0 tuneiir [16:0]
1
−
ckr ckrg >>
iiren
+ iiren
Q D
ckrg
nrst
IIR filter nrst

alphat [2:0]-3
tuneout [14:0]
>>

tuneiir [16 : 0]

0 D Q

1 ckr Q
nrst

tunerho [16:0] nrst

>> T2
OTWT B [9]
rho[3:0]-3

OTWT B_I [8:0]

tuneout [14:0] D Q

ckr Q OTWT B_F [4:0]

nrst
banksel
{mem_dcoT [8:0],5’b0}
OTW_data[10:0] banken nrst
invisible
Figure 3-10: Loop filter and normalization for tracking bank.

shown in Figure 3-10.

y[k] = (1 − λ)y[k − 1] + λx[k] (3-8)
where the value of λ = 2−lambda is limited to the negative powers of 2 and determines
the location of the additional pole that is introduced by the IIR filter according to
Eq. (3-9).
λ
fP = fR (3-9)
2π
As a rule of thumb, this pole is usually set at a frequency ten times to that of the
pole introduced by the proportional path. If needed, the IIR filter can be by-passed
by setting the signal iiren to 0. The clock is gated with this enable signal to ensure
that the IIR filter does not burn any power when disabled.
The two-point modulation requires that DCO gain be estimated and normalized
accurately. Hence, a full multiplier is used for gain normalization unlike the simplified
add and shift structure used for the other two banks. The output of the proportional
and integral path is summed to obtain the control word for the tracking bank.
The modulation data, if any, is added to this word to directly modulate the DCO.

Vamshi Krishna Chillara Master of Science Thesis

3-2 System simulation in Verilog 39

Also, banken signal can be set to ’0’ to facilitate open-loop testing similar to the
other banks. The tracking bank can then be tuned by changing the external word,
mem_dcoT .
The msb is inverted to convert the signed word into unsigned and the integer bits
are then sent to the tracking bank of the DCO. The 5 fractional bits are fed to the
first order Σ∆ modulator to improve the DCO resolution and hence the quantization
noise as discussed in Section 2-2-2

Σ∆ modulator

A 5-bit first order Σ∆ modulator is used to reduce the quantization noise from the
DCO. Figure 3-11 shows its block diagram. A multiplexer selects the dithering clock

OTWT B_F [4:0]

out[5] OTWf
D Q
sigdelen
Q
nrst
out[4:0]
nrst

ckr
0
ckvd16
1

clk_sel

Figure 3-11: First order Σ∆ modulator.

between ckr or ckvd16 depending on the requirements. For instance, in receive

mode, good out-of-band phase noise is required and hence a higher dithering rate
may be preferred. The signal clk_sel selects one of these two clocks. The divide-by-
2n signals of the DCO output signal are available from the phase incrementer used
to generate variable phase.

3-2 System simulation in Verilog

The high-speed blocks—DCO, divider, and phase incrementer—are modeled behav-
iorally in Verilog. Time-domain model of DCO as described in [49] is used for this
purpose. The low-speed blocks requiring custom design i.e., TDC, DTC, and snap-
shot circuits are also modeled. These models are used together with the rtl level
description of low-speed logic to perform system level simulations in Verilog.
Figure 3-12 shows important signals from a Verilog simulation of ADPLL. The signal
"bank_sel" changes from ’4’ to ’2’ to ’1’, indicating the transition of ADPLL from
PVT to acquisition to tracking state. The zero-phase restart pulses at each transition
can also be seen. The frequency of the ADPLL and input controls to each bank are
also shown. The input controls to each bank change only when the corresponding
bank is active and are frozen afterwards.

Master of Science Thesis Vamshi Krishna Chillara

40 RTL design

Figure 3-12: System level ADPLL simulation.

Figure 3-13 shows the zoom-in of Figure 3-12 for the PVT state. The PVT bank
brings the output frequency to within one lsb of the PVT bank to the required
value. Figure 3-14 shows the zoom-in of acquisition state and that of tracking state
is shown in Figure 3-15.

Figure 3-13: System level ADPLL simulation—PVT state.

Figure 3-14: System level ADPLL simulation—acquisition state.

Figure 3-15: System level ADPLL simulation—tracking state.

The TDC output code and hence the tracking bank input deviate by large values at
the start of frequency acquisition. This is the result of incorrect phase prediction at
the start which leads to bang-bang operation of the narrow-range TDC. As the output
frequency becomes closer to the target frequency, the phase prediction becomes
accurate and the TDC operates at its center. Eventually, the output code of TDC

Vamshi Krishna Chillara Master of Science Thesis

3-3 Estimated power consumption 41

oscillates around zero. This is observed in the simulation as shown in Figure 3-15.

3-3 Estimated power consumption

Cadence Encounter is used to synthesize the implemented rtl level low-speed logic.
After place and route, the extracted netlist is used along with the activity file gener-
ated from the system level simulation to estimate power consumption using Synopsis
PrimeTime. The estimated power breakdown of the low-speed digital logic is shown
in Table 3-1.
Table 3-1: Estimated power breakdown of the low-speed digital logic.

Block Power consumption (µW)

TX interface 14
TDC readout 9
FSM 2
Phase detector 17
Loop filter—PVT 4.5
Loop filter—acquisition 5
Loop filter—tracking 125
Digital loop filter 50
Gain normalization 25
IIR filter 40
KDTC calibration 35
DTC decoder 35

Total 250

Master of Science Thesis Vamshi Krishna Chillara

42 RTL design

Vamshi Krishna Chillara Master of Science Thesis

 Chapter 4

Circuit design

In this chapter, the circuit design and physical layout of the analog/high-speed
blocks: digitally controlled oscillator (DCO), DCO buffer, divider, and phase incre-
menter, are described with a focus on lowering the overall power consumption.

4-1 Digitally controlled oscillator (DCO)

As discussed in Section 2-1-1, a DCO is at the heart of an all-digital phase-locked
loop (ADPLL). It takes a digital input control word called the oscillator tuning
word (OTW) and generates a sinusoidal output with a frequency proportional to
OTW plus an offset. The performance of the frequency synthesizer—area, power,
and spectral purity—depends to a large extent on that of the DCO. Hence consid-
erable effort is put into its design, which is discussed in this section. The general
design considerations, namely power, phase noise, and tuning range, are first dis-
cussed followed by a description of its building blocks —inductor, active part, and
capacitor bank. The physical layout, which affects the overall performance is also
discussed and the simulation results with post-layout parasitics are presented.
An LC tank based oscillator with a fixed inductor and digitally tunable capacitor
banks is used to realize the DCO. The oscillation occurs at the resonance frequency
of the LC tank. A positive-feedback or a negative resistance is used to compensate
the energy-loss resulting from the parasitics in the LC tank, thereby sustaining the
oscillation. The frequency tuning can be achieved either by changing the inductor
or the capacitor. However, it is easier to change the capacitor rather than an induc-
tor in monolithic implementations. Moreover, adding switches to the inductor will
further degrade the already low quality factor of the on-chip inductors. Hence, a
large number of capacitor cells controlled by the OTW is used to achieve the digital
control of the oscillator frequency. The frequency of the DCO with N capacitor cells
and an inductance L is given by Eq. (4-1).
1
f= v (4-1)
u N −1
2π tL ∗
u X
C k
i=0

Master of Science Thesis 43 Vamshi Krishna Chillara

44 Circuit design

In this work, a DCO covering a frequency range of 2.4–2.7 GHz with a phase noise
of -110 dBc/Hz at 1 MHz offset from the oscillating frequency and a raw frequency
resolution of 60 kHz is targeted. The design goal is to achieve this phase noise
performance over the required tuning range with minimum power consumption. The
design variables are the choice of inductor and capacitor values, width and length
of the transistors in the active part and bias current.

4-1-1 Inductor

The power dissipated in the LC tank needs to be replenished so as to sustain the

oscillation, which places a lower limit on the power consumption of the DCO. This
loss power can be calculated by a simple tank model as shown in Figure 4-1. In

L Rs

−R

Figure 4-1: RLC model of the LC tank.

the figure, the losses in the inductor due to the finite resistance of the metal is
represented as a series resistance Rs . The quality factor of the on-chip inductors is
usually worse than that of the capacitor banks and hence they dominate the overall
energy loss of the LC tank. Hence, the capacitor losses are neglected. The negative
resistance is used to model the active element that compensates the LC tank loss.
The maximum energy stored in the inductor and capacitor is equal and is given by
Eq. (4-2).
1 2 1 2
Emax = LIpeak = CVpeak (4-2)
2 2
where, Vpeak and Ipeak represent the peak values of the voltage across the LC tank
and current through it. The current Ipeak flows through Rs resulting in a power loss
equal to
2
1 2 1 CVpeak Rs
Ploss = Ipeak Rs = (4-3)
2 2 L
The operating frequency is usually fixed and hence Eq. (4-3) can be rewritten as
2 2
1 Vpeak Rs 1 Vpeak
Ploss = = (4-4)
2 L2 ω 2 2 LωQL

where QL is the quality factor of the inductor defined as the ratio of the imaginary
part of the impedance to the real part as shown in Eq. (4-5).

ωL
QL = (4-5)
R

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 45

From Eq. (4-4) it is clear that for a given loss resistance and operating frequency of
the oscillator, the larger the inductance the lower is the power consumption. Also,
decreasing the series resistance or increasing the quality factor of the inductance
lowers the power consumption.
The largest value of the inductor that can be chosen is usually limited by the re-
quirement on tuning range or the area. For a given operating frequency, a large
value of inductance results in a small value of capacitance, limiting the tuning range
that can be achieved. Moreover, a large inductor is accompanied by a large coupling
capacitance to the substrate, thereby decreasing the self-resonant frequency. Beyond
this self-resonant frequency, the coil can no longer be used as an inductor thus im-
posing an upper limit on the achievable inductance value at a certain frequency in
standard CMOS process. Also, it should be noted that the larger the inductance
the bigger is the frequency step for a fixed capacitance step. On the other hand, the
quality factor is limited by the technology (thickness and conductivity of available
metal layers).
Finding the optimum value of inductance, which is just enough to satisfy the tuning
range with a reasonably large self-resonant frequency is non-trivial. After estimating
the amount of fixed parasitic capacitance from the capacitor banks and active part,
a value of 7.7 nH is chosen after some iterations. The inductance available from the
TSMC library is used in this work. The inductance with top most metal layers—
which are the thickest and hence have lowest resistivity—is chosen to maximize the
quality factor. Moreover, it results in lower coupling capacitance as it is farthest
from the substrate.
Figure 4-2 shows the plot of the inductance as a function of frequency across typical,
fast, and slow corners. The self-resonance frequency—beyond which an inductor
55.0

39.0
Inductance (n)

23.0 SS: 2.4G 8.272301n

7.0 TT: 2.4G 7.751025n

FF: 2.4G 7.240657n

-9.0

-25.0
0.0 2.0 4.0 6.0 8.0
Frequency (G)

Figure 4-2: Inductance vs frequency across process corners.

behaves like a capacitor—is sufficiently far (>6 GHz) from the required operating
frequencies (2.4–2.7 GHz). The value of inductance varies by almost 1 nH among
different corners. This corresponds to a frequency deviation of nearly 150 MHz at

Master of Science Thesis Vamshi Krishna Chillara

46 Circuit design

2.4 GHz. To ensure DCO supports the required tuning range across process variations,
a margin of 150 MHz on either side is added to its tuning range.
17.0

FF: 2.4G 15.84502 TT: 2.4G 14.16071

13.6
Quality factor

10.2 SS: 2.4G 12.74497

6.8

3.4

0.0
0.0 2.0 4.0 6.0 8.0
Frequency (G)

Figure 4-3: Q-factor vs frequency across process corners.

Figure 4-3 shows the plot of the quality factor of the inductance with frequency
across process corners. The quality factor is around 14 in the typical case with a
10% variation across corners.

4-1-2 Active part and biasing

A complementary cross-coupled topology is used to provide the negative resistance
in the circuit of Figure 4-1, which replenishes the tank losses. Compared to the
structure with just an NMOS or a PMOS, complementary structure reuses the bias
current, thereby providing roughly twice the transconductance for the same current.
It provides a negative resistance of
R = −2/(gm,n + gm,p ) (4-6)
where gm,n and gm,p denote the transconductance of NMOS and PMOS transistors
respectively.
Figure 4-4 shows the circuit schematic of the implemented DCO. Instead of a MOS
current source, a poly-silicon resistor is used for biasing the DCO [50]. The current
source is usually the dominating source of phase noise by means of flicker-noise up-
conversion. Using a resistor avoids this and the thermal noise associated with it is
filtered by means of a tail capacitor, Ctail .
The bias current is controlled by 5 parallel resistors connected to the supply rail by
PMOS switches. A binary 5-bit digital word controls these switches, and hence the
bias current. In addition, another resistor in parallel is always turned on providing
a minimum offset current. The DCO current can vary from 80 µA to 450 µA at 1 V
supply. The bias control can be used to implement swing voltage regulation in future
designs to ensure optimum current consumption over the entire frequency range.

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 47

VDD

Bias
Control 5

Ctail

7.7nH

5 Coarse
6 Medium

9 Fine

Figure 4-4: Circuit schematic of the implemented DCO.

The length of the transistors in the cross-coupled pair is chosen at 100 nm (minimum
length: 40 nm) to minimize the flicker noise. The width of the transistors is increased
until the gm is sufficient to sustain the oscillation. The PMOS transistors are made
thrice as wide as the NMOS devices to account for lower hole mobility. Using a
large aspect ratio pushes the transistors into weak-inversion region offering a better
gm –Id efficiency. However, it also increases the capacitance contribution from the
active part to the tank, limiting the achievable tuning range. Moreover, since this
capacitance comprises junction capacitance, it depends non-linearly on the node
voltage, making the oscillator susceptible to supply pushing.
Figure 4-5 shows the layout of the active part of the DCO. The fingers of the cross-
coupled pair are arranged in a common-centroid configuration to average out the
linear process variations. Also, the transistors are laid out to have same orientation
for better matching. The layout is made compact to minimize the routing parasitics
at the drain terminal of the cross-coupled pair as they are absorbed into the LC
tank, reducing the maximum frequency attainable.

4-1-3 Capacitor banks

Design of capacitor banks is challenging in that they need to be tunable over a large
frequency range with a fine step. A tuning range of 2.25 GHz to 2.85 GHz with
a 60 kHz step is targeted to leave enough margin for process variations to cover

Master of Science Thesis Vamshi Krishna Chillara

48 Circuit design

Ctail

To inductor

Cross-coupled
pair

Switchable
resistors
To inductor

Figure 4-5: Layout of the active part of the DCO.

the required 2.4 GHz to 2.7 GHz range. This results in a resolution requirement of
nearly 14 bits, which is difficult to achieve even with advanced component matching
techniques. Generally, a 9-bit resolution is possible without resorting to matching
techniques or digital calibration [32]. Fortunately, the fine 60 kHz resolution needs
to cover a frequency deviation of at most 2 MHz corresponding to the frequency
deviation required by the direct frequency modulation. Thus, a segmented approach
can be used where three banks—coarse, medium, and fine—cover the desired tuning
range with required resolution. The coarse, medium, and fine banks are referred to
as PVT, acquisition, and tracking banks following the nomenclature used in [32].
The PVT bank covers the whole tuning range with very coarse resolution. The ac-
quisition bank then brings the output frequency closer to the required channel fre-
quency. The PVT and acquisition banks are active only at the start of the frequency
acquisition as discussed in Section 3-1-1. Finally, the tracking bank locks to the
target frequency channel with a fine resolution and needs to cover a range equal to
either the step of medium bank or the modulation range, whichever is larger. On
top of this, it should have sufficient margin to correct the frequency drifts in the
oscillator over time.
The range and resolution of each bank is determined as follows. The range of the
PVT bank is made equal to the required tuning range. The resolution of the tracking
bank is determined by the required frequency resolution according to Eq. (4-7)

∆f = (2π 2 Lf 3 )∆C (4-7)

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 49

A 60 kHz resolution corresponds to a frequency step of roughly 20 aF at 2.7 GHz

output and 7.7 nH inductance. To have sufficient overlap between two consecutive
capacitor banks, a ratio of 7–8 is chosen between the step of the coarser bank to
the range of its immediate fine bank. Using these criteria, a 9-bit tracking bit with
a 60 kHz step, 6-bit acquisition bank with a 2.5 MHz step, and a 5-bit PVT bank
with a 20 MHz step are chosen.
Another important requirement of the capacitor banks is their quality factor. The
total tank quality factor is given by the mathematical parallel combination of the
inductor and capacitor quality factors. Hence, quality factor of the capacitor banks
should be made large compared to that of the inductor so that overall Q is limited
by that of the on-chip inductance. As mentioned earlier, a Q of 15 is achievable for
on-chip inductors in the TSMC 40 nm technology. Hence, a quality factor of 50 is
targeted for the capacitor banks in both ON and OFF states.

PVT bank

The PVT bank determines the tuning range of the DCO. A capacitor bank with
a large frequency range, i.e., large CCmax ratio is desired as it minimizes the off-
 
min
state capacitance. This in-turn allows the use of a larger inductance and hence
results in lower power consumption as discussed in Section 4-1-1. A switched MOM
configuration shown in Figure 4-6 is used a unit cell of the PVT bank as it can
provide high tuning range. When the switch is enabled, the series combination of

EN
CM OM CM OM
P N

Figure 4-6: Switched MOM configuration.

two MOM capacitors, CM OM /2, appears across the terminals P and N and the unit
cell is considered to be in ON state. On the other hand, when the switch is open,
the capacitance that appears across P and N is determined by the parasitics of the
switch and the MOM capacitors.
Quality factor
In the ON state, the switch of Figure 4-6 can be replaced by a resistance RON of
the transistor used to implement the switch. The impedance across P and N is then
given by Z = RON +  C1  giving rise to an on-state quality factor of
jω MOM
2

1
Qon = 
CM OM
 (4-8)
ωRon 2

It is clear that Ron of the switch should be made as small as possible to have a good
Q. Hence an NMOS is used instead of PMOS as the mobility and hence conductance
of the electrons is 2–3 times that of holes. The ON resistance of a MOS switch can
be expressed as
1
Ron = (4-9)
µn cox L (vgs − vth )
W

Master of Science Thesis Vamshi Krishna Chillara

50 Circuit design

Eq. (4-9) indicates that the aspect ratio W and the overdrive voltage (vgs − vth )
 
L
should be maximized to reduce the on resistance. However, increasing the aspect
ratio also increases the parasitic capacitance of the MOS switch and hence the
off-state capacitance, thereby degrading the capacitance range. To maximize the
overdrive voltage, two pull-down NMOS transistors are used to pull the DC voltage
of source and drain terminals of the MOS switch to ground in ON state. The aspect
ratio of the MOS switch is then increased until its Qon reaches 50.
In the off-state the parasitic capacitance between drain and source terminals of the
switch appears between the two MOM capacitors leading to an off-state capacitance
of
CM OM Cpar
Cof f = (4-10)
CM OM + 2Cpar

which is nearly equal to the value of parasitic capacitance. The capacitance has the
following contributions: drain and source junction capacitors of the NMOS switch,
drain junction capacitance of the pull-down transistors, and the parasitics from the
MOM capacitor to substrate. The quality-factor in the off-state is largely determined
by that of the MOM capacitors which is quite high.
The DC-voltage at the drain and source terminals of the NMOS switch is set by the
leakage current through the pull-down transistors which are now turned-off. Since
the DCO output swing is typically around 300 mV – 400 mV, the maximum negative
voltage at the source terminal of the NMOS switch is around 200 mV. Hence, the
gate-to-source voltage of the NMOS switch is always less than its threshold voltage,
ensuring the switch remains off.
Figure 4-7 shows the circuit implementation of the unit cell of the PVT bank. An

Enb
C C

En Enb
Enb Enb

Figure 4-7: Circuit schematic of the unit cell of PVT bank.

inverter is placed between the input control and the switch-enable so that capaci-
tance is lowest when the bank is turned on. This results in a positive kdco , i.e., the
frequency increases with increasing input control.
The 5-bit PVT bank is binary weighted and the cells corresponding to the higher
order bits are made from multiple unit cells. The cell corresponding to bit 1 comprises
21 unit cells and bit 2 comprises 22 unit cells and so on. This ensures that the
capacitance decreases monotonically with the input control. Also, the linearity is
improved as systematic mismatches are reduced.

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 51

Figure 4-8 shows the physical layout of the 5-bit PVT bank. The unit cells are
placed in a 4x8 matrix with 1 dummy cell. The cells are laid out such that they
have a common centroid to suppress the mismatches resulting from linear gradients
across the die. The layout parasitics are extracted using Calibre and the post-layout

Unit cell

CMOM

40 µm
switch

CMOM

60 µm

Figure 4-8: Layout of the PVT bank.

simulations to estimate the Q-factor and capacitance range are done using Cadence
Spectre. The capacitance and Q-factor are calculated from the input impedance of
the bank. Figure B-1 shows the C–V curve of the unit cell of the PVT bank.
The capacitance step is 8.8 fF with an off-state capacitance of 4.5 fF. The quality
factor in ON and OFF states is shown in Figure B-2. As can be seen, the quality
factor is limited in the ON-state and is 48, sufficiently higher than that of the
inductor. Figure 4-9 shows the total capacitance range of the PVT bank including
the routing parasitics. The PVT bank has a minimum capacitance step of 140 fF and
covers a capacitance range of 273 fF with a 8.8 fF step.
450.0

400.0
dx: 31.0
dy: 272.95577fA
Capacitance total (fA)

350.0 s: 8.8050249fA/
0.0 413.70769fA

300.0

250.0

200.0

31.0 140.75192fA
150.0

100.0
0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0
OTW_PVT[4:0]

Figure 4-9: Capacitance range of the PVT bank.

Master of Science Thesis Vamshi Krishna Chillara

52 Circuit design

Acquisition bank

The acquisition bank is implemented in a similar way as the PVT bank with smaller
MOM capacitors. From Eq. (4-8), it can be seen that the on-state Q-factor increases
when CM OM decreases. Consequently, smaller switches are sufficient to achieve the
required quality factor, resulting in a lower off-state capacitance. The 6-bit acquisi-
tion bank is realized from 63 unit cells controlled in a binary manner. The layout
of the bank is shown in Figure 4-10. The unit cells are arranged in a matrix of 8x8
while ensuring a common-centroid. The acquisition bank occupies lesser area than
PVT bank due to the lower CM OM used. The post-layout simulations are performed
30 µm

Unit cell

65 µm

Figure 4-10: Layout of the acquisition bank.

to estimate the value of capacitance step, quality factor and capacitance range, and
are shown in Figure B-3 and Figure B-4 respectively. The capacitance step of the
unit cell is 1.2 fF with an off-state capacitance of 0.7 fF. The quality factor is greater
than 50 in both ON and OFF states. Note that due to the presence of the inverter
at the input of the switch, the ON state corresponds to low enable voltage in the
simulation plots.

The total capacitance of the acquisition bank as a function of its 6-bit input con-
trol word is shown in Figure 4-11. The capacitance decreases monotonically with
OTW_AB[5:0]. The minimum capacitance from the acquisition bank is only 44 fF,
thanks to the smaller dimensions of the NMOS switch. The 6-bit acquisition bank
has a tuning range of 76 fF.

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 53

120.0

Capacitance total (fA)

0.0 121.13476fA
100.0

80.0

60.0 63.0 44.891721fA

dx: 63.0
dy: 76.243042fA
s: 1.210207fA/

40.0
0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0
OTW_AB[5:0]

Figure 4-11: Capacitance range of the acquisition bank.

Tracking bank

Tracking bank locks the PLL frequency to the target frequency with the required
resolution. The frequency resolution of this bank determines the resolution of the
DCO. To achieve a 60 kHz resolution, a 20 aF capacitance is required as given by
Eq. (4-7). The MOS varactors in an accumulation mode or depletion mode are
the common choices to achieve this fine resolution [17, 51]. However, this requires
accurate models for the varactor mode operation of the MOS transistor. Also, the
C-V transfer curve of the MOS varactor is susceptible to PVT variations. Hence,
fine bank is also realized using MOM capacitors which are better modeled and less
prone to PVT variations.
The circuit implementation of the unit cell of the tracking bank is shown in Figure 4-
12 [52]. When the control signal is high, the input to the NMOS switch is low and

Cb Cb

Enb
Cs Cs
En Enb

Enb Enb

Figure 4-12: Circuit schematic of the unit cell of tracking bank.

is hence turned off. The capacitance in this state is given by the series combination

Master of Science Thesis Vamshi Krishna Chillara

54 Circuit design

of capacitances Cb and Cs .
Cb Cs
Clow = (4-11)
2(Cb + Cs )
When the input control is low, the input to the switch is high leading to a higher
capacitance of C2s . The capacitance step is then obtained by

Cs2
∆C = (4-12)
2(Cb + Cs )

Thus a smaller capacitance step can be obtained by choosing a large value of Cb and
a small value of Cs . In the implementation, the minimum available capacitance from
the library for the MOM capacitors is chosen for Cs and the value of Cb is increased
until the required capacitance step of 20 aF is achieved. This resulted in a value of
45 fF for the big capacitance Cb .
The tracking bank is used for direct frequency modulation and hence its linearity is
crucial. Hence, the tracking bank is thermometer coded. This allows implementation
of dynamic element matching for improved matching performance in future designs.
For a 9-bit tracking bank, 511 unit cells are needed. With a large Cb of 45.5 fF,
a prohibitively large area is required. This not only increases the cost but also
results in increased routing parasitics. The increased parasitics limit the maximum
operating frequency warranting a smaller value of the inductor and increased power
consumption.
To address this issue, tracking bank is segmented into MSB cell with a step equal to
eight times that of the unit cell and LSB cell. The 6 MSB bits control the MSB cells
while the LSB cells are controlled by 3 LSB bits. In this way, only 70 cells—63 MSB
and 7 LSB—are required as opposed to 511, which is the case without segmentation.
In addition, the larger step size requirement of the MSB cells results in a smaller
value for Cb according to Eq. (4-12), further reducing the area of the tracking bank.
A 6:64 thermometer decoder is required to control the MSB cells which is both
power and area hungry. To avoid this, the MSB cells are arranged in a matrix of
8x8 and are controlled by two 3:8 decoders instead. The control logic along with the
MSB cell is shown in Figure 4-13. The bits <8:6> of the control word are converted
to 8 row signals and the next 3 bits, <5:3> control the columns. When the "row"
signal is high, all the banks in that row are turned on irrespective of the value of
the column signal. Only when a given row is not enabled, do the column signals
determine whether the cell is enabled. Another 3:8 decoder is used to control the
LSB bits. An additional LSB cell is used for Σ∆-dithering. In this way, a high-
speed adder required to add the control word of the tracking bank and the output
of the Σ∆ modulator is avoided. Thus 63 MSB cells and 8 LSB cells are used for
implementing the tracking bank.
Figure 4-14a and Figure 4-14b show the physical layout of the LSB and MSB cells
of the tracking bank. The layout of the total bank is shown in Figure 4-15. The LSB
cells are placed in the first row, above the MSB cells. Again the unit cells are laid
out to have a common centroid to minimize the effects of linear gradients across the
die. The tracking bank occupies an area of 90 µm x 55 µm which is only slightly
larger than that of the PVT bank.

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 55

Cb Cb

Enb
Cs Cs

RWLS Enb
Enb
CL

Enb
RW

Figure 4-13: Circuit schematic of the MSB cell of tracking bank.

Cs Cs Cs Cs

Cb Cb
Cb Cb

(a) LSB cell (b) MSB cell

Figure 4-14: Physical layout of the unit cell of tracking bank

The post-layout estimations of the capacitance step and quality factor of MSB cell
and LSB cell are shown in Figure B-7 and Figure B-8; and Figure B-5 and Figure B-
6, respectively. The quality factor of both banks is greater than 50 in ON and OFF
states. The LSB cell has a step of 18 aF and the MSB cell has a step of 145 fF which
is approximately eight times the LSB step.
Figure 4-16 shows the capacitance of the tracking bank as a function of its 9-bit
control word. The tracking bank has significant constant minimum capacitance of
73 fF. It covers a range of 9 fF with an average step of 18 aF.
The operating range and design of the quality factors of the three capacitor banks
is summarized in Table 4-1. The total off-state capacitance from all three banks is
around 260 fF.

Master of Science Thesis Vamshi Krishna Chillara

56 Circuit design

LSB cell
55 µm

MSB cells

MSB unit

90 µm

Figure 4-15: Physical layout of the tracking bank.

Table 4-1: Summary of capacitor banks.

Bank type Bits Cmin Range ∆C Qmin

(fF) (fF)
PVT 5 140.7 273 8.8 fF 48
Acquisition 6 45 76.2 1.2 fF 58
Tracking 9 73 9.5 18 aF 66
segmented (6+3)

82.5 dx: 511.0

0.0 82.472575fA dy: 9.4680866fA
s: 18.528545aA/
Capacitance total (fA)

80.0

77.5

75.0
511.0 73.004489fA

72.5

0.0 106.0 212.0 318.0 424.0 530.0

OTW_TB[8:0]

Figure 4-16: Capacitance range of the tracking bank.

Vamshi Krishna Chillara Master of Science Thesis

4-1 Digitally controlled oscillator (DCO) 57

4-1-4 Layout
The physical layout of the individual banks and the active part have already been
presented. These blocks are arranged to minimize the routing parasitics from the
inductor to capacitor banks and the active part as shown in Figure 4-17. Long

285 µm

150 µm
310 µm

110 µm
TB AB PVT

Active part

Figure 4-17: Layout of the DCO.

metal lines not only increase the fixed capacitance of the tank but also decrease the
quality factor by increasing the series resistance. Top metals with large width are
used for connecting the inductor with rest of the DCO to minimize the quality factor
degradation. The capacitor banks and the active part are placed symmetrically about
the inductor.

Post-layout simulations

The parasitics from the layout are extracted using Calibre and the post-layout sim-
ulations are performed to estimate the current consumption, swing, and phase-noise
of the DCO. The effect of bond wire connections from supply to the chip are modeled
by a 2 nH inductor. The capacitor banks are modeled using Verilog-A by using the
capacitance step, range, and quality factor obtained from separate post-layout sim-
ulations. The rest of the DCO is simulated using the Calibre extracted views. This
speeds-up the simulation significantly without sacrificing the accuracy.
Figure 4-18 shows the output of the DCO obtained from the transient simulation.
The single-ended output swing is around 335 mV for a current consumption of
148 µA. The common-mode voltage is around 370 mV and is also shown in the
figure. Figure 4-19 shows the phase-noise of the DCO estimated using the periodic
steady-state (PSS) analysis. A phase-noise of -113 dBc/Hz at 1 MHz offset from the
operating frequency is achieved. The major noise contributors are the inductance
and the cross-coupled pair. The current consumption can be traded for phase-noise
using the 5-bit bias control word.

Master of Science Thesis Vamshi Krishna Chillara

58 Circuit design

Figure 4-18: Transient simulation of the DCO.

Figure 4-19: Phase-noise simulation of the DCO.

Vamshi Krishna Chillara Master of Science Thesis

4-2 DCO buffer 59

4-2 DCO buffer

The DCO needs to drive the PA and divide-by-2 pre-scaler as shown in Figure 2-5. A
buffer is typically used to isolate the DCO from the effects of varying load, referred
as load-pulling. Also, it allows the DCO to operate in the current-limited regime with
a low output swing to reduce the power consumption. The implementation of this
DCO buffer is discussed in this section.

4-2-1 Self-biased inverter

Since inverter based buffers are power efficient, a self-biased inverter, shown in Fig-
ure 4-20, is typically used as the DCO buffer. The DC-level of the DCO output is

Rbias

From oscillator To PA and

divider

Cbias

Figure 4-20: Self-biased inverter as the DCO buffer.

prone to PVT variations. Consequently, the output of the oscillator is ac-coupled to

the buffer by means of a large coupling capacitor. Thus, the variations on the DC-
level of the oscillator output do not impact the buffer output. The DC-level at the
input of the buffer is fixed by a large resistor Rbias . Since the resistor is connected to
the gate of the NMOS and PMOS of the inverter, no DC voltage drop occurs across
it. This results in a same DC-voltage at the input and output nodes of the inverter
i.e., it lies on the line "Vin = Vout ". As shown in the Figure 4-21, the DC-level of

VTC

Vout

Vin Vbias

Figure 4-21: Biasing the self-biased inverter.

the signal is the point of intersection of the VTC and Vin = Vout curves. The VTC

Master of Science Thesis Vamshi Krishna Chillara

60 Circuit design

of the inverter is fixed such that this point of intersection corresponds to the point
of maximum sensitivity on the voltage transfer characteristic (VTC) of the inverter
and hence enables operation with low input-swing.
However, this approach uses passive components—Cbias and Rbias —that do not scale
with technology. Hence it occupies a large area leading to higher system costs. More-
over, the large resistor Rbias used for biasing is a source of significant thermal noise
which couples into the oscillator output, thereby degrading the phase noise perfor-
mance. Thus the oscillator needs to expend more current to maintain the required
phase noise levels. Furthermore, the large decoupling capacitor introduces signifi-
cant parasitics, thereby loading the output node of the oscillator. This increases the
power consumption as well as reduces the maximum operable frequency of the os-
cillator. Thus a self-biased inverter based buffer poses a serious challenge in scaling
down the power consumption.

4-2-2 DC coupled buffer with tunable VTC

To address the aforementioned problems of self-biased inverter, a DC-coupled buffer

with tunable VTC is proposed. In this approach, the bulky passives are avoided by
DC coupling the oscillator output to the buffer. The variation in the DC-level of
the DCO output now affects the operation of the buffer. Thus, to ensure the DCO
buffer always operates at its maximum sensitivity point, VTC of the inverter is tuned
as shown in Figure 4-22. In this way, the DC-level of the oscillator output always
corresponds to the maximum sensitivity point on the VTC of the buffer.
To summarize, in an ac-coupled self-biased inverter (Figure 4-20), the VTC is fixed
at its optimum point, such that the input DC-level set by Rbias ensures operation at
maximum sensitivity. On the other hand, in the presented approach, the DC-level of
the input buffer is fixed (by the DC-level of DCO output), while the VTC is changed
to ensure the operation at maximum sensitivity point across PVT variations. In this
way, an area efficient low-power buffer which operates with low-input swing over
PVT variations is realized.

Figure 4-22 illustrates the idea of tuning the VTC for operation across process vari-
ations. The VTC of the inverter is varied by digitally controlling the device ratio of

Tunable VTC

Vout wp/wn

Vbias
Vin

Figure 4-22: Tuning the VTC of the inverter.

Vamshi Krishna Chillara Master of Science Thesis

4-2 DCO buffer 61

PMOS to NMOS (wp /wn ) of the inverter to cover process variation.

Figure 4-23 shows the schematic of the proposed buffer with digitally tunable VTC.
The variation in DC-level of the oscillator output is estimated from Spectre simula-
tions across process corners. The number and width of the switchable PMOS/NMOS
devices is then chosen to cover this variation with extra margin. Four PMOS and
NMOS devices with binary weighted widths serve as the additional devices and are
controlled by the 5-bit digital word.
When the input code is "00000" i.e., none of the additional devices are connected, a
default PMOS-NMOS pair is connected. This pair is sized to drive the subsequent
load while operating at the maximum sensitivity point for an input DC-level cor-
responding to the typical corner. The MSB of the 5-bit buffer control determines
whether PMOS or NMOS are turned on while the 4 LSB bits determine the number
of those devices that are turned on.

VDD

EnP
WP

out1 Out

In

WN
EnN

Figure 4-23: Schematic of the proposed VTC-tunable buffer.

The subsequent buffer of Figure 4-23 is used to drive the large output load. In its
absence, the default pair of the tunable-buffer should be very large. This, in turn
warrants large sizes for additional devices to alter the wp /wn ratio significantly,
leading to a larger overall size of the buffer. Thus, the first buffer brings the low-
input swing to rail-to-rail level and drives the relatively small subsequent buffer
which drives the actual load (PA and divider).
By monitoring the duty-cycle of the oscillator output signal, the control code that
tunes the VTC to the desired position is generated. At the optimal biasing point,
the duty cycle of the oscillator output is 50%. If the input bias level is larger than
the optimum level, then the digital control enables more PMOS devices such that
the VTC shifts to the right. Similarly, if the input bias is smaller than the optimal
point, more NMOS devices are enabled to shift the VTC towards left.
From post-layout simulations across various process corners, variation of the DC-
level of the DCO output signal is estimated. At 1 V supply, the DC-level varies from
330 mV to 400 mV. The buffer is then designed to cover this range by adding NMOS
and PMOS devices in parallel to the first inverter. These are connected to GND and

Master of Science Thesis Vamshi Krishna Chillara

62 Circuit design

VDD lines via switches which are controlled by the 5-bit buffer control word. The
MSB of the control word decides if additional PMOS or NMOS devices are required
while the 4 LSB bits determine the number of devices connected in parallel to the
first stage.
Figure 4-24 shows the transient simulation of the buffer across various process cor-
ners. By setting an appropriate control word, the buffer can withstand the DC-level
variations on its input signal. The phase noise simulation from PSS analysis is also
shown. The buffer consumes 56 µA and has a phase noise of -123 dBc/Hz at 1 MHz
offset which 10 dB lower than that of the DCO.

Figure 4-24: Operation of the buffer across process corners and phase-noise.

Since the proposed structure avoids passive components, it occupies a very small
area of 5 µm x 10 µm and is aligned with the technology scaling. In comparison,
a self-biased inverter would need a coupling capacitor of the order of 0.5 pF and a
biasing resistor of the order of 200 kΩ. The coupling capacitance should be large
enough to not attenuate the sinusoidal output of the DCO and the value of 0.5 pF
is obtained from Spectre simulations. Using crtmom capacitor and ppoly resistors
from TSMC library, the area of these two is estimated at 20 µm x 20 µm or eight
times that of the DC-coupled buffer. Moreover, the power consumption is reduced
by avoiding driving the bulky parasitics associated with the decoupling capacitors.
Also, noise feed-through from the bias resistor is absent, thereby allowing lower
current consumption for a given phase noise requirement compared to the traditional
approach.

Vamshi Krishna Chillara Master of Science Thesis

4-3 Divider 63

4-3 Divider
As discussed in Section 2-1, a divide-by-2 block is used after the DCO buffer and
the divided down output clock is used for phase detection. This helps in reducing
the operating frequency of the phase incrementer and hence saves power. A sense-
amplifier based divider [5] is ideal when the low-input swing operation is needed. In
this work, since the DCO buffer boosts the output to rail-to-rail voltage, a dynamic
CMOS divider is used for its high-speed, low-power operation. The dynamic dividers
are fast since they avoid the positive feedback transistors required to store the output
until the next significant edge of the clock. Instead, the device and routing parasitic
capacitances are used for storing the value. Since the operation frequency is quite
high, the nodes are refreshed before the capacitor discharges, thereby retaining the
value. Transmission gate based and tri-state inverter based dividers are compared
to chose the optimum architecture.

4-3-1 Transmission-gate based dynamic divider

A transmission-gate based dynamic CMOS divider is shown in Figure 4-25 [53].

CKV CKV
I+ Q+

rst rst
CKV CKV

VDD VDD
nrst nrst
CKV CKV
Q-
I-

CKV CKV

nrst rst

Figure 4-25: Transmission-gate based dynamic CMOS divider.

The transmission-gate inverter combination acts as a simple D-latch, with para-

sitics at the output of transmission gate acting as the storage element. The cascade
of two-latches forms a master-slave flip-flop. Two such D-flip flops are cross-coupled
to obtain a divider-by-2 with quadrature output phases. The outputs of each trans-
mission gate should be initialized properly for this configuration to provide the re-
quired divide-by-2 signals. This is accomplished by the pull-up and pull-down MOS
transistors which are activated only at the reset.

Master of Science Thesis Vamshi Krishna Chillara

64 Circuit design

4-3-2 Tri-state inverter based dynamic divider

Figure 4-26 shows the simplified circuit schematic of the tri-state inverter based
dynamic divider. A tri-state inverter replaces the transmission-gate inverter combi-

VDD
CKV CKV
I+ Q+

CKV rst CKV rst

VDD VDD
nrst nrst
CKV CKV

Tri-state I- Q-
inverter CKV CKV

nrst rst

Figure 4-26: Tri-state inverter based dynamic CMOS divider.

nation of the previous configuration (see Figure 4-25). This structure is compared
with the transmission-gate based architecture for power consumption and phase
noise performance. It was observed that the transmission-gate based architecture
has a slightly better phase-noise performance for a given power consumption and
hence is adopted in this work.

4-3-3 Post-layout simulations

Initially, it was planned to use the quadrature phases of the divided-down DCO
output to reduce the detection range of DTC. However, this could not be implemented
and hence quadrature phases are no longer needed. Consequently, the divider of
Figure 4-25 is simplified to just one D-flip-flop with its inverted output and input
connected as shown in Figure 4-27.
The layout parasitics are extracted using Calibre and the post-layout simulations
to estimate the phase noise and power consumption of divider-by-2 are performed.
Figure 4-28 shows the transient simulation of the divider output at 1 V and 0.9 V
supply voltage. The two output phases, Q and Q̄, have a delay of around 40 ps at
both 1 V and 0.9 V. This is due to the presence of the extra inverter in one-path
(see Figure 4-27). The estimated current consumption is roughly around 30 µA for
both supply voltages.
Figure 4-29 shows the phase-noise of the divider at 1 V and 0.9 V supply voltages
estimated from PSS analysis. The phase-noise of the DCO is lower by 6 dB at the
output of the divider by virtue of division by 2. However, if the phase-noise from
the divider is large, it can limit the output phase noise. At 1 V supply, the phase
noise at 1 MHz offset is -140 dBc/Hz which is 17 dB lower than that of the buffer
and hence does not affect the phase noise of the output signal.

Vamshi Krishna Chillara Master of Science Thesis

4-3 Divider 65

CKV CKV
Q

CKV CKV

Figure 4-27: Simplified schematic of the implemented divider.

1.25
1V 27 TT

1.0

.75
V (V)

dx: 40.790378ps
dy: 393.57406fV
.5 s: 9.6486986mV/s

.25

0.0

7.0 7.5 8.0 8.5 9.0

time (ns)

1.0 0.9V 27 TT
dx: 41.858812ps
dy: 0.0V
.75 s: 0.0V/s
V (V)

.5

.25

0.0

7.0 7.5 8.0 8.5 9.0

time (ns)

Figure 4-28: Transient simulation of the divider at 1 V and 0.9 V supply.

Master of Science Thesis Vamshi Krishna Chillara

66 Circuit design

Figure 4-29: Phase noise of the divider at 1 V and 0.9 V supply.

Vamshi Krishna Chillara Master of Science Thesis

4-4 Phase incrementer 67

4-4 Phase incrementer

A phase-incrementer performs the integer phase detection of the variable clock by
counting the number of ckvd2 clock cycles. As discussed in Section 3-1-2, a 7-bit
integer counter is required. The phase incrementer could be implemented either as
synchronous or asynchronous logic. In a synchronous counter, all the flip-flops are
clocked by the input clock. This leads to a large power consumption but the outputs
are synchronized and the delay is small. Also, the ckvd2 clock is loaded by all the
flip-flops which might increase the power consumption of the divider that drives the
phase incrementer. For this reason, an asynchronous counter is used to realize the
phase incrementer.
In an asynchronous counter, the output of each stage triggers the succeeding stage.
Thus operating frequency of each succeeding stage is reduced by 2, resulting in lower
overall power consumption. However, in this implementation, the outputs of each
stage are available after the preceding stage with some delay. Figure 4-30 shows the
timing diagram of the implemented synchronous counter. After the rising edge of

CKVD2

CKR

PHV_I[6:0]

After delay
compensation

Figure 4-30: Timing waveforms of ckvd2, ckr, and phase incrementer output.

the ckvd2 signal, the output of the counter takes a long time before all the bits
are settled. If the rising edge ckr that samples the output of the phase incrementer
falls within this window when the output phase is still changing (highlighted area
in Figure 4-30), incorrect value of output phase is fed to the phase detector block
of the low-speed digital logic. This results in an incorrect estimation of phase error
and will break the lock.
To address this issue, the delay between ckr and ckvd2 rising edges are estimated
using post-layout simulations in all corners. Additional delay elements (buffers) are
added at the outputs of each stage of the phase incrementer to synchronize them and
ensure that the output of the phase incrementer begins to change only after the rising
edge of ckr. Figure 4-31 shows the circuit schematic of the phase incrementer. The
last two stages are implemented in a synchronous fashion since the delay is too large.
The D-flip-flop within the asynchronous counter is implemented by a transmission
gate based structure similar to that discussed in Section 4-3-1 while a library cell is
used for the sampling flip-flops.

Master of Science Thesis Vamshi Krishna Chillara

68 Circuit design

D D D D D D
D
CKVD2 Q Q Q
Q Q Q Q
Q Q Q Q Q Q Q

PHV
7
Delay compensation D
CKR

Figure 4-31: Circuit schematic of the phase incrementer.

Vamshi Krishna Chillara Master of Science Thesis

 Chapter 5

Measurements

The ultra-low-power ADPLL implemented in this work is fabricated in TSMC LP

40 nm CMOS process. The measurement set-up, stand-alone DCO measurements
and ADPLL measurements are presented in this chapter.

5-1 ADPLL test plan

The chip micrograph of the low-power ADPLL is shown in Figure 5-1. The chip is
pad-limited and occupies an active core area of only 0.2 mm2 . It has separate power
supplies for DCO, TDC/DTC, low-speed logic, high-speed blocks, and the power am-
plifier. This reduces the noise coupling from digital logic into DCO or TDC via supply.
They also have separate grounds. The metal casing available with the package is con-
nected to all the GND pins, expect the noisy digital-GND, of the IC via down-bonds
to keep the inductance minimum. The separate power supplies helps evaluate the
current consumption of each of these blocks separately.

PA
Buf.
310 µm

& Div.
Digital DCO

TDC/DTC
650 µm

Figure 5-1: Chip-micrograph of the ADPLL prototype.

The chip is placed in a QFN32 package. The packaged chip is mounted on a PCB
which also contains LDO regulators to provide required supply voltages. Also, an

Master of Science Thesis 69 Vamshi Krishna Chillara

70 Measurements

FPGA interface with required voltage level-shifters is mounted on the PCB. An ex-
ternal 32 MHz clock generated by a signal generator is used as the reference clock
for this ADPLL. It is provided via an SMA port of the PCB. Another SMA port
provides the output of the PA which is read into the spectrum analyzer to measure
the phase noise. The photographs of the test PCB and test bench setup are shown
in Figure A-2 and Figure A-3, respectively.
Figure 5-2 shows the block diagram of test-setup. A Xilinx FPGA board acts as an

Matlab

FPGA
Spectrum
analyzer
PA output

Signal
ADPLL PCB generator

Supply FREF input

Figure 5-2: Block diagram of ADPLL test setup.

interface to the PC and the SPI implemented on the chip. A Matlab program
updates the SPI registers via the interface implemented in FPGA. The modulation
data required to test the direct frequency modulation capability of the ADPLL is
also implemented in the FPGA. Since SPI limits the frequency at which the data
can change, the 10-bit modulation data is read by the ADPLL directly through bond
pads.

5-2 Measurement results

The open-loop DCO and closed-loop ADPLL measurement results are presented in
this section.

5-2-1 Open-loop DCO measurements

The performance of the DCO, namely phase noise, frequency range, and power con-
sumption, are characterized in this section. The loop is opened to characterize the
free-running DCO performance. This is done by setting the bank_en signal to "000",
as discussed in Section 3-1-5. mem_dco signal of each bank is set to control the
tuning word of the corresponding bank of DCO. The mem_dco signals represent
signed data and its MSB is flipped internally in the control block of the low-speed
logic before it is applied to the DCO.

Vamshi Krishna Chillara Master of Science Thesis

5-2 Measurement results 71

Tuning range

The DCO is designed to cover 2.25 GHz – 2.85 GHz using three banks—5-bit PVT,
6-bit acquisition, and 9-bit tracking—to meet the required 2.4 GHz – 2.7 GHz fre-
quency range. Figure 5-3 shows the measured frequency of the DCO with varying
PVT and acquisition code at 1 V supply.

2800

2700

2600
Frequency [MHz]

2500 PVT : 0
PVT : 4
PVT : 8
2400 PVT : 12
PVT : 16
PVT : 20
2300 PVT : 24
PVT : 28
PVT : 31
2200

2100

2000
0 10 20 30 40 50 60 70

OTW_AB[5:0]

Figure 5-3: Measured tuning range of the DCO at 1 V supply.

The DCO covers the frequency range of 2.1 GHz – 2.7 GHz. Although the target
frequency bands are covered, the frequency is shifted by around 150 MHz compared
to the post-layout simulations. One reason could be the change in inductance value
due to process variations. As discussed in Section 4-1-1, the inductance value can
change by 10% over different corners leading to a frequency shift. Another possibility
could be the under estimation of the parasitic capacitance by the extraction tool.
The frequency step of the PVT bank is around 11.6 MHz at the lowest operating fre-
quency (2.1 GHz) and is 25.7 MHz at the highest operating frequency. At the typical
running frequency, 2.4 GHz, the frequency step of the PVT bank is 17 MHz which
is close to the simulated value. The frequency step of acquisition bank is 1.4 MHz,
2.3 MHz, and 3.1 MHz at the lowest, typical, and highest operating frequencies, re-
spectively. The PVT bank covers a frequency range of 530 MHz while the acquisition
bank has a range of around 150 MHz when operating around 2.4 GHz frequency.
The tuning range of the tracking bank is shown in Figure 5-4. The control words
of the PVT and acquisition banks are tuned to change the operating frequency to
around 2.44 GHz. The control word for the tracking bank is then swept to obtain
its frequency range. It can be seen that the tracking range covers a range of nearly
20 MHz. The frequency step is around 40 kHz, slightly lower than that expected
from post-layout simulations. The possible reason is the larger parasitics in off-state
than expected from simulations. However, since the range is sufficiently larger than
the step of acquisition bank, it is not an issue.

Master of Science Thesis Vamshi Krishna Chillara

72 Measurements

2460

2455

Frequency [MHz]
2450

2445

2440

2435
0 50 100 150 200 250 300 350 400 450 500

OTW_TB[8:0]

Figure 5-4: Measured tuning range of the tracking bank of the DCO.

Table 5-1 summarizes the measurement results of the frequency range of the three
banks of the digitally controlled oscillator (DCO) at the typical operating frequency
of around 2.4 GHz. We can see that the range of the finer bank is around 7 times
that of its immediate coarse bank ensuring sufficient overlap between the banks.

Table 5-1: Measurement results of capacitor banks at around 2.4 GHz

PVT Acquisition Tracking

No. of bits 5 6 9
Frequency 17 MHz 2.3 MHz 40 kHz
step
Frequency 530 MHz 150 MHz 20 MHz
range

Phase noise and power consumption

The phase noise and power consumption of the oscillator are measured at 2.4 GHz
operating frequency. The DCO bias current is changed by tuning the 5-bit digital
control word as discussed in Section 4-1-2. The measured phase noise of the DCOis
shown in Figure 5-5. The DCO has a phase noise of -115.3 at 1 MHz offset for a
combined (DCO+buffers) power consumption of 450 µA when operating at 2.46 GHz.
The current can be decreased to trade-off performance by tuning the bias control
word. Figure 5-6 shows the plot of the measured phase noise of DCO as a function
of current consumed of DCO and buffer. Since the DCO buffer and DCO share the
same power supply, the power consumed by the DCO alone could not be measured.
A FoM given by Eq. (5-1) is typically used to evaluate the performance of an oscil-
lator. It takes into account the power consumption and phase noise to enable a fair
comparison.
 ∆f 2  P ower 
F oM = L(∆f ) + 10 log10 + 10 log10 (5-1)
f0 1 mW

Vamshi Krishna Chillara Master of Science Thesis

5-2 Measurement results 73

Figure 5-5: Measured phase noise of the DCO.

Since the power consumption of DCO alone could not be measured, the post layout
estimation of the buffer power is used to estimate the DCO power from the combined
power consumption. Post-layout simulations show that each buffer consumes around
60 µA and hence the power consumption of DCO is 330 µA for a phase noise of -
115.3 dBc/Hz resulting in an FoM of -187.7 dB.
For a current consumption of around 360 µA, the phase noise at 1 MHz offset is
around -112 dBc/Hz—the target value. However, the current consumption is around
90 µA higher than that expected from the post-layout simulations. The possible rea-
son is that the quality factor of the inductor is less than the expected 14. The reduced
quality factor degrades the phase noise and hence the DCO needs more current to
maintain the required performance. This is also evident from the observation that a
higher value of bias control word is needed to start-up the DCO oscillation than that
estimated from simulations. The tank loss is higher and hence needs more current
to replenish it to sustain the oscillation.
The phase-noise improves with the bias current until the current consumption is
400 µA. The DCO operates in the so-called current-limited range and its output
swing increases with bias current. The increased swing results in a better phase noise
performance. However, once the current is too large, the DCO enters the voltage-
limited regime. In this mode, the output swing of the DCO is limited by the available
voltage headroom. Hence increasing the current has negligible returns in terms of
the phase noise improvement.

5-2-2 Loop-locking behavior

The settling time of the PLL is measured using a signal analyzer and is shown in
Figure 5-7. From the figure it can be seen that, initially, the frequency deviates by
a large value. In this region, the phase prediction is not accurate; consequently, the

Master of Science Thesis Vamshi Krishna Chillara

74 Measurements

-107
-108

PN@1 MHz [dBc/Hz]

-109
-110
-111
-112
-113
-114
-115
-116
-117
-118
300 350 400 450 500 550 600
DCO+Buffer current (µA)

Figure 5-6: Measured phase noise of the DCO versus current.

Demodulated frequency

Bang-bang settling Within

Outside TDC’s range TDC’s range

Settling behavior

Figure 5-7: Measured settling behavior of the ADPLL.

phase error is out of narrow range of the TDC. The TDC hence acts like a bang-bang
phase detector during this time period. Eventually, the output frequency becomes
closer to the target value reducing the phase error to within the TDC’s range. Hence
the frequency deviation and phase noise is small. The ADPLL settles to the target
value within 16 µs.

5-2-3 Spectral purity and phase noise

Figure 5-8 shows the spectrum of the ADPLL output clock when the frequency com-
mand word (FCW) set to 37.5 corresponding to a target frequency of 2.4 GHz. The
reference spur is quite low at -70 dBc. The fractional spur occurring at 0.5*FREF,
which is 16 MHz is also below 65 dBc as it corresponds to a channel with large
fractional FCW.
The magnitude of the fractional spurs is measured for all the channels that com-

Vamshi Krishna Chillara Master of Science Thesis

5-2 Measurement results 75

prise the Bluetooth Smart, 2.4 GHz – 2.48 GHz with a 2 MHz spacing. They are
plotted in Figure 5-9. The worst-case fractional spur is -38 dBc for the near-integer

Integer channel (FCW=38)

-35

Fractional spur [dBc]

-40

-45

-50

Fractional spur
-55
Reference spur
-60
2400 2420 2440 2460 2480
Frequency [MHz]
Frequency [MHz]
Figure 5-8: Output spectrum of the
ADPLL for FCW = 37.5. Figure 5-9: Fractional spur over
Bluetooth Smart channels.

channels. Although this value meets the target requirements (< -30 dBc) it is high.
The possible reasons could be the mismatch between the individual delay elements
in the DTC [22]. Several spur-reduction techniques are proposed in the literature to
address this issue. The FREF dithering employed in [22, 23] may be adapted to this
architecture in future designs to improve the fractional spur performance.
The phase-noise plot of the frequency synthesizer measured using an Agilent 4440A
spectrum analyzer is shown in Figure 5-10 for FCW = 38.125.

Figure 5-10: Measured phase noise of the synthesizer for FCW = 38.125.

The loop band-width is set to around 200 kHz by setting the proportional and
integral constants of the tracking bank, α = 2−5 and ρ = 2−11 . The integrated phase

Master of Science Thesis Vamshi Krishna Chillara

76 Measurements

noise between 1 kHz – 100 MHz is 1.7 ps when FCW = 38.125. The phase noise at
very low frequency offsets is dominated by the reference signal. The in-band phase
noise is -90 dBc/Hz and is limited by either the accuracy of DTC gain calibration or
the TDC resolution. The out-of band phase noise at 1 MHz offset is -108.7 dBc/Hz.
The phase noise of the synthesizer for far-off integer channel is shown in Figure 5-
11 corresponding to an FCW of 37.5. The integrated jitter is 1.38 ps indicating the
improvement possible by applying spur-reduction techniques.

Figure 5-11: Measured phase noise of the synthesizer for FCW = 37.5.

5-2-4 Direct frequency modulation

The implemented ADPLL is capable of direct frequency modulation. It performs 2-
point modulation to eliminate the impact of loop-bandwidth on the maximum data-
rate achievable. The ADPLL is configured to provide modulation data for the two
targeted standards—ZigBee and Bluetooth Smart. The modulation data is generated
by the FPGA included in the test setup (see Figure 5-2).
Figure 5-12 and Figure 5-13 show the 2 Mcps HS-OQPSK modulation provided by
the ADPLL. The ADPLL provides the modulation with 2.3% EVM while fulling the
spectral mask requirements.
The 1 Mbps GFSK modulation provided by the ADPLL are shown in Figure 5-14
and Figure 5-15. The ADPLL provides the modulation with an FSK error of 5.2%
(spec. < 20%) and fulfills the spectral mask requirements.

Vamshi Krishna Chillara Master of Science Thesis

5-2 Measurement results 77

Figure 5-12: Measured ZigBee modulation accuracy.

Figure 5-13: Measured ZigBee spectrum.

Master of Science Thesis Vamshi Krishna Chillara

78 Measurements

Figure 5-14: Measured Bluetooth Smart modulation accuracy.

FC=2.4GHz
Bluetooth Smart
spectral mask

Bluetooth Smart
spectral mask
1 MHz/div

Figure 5-15: Measured Bluetooth Smart spectrum.

Vamshi Krishna Chillara Master of Science Thesis

5-2 Measurement results 79

5-2-5 Power consumption

The power break-down of the ADPLL is shown in Table 5-2. The power consumption

Table 5-2: Measured power break-down of the ADPLL.

Power consumption (µW)

DCO+buffer 450
low-speed digital 270
Divider + 100
Phase incrementer
TDC+DTC 40

Total 860

of the DCO and buffer is dominant. The high frequency circuits divider and phase
incrementer consume only 100 µW, thanks to the asynchronous counter architec-
ture and dynamic logic for the divider. Most importantly, the TDC and DTC, which
perform the fractional phase detection consume only 40 µW compared to the typ-
ical mW-level power consumption in time-to-digital converters (TDCs). The phase
prediction and snapshotting techniques enabled the narrow-range low-frequency op-
eration of TDC as discussed in Section 2-1. This proves the effectiveness of the DTC-
assisted snapshot TDC in reducing the power consumption drastically compared to
the conventional stand-alone TDC. The supply voltage and power consumption can
be further reduced to 0.9 V and 750 µW by trading-off jitter performance (2.2 ps).

5-2-6 Performance summary and comparison

The performance of the ADPLL designed in this work is summarized and compared
to the state-of-the-art PLLs in the literature and is shown in Table 5-3. The total
power consumption of the ADPLL is 860 µW at 1 V supply for an integrated jitter
of 1.7 ps operating at 2.4 GHz. This work achieves the lowest power consumption
among the multi-GHz ADPLLs published in the literature with a state-of-the-art FoM
of -236 dB.
Figure 5-16 compares the presented ADPLL with the state-of-the art PLLs in literature
in terms of jitter variance and power consumption. The ADPLLs are denoted in
black. The CP-PLLs with lowest power and highest performance are also depicted (in
blue). The jitter2 -power FoM is also shown along with the desired direction i.e., to
achieve low power and low jitter simultaneously. It is evident that this work presents
the first sub-mW fractional-N ADPLL and achieves a power consumption at least 5
times lower than that of the ADPLLs with similar FoM. Also, this ADPLL occupies
3.75 times smaller area compared to its best performing analog counterpart [5] for
similar applications, indicating its huge potential for cost savings. The sub-mW
power consumption of this ADPLL shows the feasibility of leveraging ADPLLs in
ultra-low-power applications.



F oM = 10log10 P
[30]
1 2


σjitter ∗ 1mW

Master of Science Thesis Vamshi Krishna Chillara

80 Measurements

Table 5-3: Comparison with the state-of-the-art.

This work [5] [12] [43] [42] [45]

ISSCC’12 ISSCC’04 ISSCC’11 ISSCC’11 ISSCC’13
Architecture ADPLL CP-PLL ADPLL ADPLL ADPLL ADPLL
DTC+TDC Analog TDC-based Bang-Bang Bang-bang TDC-based

Application Bluetooth Bluetooth Bluetooth NA 4G Cellular Bluetooth

Smart(V4)/ Smart(V4) (V1) EDR(V2)
ZigBee ZiBbee
Technology 40 nm 90 nm 130 nm 65 nm 40 nm 40 nm
Reference 32 MHz 24 MHz 13 MHz 48 MHz 40 MHz 26 MHz
Output (GHz) 2.1–2.7 1.7–2.48 2.4 4.9–6.9 2.9–4.0 2.4
RMS Jitter (ps) 1.71 2.66 1.02 0.61 0.56 0.98
Power (mW) 0.86 1.1 30 24 4.5 4.55
Supply 1 V 1.2 V 1.5 V 1.2 V 1.2 V 1.3 V
Reference spur -70 dBc -62 dBc -80 dBc -67 dBc -72 dBc -80 dBc
Core area(mm2 ) 0.2 0.75 0.8 0.91 0.22 0.075
PN @ 1 MHz -109 -111 -86@10 kHz -116 -110 -113
offset
FM capability Two-point Two-point Two-point No Two-point Two-point
FoM1 (dB) -236 -231 -225 -230 -238.3 -233.6

Figure 5-16: Jitter variance-power plot of state-of-the-art PLLs.

Vamshi Krishna Chillara Master of Science Thesis

 Chapter 6

Conclusions

In this thesis, the theory and implementation of an ultra-low-power all-digital phase-

locked loop (ADPLL) for frequency synthesis and modulation in ultra-low-power
transceivers is presented. In Chapter 2, it has been shown that TDC remains the
main bottleneck in reducing the power consumption of ADPLLs to sub-mW levels.
To this end, several low-power techniques are presented.
The power consumption is reduced at architecture level by using a combination
of digital-to-time converter (DTC) and time-to-digital converter (TDC) with snap-
shotting to replace the traditional power-hungry TDC for fractional phase detection.
This reduces the required detection range as well as the operating frequency of the
TDC resulting in huge power savings. At the circuit-level, the power consumption of
the DCO is reduced by using a low-power DCO buffer with tunable voltage transfer
characteristic (VTC). This avoids bulky decoupling capacitors and biasing resistors,
thereby reducing the power and area of the DCO plus buffers.
The RTL design of the low-speed digital logic and the circuit design and physical
layout of the high speed blocks—DCO, DCO buffer, divider, and phase incrementer—
are discussed in detail. To evaluate the effectiveness of the low-power techniques
presented, a prototype is implemented in a TSMC LP 40 nm CMOS process. The
synthesizer has a measured integrated jitter of 1.7 ps for a power consumption of
860 µW leading to a jitter2 -power FoM of -236 dB. This is at least 5 dB better than
that achieved by the published PLLs in literature with similar power consumption [5].
The achieved FoM is slightly lower than the best FoM reported for ADPLLs, but has
at least 5x lower consumption. In addition, the prototype ADPLL also supports
high data-rate frequency modulation, and is demonstrated for ZigBee and Bluetooth
Smart standards.
Figure 6-1 shows the jitter2 -power FoM of the state-of-the-art fractional-N ADPLLs
plotted as a function of power consumption. This work presents the first RF ADPLL
with a sub-mW power consumption with an FoM close to the state-of-the-art. From
Figure 6-1, it can be observed that high performance ADPLLs tend to have a better
FoM compared to low-power ADPLLs. The presented techniques enable ADPLLs to
break the sub-mW barrier and thus to be employed in the emerging ultra-low-power
WPAN applications.

Master of Science Thesis 81 Vamshi Krishna Chillara

82 Conclusions

−220
VLSI'13 11.2 ISSCC'10 26.5

ISSCC'11 5.3 ISSCC'13 20.6

HS Kim JSSC Jul '13

−225
L. Xu CICC'09 ISSCC'11 3.1
ISSCC'12 14.5 VLSI'10 14.3
ISSCC'10 26.6
ISSCC'11 3.2 ISSCC'11 5.6
−230
FoM [dB]

ISSCC'09 5.1 ISSCC'10 26.7

ISSCC'08 19.1
ISSCC'13 19.8
−235 VLSI'09 18.2

This work

ISSCC'11 5.1
−240 VLSI'11 11.1
Yao JSSC Mar '13

−245
1 10 100

Power [mw]

Figure 6-1: FoM versus power consumption of state-of-the-art PLLs.

6-1 Future work

• Although the power consumption of the TDC is reduced drastically, DCO con-
sumes considerable power. While the power consumption is limited mainly by
the Q-factor of the on-chip inductor, some improvements are possible. The
bias current of the DCO in this implementation is varied by changing the top
resistor. However, the cross-coupled transistors remain unchanged and hence
are optimized for only a limited range of bias current. This can be solved
by controlling the number of cross-coupled pair resistor cells attached to the
LC-tank instead. Each such cell carries a fixed current and hence the power
consumption and phase noise are optimum irrespective of the bias current.
Also, swing regulation of the DCO should be implemented to ensure constant
swing at all frequencies of operation.

• The automatic calibration of DC-coupled DCO buffer should be implemented.

One way would be to measure the output duty cycle to control the buffer
control word so as to maintain the 50% duty-cycle.

• Although the fractional spurs satisfy the requirements of the targeted appli-
cation, they are still quite high. One possible way to mitigate the spurs is to
increase the size of the delay cells of DTC to improve matching. Since the DTC
consumes only 2.5% of the total power, increased size would have little impact
on the overall power consumption. Also, FREF dithering proposed in [22, 23]
may be adapted if needed. In addition, multiple phases of DCO could be ex-
ploited to further reduce the DTC range. This reduces the INL and the reduced
power can be traded to further improve the matching performance.

Vamshi Krishna Chillara Master of Science Thesis

 Appendix A

Chip pinout, bonding diagram, and

measurement setup

Table A-1 lists the pinout configuration of the implemented ADPLL prototype. The
bonding diagram with the QFN32 package is shown in Figure A-1. The package has
a metal layer underneath to which numerous down-bonds are made from IC, thereby
minimizing the length of grounding bond wires.

32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 9 10 11 12 13 14 15 16 17

56

Figure A-1: Bonding diagram of the ADPLL IC.

Master of Science Thesis 83 Vamshi Krishna Chillara

84 Chip pinout, bonding diagram, and measurement setup

Table A-1: Chip pinout of the ADPLL prototype.

Pin number Name Description

1 — Grounded
2 TDC_OUT<3>
3 TDC_OUT<2> 4-bit TDC
4 TDC_OUT<1> output
5 TDC_OUT<0>
6 PA_CM Buffer calibration
7 VDD_PA 1 V PA supply
8 VDD_PA 1 V PA supply
9 PA_OUT Output clock
10 VDD_DIV 1 V divider supply
11 NRST Asynchronous reset
acive low
12 GND_DIG Digital ground
13 VDD_DIG 1 V digital supply
14 MOSI SPI Control signal
15 MISO SPI Control signal
16 SCLK SPI clock
17 CS SPI select
18 TX_data<9>
19 TX_data<8>
20 TX_data<7> 10-bit modulation
21 TX_data<6> data
22 TX_data<5>
23 TX_data<4>
24 TX_data<3>
25 TX_data<2>
26 TX_data<1>
27 TX_data<0>
28 VDD_TDC 1 V TDC supply
29 DTC_OUT DTC output
for testing
30 TDC_IN TDC input
for testing
31 CLK_IN 32 MHz reference
32 VDD_DCO 1 V DCO supply

Vamshi Krishna Chillara Master of Science Thesis

 85

Measurement setup
The test PCB on which the packaged ADPLL prototype is mounted is shown in
Figure A-2. The output clock of the ADPLL is taken out via an SMA connector.
External signal generator is used to supply the reference clock and is connected to
the test PCB via another SMA connector. The SPI registers of the ADPLL IC are
controlled by a Matlab program via FPGA.

To FPGA

To PC

Level shifters
Reference clock

ADPLL IC

LDO Matching Output clock

network

Figure A-2: Photograph of the test PCB.

The test bench built to characterize the implemented ADPLL prototype is shown in
Figure A-3.

Signal generator

Power supply
Spectrum analyzer
FPGA

Figure A-3: Photograph of the test bench setup.

Master of Science Thesis Vamshi Krishna Chillara

86 Chip pinout, bonding diagram, and measurement setup

Vamshi Krishna Chillara Master of Science Thesis

 Appendix B

Simulations

B-1 Simulations of the capacitor banks

The post-layout estimations of the quality factor and capacitance step of the capac-
itor banks are shown here:
15.0

13.323542fA

12.5
Capacitance (fA)

10.0

dx: 490.0m
7.5 dy: 8.8067973fA
s: 17.973056fA/

5.0 4.5167448fA

2.5
0.0 .25 .5 .75 1.0
Enable voltage

Figure B-1: C–V curve of the unit cell of the PVT bank.

Master of Science Thesis 87 Vamshi Krishna Chillara

88 Simulations

600.0

Q:594.72906

400.0
Quality factor

200.0

Q:48.621239

0.0

0.0 .25 .5 .75 1.0

Enable voltage

Figure B-2: Quality factor of the unit cell of the PVT bank.

2.0

1.9283622fA
1.75

1.5
Capacitance (fA)

1.25

1.0
dx: 630.625m
dy: 1.2142252fA
s: 1.9254315fA/
.75 714.13692aA

.5
0.0 .25 .5 .75 1.0
Enable voltage

Figure B-3: C–V curve of the unit cell of the acquisition bank.

Vamshi Krishna Chillara Master of Science Thesis

B-1 Simulations of the capacitor banks 89

2.5

2.0

2.0489991k

1.5
Quality factor (k)

1.0

.5 58.134898

0.0

-.5
0.0 .25 .5 .75 1.0
Enable voltage

Figure B-4: Quality factor of the unit cell of the acquisition bank.

870.0

867.58088aA

dx: 659.28571m
865.0 dy: 17.558512aA
s: 26.63263aA/
Capacitance (aA)

860.0

855.0

850.02236aA
850.0

0.0 .25 .5 .75 1.0

Enable voltage

Figure B-5: C–V curve of the LSB cell of the tracking bank.

Master of Science Thesis Vamshi Krishna Chillara

90 Simulations

3.0

2.8041433k
2.5
Quality factor (k)

2.0

1.5

1.0

.5

66.363873
0.0
0.0 .25 .5 .75 1.0
Enable voltage

Figure B-6: Quality factor of the LSB cell of the tracking bank.

925.0

900.0
903.23169aA

875.0
Capacitance (aA)

850.0

825.0

800.0
dx: 731.58088m
dy: 145.03374aA
s: 198.24703aA/
775.0 758.19795aA

750.0
0.0 .25 .5 .75 1.0
Enable voltage

Figure B-7: C–V curve of the MSB cell of the tracking bank.

Vamshi Krishna Chillara Master of Science Thesis

B-1 Simulations of the capacitor banks 91

2.5

2.082616k
2.0
Quality factor (k)

1.5

1.0

.5

74.384227
0.0

-.5
0.0 .25 .5 .75 1.0
Enable voltage

Figure B-8: Quality factor of the MSB cell of the tracking bank.

Master of Science Thesis Vamshi Krishna Chillara

92 Simulations

Vamshi Krishna Chillara Master of Science Thesis

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Vamshi Krishna Chillara Master of Science Thesis

 Glossary

List of Acronyms
ADC analog-to-digital converter

ADPLL all-digital phase-locked loop

BBPLL bang-bang phase-locked loop

CKR re-timed reference

CKV variable clock

CMOS complementary metal-oxide-semiconductor

CP-PLL charge-pump phase-locked loop

DCO digitally controlled oscillator

DIBL drain-induced barrier lowering

DTC digital-to-time converter

FCW frequency command word

FoM figure-of-merit

FPGA field programmable gate array

FSM finite state machine

IF intermediate frequency

LDO low-dropout

LNA low-noise amplifier

LO local oscillator

MICS medical implant communication service

OTW oscillator tuning word

Master of Science Thesis 99 Vamshi Krishna Chillara

100 Glossary

PCB printed circuit board

PGA programmable gain amplifier

PLL phase-locked loop

PVT process, voltage, and temperature

PA power amplifier

RF radio frequency

SNR signal-to-noise ratio

TDC time-to-digital converter

VCO voltage-controlled oscillator

VTC voltage transfer characteristic

WBAN wireless body area network

WPAN wireless personal area network

Vamshi Krishna Chillara Master of Science Thesis