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• Figure shows that both interconnect delay and gate delay decrease as we
scale down feature sizes but at different rates.
• Floorplanning allows us to predict this interconnect delay by estimating
interconnect length.

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Floorplanning Goals and Objectives
 The input to a floorplanning tool is a hierarchical
netlist that describes the interconnection of the blocks
(RAM, ROM, ALU, cache controller, and so on); the
logic cells (NAND, NOR, D flip-flop, and so on) within
the blocks; and the logic cell connectors (the terms
terminals , pins , or ports mean the same thing as
connectors ).
 The netlist is a logical description of the ASIC; the
floorplan is a physical description of an ASIC.
 Floorplanning is thus a mapping between the logical
description (the netlist) and the physical description
(the floorplan).
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  The goals of floorplanning are to:
 Arrange the blocks on a chip,
 Decide the location of the I/O pads
 Decide the location and number of the power
pads
 Decide the type of power distribution and
 Decide the location and type of clock
distribution.
• The objectives of floorplanning are to minimize the
chip area and minimize delay
• Measuring area is straightforward, but measuring delay
is more difficult.

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Measurement of Delay in Floorplanning
 Throughout the ASIC design process we need to predict
the performance of the final layout.
 In floorplanning we wish to predict the
interconnect delay before we complete any routing.
 For example imagine trying to predict how long it takes
to get from Russia to China without knowing where in
Russia we are or where our destination is in China.
Actually it is worse, because in floorplanning we may
move Russia or China.

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 To predict delay we need to know the parasitics associated with
interconnect: the interconnect capacitance (wiring capacitance
or routing capacitance) as well as the interconnect resistance.
 At the floorplanning stage we know only the fanout(FO) of a net
(the number of gates driven by a net) and the size of the block
that the net belongs to. But we cannot predict the resistance of
the various pieces of the interconnect path since we do not yet
know the shape of the interconnect for a net.
 So first we can estimate the total length of the interconnect and
thus estimate the total capacitance.
 And here we can estimate interconnect length by collecting
statistics from previously routed chips and analyzing the results.
 From these statistics we can create tables that predict the
interconnect capacitance as a function of net fanout and block size.
 A floorplanning tool can then use these predicted-capacitance
tables (also known as interconnect-load tables or wire-load tables )

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  Typically between 60 and 70 percent of nets have a FO = 1. The
distribution for a FO = 1 has a very long tail, stretching to
interconnects that run from corner to corner of the chip.
 The distribution for a FO = 1 often has two peaks, corresponding
to a distribution for close neighbors in subgroups within a block,
superimposed on a distribution corresponding to routing between
subgroups.
 We often see a twin-peaked distribution at the chip level also,
corresponding to separate distributions for interblock routing
(inside blocks) and intrablock routing (between blocks).
 The distributions for FO > 1 are more symmetrical and flatter than
for FO = 1.
 The wire-load tables can only contain one number, for example the
average net capacitance, for any one distribution. Many tools take
a worst-case approach and use the 80- or 90-percentile point
instead of the average. Thus a tool may use a predicted capacitance
for which we know 90 percent of the nets will have less than the
estimated capacitance.

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  We need to repeat the statistical analysis for blocks
with different sizes. For example, a net with a FO = 1 in
a 25 k-gate block will have a different (larger) average
length than if the net were in a 5 k-gate block.
 The statistics depend on the shape (aspect ratio) of the
block (usually the statistics are only calculated for
square blocks).
 The statistics will also depend on the type of netlist.
For example, the distributions will be different for a
netlist generated by setting a constraint for minimum
logic delay during synthesiswhich tends to generate
large numbers of two-input NAND gatesthan for
netlists generated using minimum-area constraints.
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 There are no standards for the wire-load tables
themselves, but there are some standards for their use
and for presenting the extracted loads.

• Table shows the estimated metal interconnect lengths, as

a function of die size and fanout, for a series of three-
level metal gate arrays. In this case the interconnect
capacitance isDeepika
10/19/2024 about 2 pFcm.
V B, Assistant Professor, GMIT, DVG 10
 • Figure shows that, because we do not decrease chip size as we scale
down feature size, the worst-case interconnect delay increases. One way
to measure the worst-case delay uses an interconnect that completely
crosses the chip, a coast-to-coast interconnect . In certain cases the
worst-case delay of a 0.25 mm process may be worse than a 0.35 mm
process, for example.

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 Floorplanning Tools
 Below figure 16.6(a) shows an initial random floorplan generated by a
floorplanning tool. Two of the blocks, A and C in this example, are
standard-cell areas (the chip shown in Figure 16.1 is one large standard-
cell area).
 These are flexible blocks (or variable blocks ) because, although their
total area is fixed, their shape (aspect ratio) and connector locations
may be adjusted during the placement step.
 The dimensions and connector locations of the other fixed blocks
(perhaps RAM, ROM, compiled cells, or megacells) can only be
modified when they are created.
 We may force logic cells to be in selected flexible blocks by seeding .
 We choose seed cells by name. For example, ram_control* would select
all logic cells whose names started with ram_control to be placed in
one flexible block.

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  The special symbol, usually ' * ', is a wildcard symbol . Seeding may be
hard or soft.
 A hard seed is fixed and not allowed to move during the remaining
floorplanning and placement steps.
 A soft seed is an initial suggestion only and can be altered if necessary by
the floorplanner.
 We may also use seed connectors within flexible blocks forcing certain
nets to appear in a specified order, or location at the boundary of a
flexible block.
 The floorplanner can complete an estimated placement to
determine the positions of connectors at the boundaries of the
flexible blocks.
 Figure 16.6 (b) illustrates a rat's nest display of the connections
between blocks. Connections are shown as bundles between the
centers of blocks or as flight lines between connectors.
 Figure 16.6 (c) and (d) show how we can move the blocks in a
floorplanning tool to minimize routing congestion .
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 We need to control the aspect ratio of our floorplan because we
have to fit our chip into the die cavity (a fixed-size hole, usually
square) inside a package.
 Figure 16.7 (a) and(b) show how we can rearrange our chip to
achieve a square aspect ratio.
 Figure 16.7 (c) also shows a congestion map , another form of
routability display. There is no standard measure of routability.
Generally the interconnect channels , (or wiring channels I shall
call them channels from now on) have a certain channel capacity ;
that is, they can handle only a fixed number of interconnects. One
measure of congestion is the difference between the number of
interconnects that we actually need, called the channel density ,
and the channel capacity.
 Another measure, shown in Figure 16.7 (d), uses the ratio of
channel density to the channel capacity. With practice, we can
create a good initial placement by floorplanning and a pictorial
display. This is one area where the human ability to recognize
patterns and spatial relations is currently superior to a computer
programs ability.
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 Channel Definition
 During the floorplanning step we assign the areas between blocks that are
to be used for interconnect. This process is known as channel definition or
channel allocation.
 The above Figure 16.8 shows a T-shaped junction between two rectangular
channels and illustrates why we must route the stem (vertical) of the T
before the bar.
 The general problem of choosing the order of rectangular channels to route
is channel ordering .
 The below Figure 16.9 shows a floorplan of a chip containing several blocks.
Suppose we cut along the block boundaries slicing the chip into two pieces
( Figure 16.9 a).
 Then suppose we can slice each of these pieces into two. If we can continue
in this fashion until all the blocks are separated, then we have a slicing
floorplan ( Figure 16.9 (b)).
 Figure 16.9 (c) shows how the sequence we use to slice the chip defines a
hierarchy of the blocks. Reversing the slicing order ensures that we route
the stems of all the channel T-junctions first.

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  The above Figure 16.10 shows a floorplan that is not a
slicing structure.
 We cannot cut the chip all the way across with a knife
without chopping a circuit block in two. This means we
cannot route any of the channels in this floorplan without
routing all of the other channels first. We say there is a
cyclic constraint in this floorplan.
 There are two solutions to this problem.
 One solution is to move the blocks until we obtain a slicing
floorplan.
 The other solution is to allow the use of L -shaped, rather
than rectangular, channels (or areas with fixed connectors
on all sidesa switch box ).
 We need an area-based router rather than a channel router
to route L -shaped regions or switch boxes.
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• The below Figure 16.11 (a) displays the floorplan of the ASIC design shown.
• We can remove the cyclic constraint by moving the blocks again, but this
increases the chip size.
• Figure 16.11 (b) shows an alternative solution. We merge the flexible standard
cell areas A and C. We can do this by selective flattening of the netlist.
Sometimes flattening can reduce the routing area because routing between
blocks is usually less efficient than routing inside the row-based blocks.
• Figure 16.11 (b) shows the channel definition and routing order for our chip.

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 I/O and Power Planning
 Every chip communicates with the outside world.
 Signals flow onto and off the chip and we need to supply
power.
 We need to consider the I/O and power constraints early in
the floorplanning process.
 A silicon chip or die (plural die, dies, or dice) is mounted
on a chip carrier inside a chip package .
 Connections are made by bonding the chip pads to fingers
on a metal lead frame that is part of the package.
 The metal lead-frame fingers connect to the package pins .
 A die consists of a logic core inside a pad ring .

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 Figure 16.12 (a) shows a pad-limited die and Figure 16.12 (b) shows a
core-limited die . On a pad-limited die we use tall, thin pad-limited
pads , which maximize the number of pads we can fit around the
outside of the chip. On a core-limited die we use short, wide core-
limited pads . Figure 16.12 (c) shows how we can use both types of
pad to change the aspect ratio of a die to be different from that of
the core.

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  Figure 16.13 (a) and (b) are magnified views of the
southeast corner of our example chip and show the
different types of I/O cells.
 Figure 16.13 (c) shows a stagger-bond arrangement using
two rows of I/O pads. In this case the design rules for bond
wires (the spacing and the angle at which the bond wires
leave the pads) become very important.
 Figure 16.13 (d) shows an area-bump bonding arrangement
(also known as flip-chip, solder-bump or C4, terms coined
by IBM who developed this technology [ Masleid, 1991])
used, for example, with ball-grid array ( BGA ) packages.
Even though the bonding pads are located in the center of
the chip, the I/O circuits are still often located at the edges
of the chip because of difficulties in power supply
distribution and integrating I/O circuits together with
logic in the center of the die.
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  Figure 16.15 shows two possible power distribution
schemes. The long direction of a rectangular channel is the
channel spine .
 Some automatic routers may require that metal lines
parallel to a channel spine use a preferred layer (either m1,
m2, or m3).
 Alternatively we say that a particular metal layer runs in a
preferred direction .
 Since we can have both horizontal and vertical channels,
 we may have the situation shown in Figure 16.15 , where we
have to decide whether to use a preferred layer or the
preferred direction for some channels. This may or may not
be handled automatically by the routing software.

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 Clock Planning
 Figure 16.16 (a) shows a clock spine (not to be confused
with a channel spine) routing scheme with all clock pins
driven directly from the clock driver. MGAs and FPGAs
often use this fish bone type of clock distribution scheme.
 Figure 16.16 (b) shows a clock spine for a cell-based ASIC.
 Figure 16.16 (c) shows the clock-driver cell, often part of a
special clock-pad cell.
 Figure 16.16 (d) illustrates clock skew and clock latency .
Since all clocked elements are driven from one net with a
clock spine, skew is caused by differing interconnect
lengths and loads. If the clock-driver delay is much larger
than the interconnect delays, a clock spine achieves
minimum skew but with long latency.
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  We can design a tree of clock buffers so that the taper
of each stage is e • 2.7 by using a fanout of three at each
node, as shown in Figure 16.17 (a) and (b).
 The clock tree , shown in Figure 16.17 (c), uses the
same number of stages as a clock spine, but with a
lower peak current for the inverter buffers.
 Figure 16.17 (c) illustrates that we now have another
problemwe need to balance the delays through the tree
carefully to minimize clock skew.

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 Placement
 After completing a floorplan we can begin placement
of the logic cells within the flexible blocks.
 Placement is much more suited to automation than
floorplanning.
 Thus we shall need measurement techniques and
algorithms.
 After we complete floorplanning and placement, we
can predict both intrablock and interblock
capacitances.
 This allows us to return to logic synthesis with more
accurate estimates of the capacitive loads that each
logic cell must drive.
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 Placement Goals and Objectives
 The goal of a placement tool is to arrange all the logic
cells within the flexible blocks on a chip. Ideally, the
objectives of the placement step are to
● Guarantee the router can complete the routing step
● Minimize all the critical net delays
● Make the chip as dense as possible
• We may also have the following additional objectives:
● Minimize power dissipation
● Minimize cross talk between signals

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 • Objectives such as these are difficult to define in a way
that can be solved with an algorithm and even harder
to actually meet.
 Current placement tools use more specific and
achievable criteria.
 The most commonly used placement objectives are
one or more of the following:
● Minimize the total estimated interconnect length
● Meet the timing requirements for critical nets
● Minimize the interconnect congestion

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