Chapter 1

SPRUH73H – October 2011 – Revised April 2013

Introduction

1.1 AM335x Family

1.1.1 Device Features

This architecture is configured with different sets of features in different devices. This technical reference
manual details all of the features available in current and future AM335x devices. Some features may not
be available or supported in your particular device. The features supported across different AM335x
devices are shown in Table 1-1. For more information on the different packages, refer to your device-
specific data manual.

Table 1-1. Device Features

Subsystem/ AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
Co-Processor/
Peripheral
ARM MPU Subsystem Y Y Y Y Y Y
Programmable Real-Time N N All features All features All features All features
Unit and Industrial excluding including excluding including
Communication Subsystem EtherCAT EtherCAT EtherCAT EtherCAT
(PRU-ICSS)
Graphics Accelerator N Y N N Y Y
(SGX)
Memory Map Y Y Y Y Y Y
Interrupts Y Y Y Y Y Y
Memory Subsystem Y Y Y Y Y Y
Power and Clock Y Y Y Y Y Y
Management (PRCM)
Control Module Y Y Y Y Y Y
Interconnects Y Y Y Y Y Y
Enhanced Direct Memory Y Y Y Y Y Y
Access (EDMA)
Touchscreen Controller Y Y Y Y Y Y
LCD Controller Y Y Y Y Y Y
Ethernet Subsystem ZCE: 1 port ZCE: 1 port No ZCE No ZCE No ZCE No ZCE
ZCZ: 2 ports ZCZ: 2 ports Available Available Available Available
ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports
Pulse-Width Modulation Y Y Y Y Y Y
Subsystem
Universal Serial Bus (USB) ZCE: 1 port ZCE: 1 port No ZCE No ZCE No ZCE No ZCE
ZCZ: 2 ports ZCZ: 2 ports Available Available Available Available
ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports ZCZ: 2 ports
Interprocessor Y Y Y Y Y Y
Communication
Multimedia Card (MMC) Y Y Y Y Y Y
Universal Asynchronous Y Y Y Y Y Y
Receiver/Transmitter
(UART)
DMTimer Y Y Y Y Y Y

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Table 1-1. Device Features (continued)

Subsystem/ AM3352 AM3354 AM3356 AM3357 AM3358 AM3359
Co-Processor/
Peripheral
DMTimer 1ms Y Y Y Y Y Y
RTCSS Y Y Y Y Y Y
Watchdog Y Y Y Y Y Y
I2C Y Y Y Y Y Y
Multichannel Audio Serial Y Y Y Y Y Y
Port (McASP)
Controller Area Network Y Y Y Y Y Y
(CAN)
Multichannel Serial Port Y Y Y Y Y Y
Interface (McSPI)
General Purpose Y Y Y Y Y Y
Input/Output (GPIO)
Initialization Y Y Y Y Y Y

1.1.2 Device Identification

Several registers help identify the type and available features of the device. Table 1-2 summarizes these
registers.

Table 1-2. Device_ID (Address 0x44E10600) Bit Field Descriptions

Bit Field Value Description
31-28 DEVREV Device revision
0000b - Silicon Revision 1.0
0001b - Silicon Revision 2.0
0010b - Silicon Revision 2.1
See device errata for detailed information on functionality in each device revision.
Reset value is revision-dependent.
27-12 PARTNUM Device part number
0xB944
11-1 MFGR Manufacturer's ID
0x017
0 Reserved Read always as 0
0x0

1.1.3 Feature Identification

The AM335x has many different feature sets available. The DEV_FEATURE register in the control module
identifies which features are available in each device in the AM335x family. See Table 1-3, dev_feature
Register, in the control module chapter for more information on the bits in the DEV_FEATURE register.

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Table 1-3. DEV_FEATURE (Address 0x44E10604) Register Values

Bit 3 3 29 28 27 26 25 24 23 22 21 20 19 18 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register
1 0 7 6 Value
R S I R D C I
e G C e C P C
s X S s A S S
Bit e S e N W S
Reserved Reserved Reserved
Definition r _ r
v F v
e E e
d A d
AM3352 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0x00FC0382
AM3354 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0x20FC0382
AM3356 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x00FD0383
AM3357 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x00FF0383
AM3358 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x20FD0383
AM3359 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0x20FF0383

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www.ti.com Silicon Revision Functional Differences and Enhancements

1.2 Silicon Revision Functional Differences and Enhancements

This section describes the differences in functionality among different silicon revisions of AM335x.
Enhancements introduced in silicon revisions are also described. For a description of silicon bugs that
were fixed in later revisions of the device, see AM335x ARM Cortex-A8 Microprocessors (MPUs) Silicon
Errata (literature number SPRZ360). Errata items that were fixed may or may not show up in this section.

1.2.1 Added RTC Alarm Wakeup for DeepSleep Modes

See Section 8.1.4.5, Wakeup Sources/Events.
PG1.0: RTC alarm will not wake up device from DeepSleep0.
PG2.x: RTC alarm was added as a wake-up source from DeepSleep modes.

1.2.2 Changed BOOTP Identifier

See Section 26.1.8.4.2, BOOTP (RFC 951) and Errata Advisory 1.0.8.
PG1.0: BOOTP Identifier string is "DM814x ROM v1.0".
PG2.x: BOOTP Identifier string is "AM335x ROM".

1.2.3 Changed Product String in USB Descriptor

See Section 26.1.8.6.1.2, Enumeration Descriptors.
PG1.0: Product string in USB descriptor is "Subarctic".
PG2.x: Product string in USB descriptor is "AM335x USB".

1.2.4 Added DPLL Power Switch Control and Status Registers

See Section 9.3.14, dpll_pwr_sw_status Register, and Section 9.3.76, dpll_pwr_sw_ctrl Register.
PG1.0: DPLL Power Switch Control and Status registers do not exist.
PG2.x: Added DPLL Power Switch Control and DPLL Power Switch Status registers in the Control Module
to facilitate power optimization.

1.2.5 Added Control for CORE SRAM LDO Retention Mode

See newly added SMA2 register, Section 9.3.78.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.VSLDO_CORE_AUTO_RAMP_EN.

1.2.6 Added Pin Mux Options for GPMC_A9 to Facilitate RMII Pin Muxing
See newly added SMA2 register, Section 9.3.78.
PG1.0: SMA2 register does not exist.
PG2.x: Added SMA2.RMII2_CRS_DV_MODE_SEL.

1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)

See Section 6.3, ARM Cortex-A8 Interrupts and Errata Advisory 1.0.6.
PG1.0: nNMI input signal is active high.
PG2.x: nNMI input signal is active low.

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1.2.8 Changed Default Value of ncin and pcin Bits in vtp_ctrl Register
See Section 9.3.54, vtp_ctrl Register.
PG1.0: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 0.
PG2.x: VTP_CTRL.NCIN and VTP_CTRL.PCIN reset value is 1.

1.2.9 Changed Default Value of RGMII Mode to No Internal Delay

See Section 9.3.31, gmii_sel Register and Errata Advisory 1.0.10.
PG1.0: RGMII1_IDMODE And RGMII2_IDMODE reset value is 0.
PG2.x: RGMII1_IDMODE And RGMII2_IDMODE reset value is 1.

1.2.10 Changed Default Value of RMII Clock Source

See Section 9.3.31, gmii_sel Register and Errata Advisory 1.0.18.
PG1.0: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 0.
PG2.x: RMII1_IO_CLK_EN and RMII2_IO_CLK_EN reset value is 1.

1.2.11 Changed the Method of Determining Speed of Operation During EMAC Boot
See Section 26.1.8.4, EMAC Boot Procedure and Errata Advisory 1.0.7.
PG1.0: Link speed is determined by CONTROL register bit 6 in the external ethernet PHY. Note that some
PHYs may not update this bit, as it is not necessary as described in the 802.3 specification.
PG2.x: Link speed is determined by reading the Auto-Negotiation Advertisement and Auto-Negotiation
Link Partner Base Page Ability registers in the external ethernet PHY.

1.2.12 Added EFUSE_SMA Register for Help Identifying Different Device Variants
See Section 9.3.50, efuse_sma Register.
PG1.0: EFUSE_SMA register value is not applicable. Value is always 0.
PG2.x: Added EFUSE_SMA description to distinguish package type and maximum ARM frequency of the
device.

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 Chapter 2
SPRUH73H – October 2011 – Revised April 2013

Memory Map

This sections describes the memory map for the device.

2.1 ARM Cortex-A8 Memory Map

Table 2-1. L3 Memory Map

Block Name Start_address (hex) End_address (hex) Size Description
GPMC 0x0000_0000 (1) 0x1FFF_FFFF 512MB 8-/16-bit External Memory
(External Memory) (Ex/R/W) (2)
Reserved 0x2000_0000 0x3FFF_FFFF 512MB Reserved
Boot ROM 0x4000_0000 0x4001_FFFF 128KB
0x4002_0000 0x4002_BFFF 48KB 32-bit Ex/R (2) – Public
Reserved 0x4002_C000 0x400F_FFFF 848KB Reserved
Reserved 0x4010_0000 0x401F_FFFF 1MB Reserved
Reserved 0x4020_0000 0x402E_FFFF 960KB Reserved
Reserved 0x402F_0000 0x402F_03FF 64KB Reserved
SRAM internal 0x402F_0400 0x402F_FFFF 32-bit Ex/R/W (2)
L3 OCMC0 0x4030_0000 0x4030_FFFF 64KB 32-bit Ex/R/W (2) OCMC SRAM
Reserved 0x4031_0000 0x403F_FFFF 960KB Reserved
Reserved 0x4040_0000 0x4041_FFFF 128KB Reserved
Reserved 0x4042_0000 0x404F_FFFF 896KB Reserved
Reserved 0x4050_0000 0x405F_FFFF 1MB Reserved
Reserved 0x4060_0000 0x407F_FFFF 2MB Reserved
Reserved 0x4080_0000 0x4083_FFFF 256KB Reserved
Reserved 0x4084_0000 0x40DF_FFFF 5888KB Reserved
Reserved 0x40E0_0000 0x40E0_7FFF 32KB Reserved
Reserved 0x40E0_8000 0x40EF_FFFF 992KB Reserved
Reserved 0x40F0_0000 0x40F0_7FFF 32KB Reserved
Reserved 0x40F0_8000 0x40FF_FFFF 992KB Reserved
Reserved 0x4100_0000 0x41FF_FFFF 16MB Reserved
Reserved 0x4200_0000 0x43FF_FFFF 32MB Reserved
L3F CFG Regs 0x4400_0000 0x443F_FFFF 4MB L3Fast configuration registers
Reserved 0x4440_0000 0x447F_FFFF 4MB Reserved
L3S CFG Regs 0x4480_0000 0x44BF_FFFF 4MB L3Slow configuration registers
L4_WKUP 0x44C0_0000 0x44FF_FFFF 4MB L4_WKUP
Reserved 0x4500_0000 0x45FF_FFFF 16MB Reserved
McASP0 Data 0x4600_0000 0x463F_FFFF 4MB McASP0 Data Registers
McASP1 Data 0x4640_0000 0x467F_FFFF 4MB McASP1 Data Registers
Reserved 0x4680_0000 0x46FF_FFFF 8MB Reserved
Reserved 0x4700_0000 0x473F_FFFF 4MB Reserved

(1)
The first 1MB of address space 0x0-0xFFFFF is inaccessible externally.
(2)
Ex/R/W – Execute/Read/Write.

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Table 2-1. L3 Memory Map (continued)

Block Name Start_address (hex) End_address (hex) Size Description
USBSS 0x4740_0000 0x4740_0FFF 20KB USB Subsystem Registers
USB0 0x4740_1000 0x4740_12FF USB0 Controller Registers
USB0_PHY 0x4740_1300 0x4740_13FF USB0 PHY Registers
USB0 Core 0x4740_1400 0x4740_17FF USB0 Core Registers
USB1 0x4740_1800 0x4740_1AFF USB1 Controller Registers
USB1_PHY 0x4740_1B00 0x4740_1BFF USB1 PHY Registers
USB1 Core 0x4740_1C00 0x4740_1FFF USB1 Core Registers
USB CPPI DMA 0x4740_2000 0x4740_2FFF USB CPPI DMA Controller
Controller Registers
USB CPPI DMA 0x4740_3000 0x4740_3FFF USB CPPI DMA Scheduler
Scheduler Registers
USB Queue Manager 0x4740_4000 0x4740_4FFF USB Queue Manager Registers
Reserved 0x4740_5000 0x477F_FFFF 4MB-20KB Reserved
Reserved 0x4780_0000 0x4780_FFFF 64KB Reserved
MMCHS2 0x4781_0000 0x4781_FFFF 64KB MMCHS2
Reserved 0x4782_0000 0x47BF_FFFF 4MB-128KB Reserved
Reserved 0x47C0_0000 0x47FF_FFFF 4MB Reserved
L4_PER 0x4800_0000 0x48FF_FFFF 16MB L4 Peripheral (see L4_PER table)
TPCC (EDMA3CC) 0x4900_0000 0x490F_FFFF 1MB EDMA3 Channel Controller
Registers
Reserved 0x4910_0000 0x497F_FFFF 7MB Reserved
TPTC0 (EDMA3TC0) 0x4980_0000 0x498F_FFFF 1MB EDMA3 Transfer Controller 0
Registers
TPTC1 (EDMA3TC1) 0x4990_0000 0x499F_FFFF 1MB EDMA3 Transfer Controller 1
Registers
TPTC2 (EDMA3TC2) 0x49A0_0000 0x49AF_FFFF 1MB EDMA3 Transfer Controller 2
Registers
Reserved 0x49B0_0000 0x49BF_FFFF 1MB Reserved
Reserved 0x49C0_0000 0x49FF_FFFF 4MB Reserved
L4_FAST 0x4A00_0000 0x4AFF_FFFF 16MB L4_FAST
DebugSS 0x4B00_0000 0x4BFF_FFFF 16MB Debug Subsystem region
EMIF0 0x4C00_0000 0x4CFF_FFFF 16MB EMIF0 Configuration registers
Reserved 0x4D00_0000 0x4DFF_FFFF 16MB Reserved
Reserved 0x4E00_0000 0x4FFF_FFFF 32MB Reserved
GPMC 0x5000_0000 0x50FF_FFFF 16MB GPMC Configuration registers
Reserved 0x5100_0000 0x52FF_FFFF 32MB Reserved
Reserved 0x5300_0000 0x530F_FFFF 1MB Reserved
0x5310_0000 0x531F_FFFF 1MB Reserved
Reserved 0x5320_0000 0x533F_FFFF 2MB Reserved
Reserved 0x5340_0000 0x534F_FFFF 1MB Reserved
0x5350_0000 0x535F_FFFF 1MB Reserved
Reserved 0x5360_0000 0x54BF_FFFF 22MB Reserved
ADC_TSC DMA 0x54C0_0000 0x54FF_FFFF 4MB ADC_TSC DMA Port
Reserved 0x5500_0000 0x55FF_FFFF 16MB Reserved
SGX530 0x5600_0000 0x56FF_FFFF 16MB SGX530 Slave Port
Reserved 0x5700_0000 0x57FF_FFFF 16MB Reserved
Reserved 0x5800_0000 0x58FF_FFFF 16MB Reserved
Reserved 0x5900_0000 0x59FF_FFFF 16MB Reserved
Reserved 0x5A00_0000 0x5AFF_FFFF 16MB Reserved

156 Memory Map SPRUH73H – October 2011 – Revised April 2013

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Table 2-1. L3 Memory Map (continued)

Block Name Start_address (hex) End_address (hex) Size Description
Reserved 0x5B00_0000 0x5BFF_FFFF 16MB Reserved
Reserved 0x5C00_0000 0x5DFF_FFFF 32MB Reserved
Reserved 0x5E00_0000 0x5FFF_FFFF 32MB Reserved
Reserved 0x6000_0000 0x7FFF_FFFF 512MB Reserved
EMIF0 SDRAM 0x8000_0000 0xBFFF_FFFF 1GB 8-/16-bit External Memory
(Ex/R/W) (3)
Reserved 0xC000_0000 0xFFFF_FFFF 1GB Reserved
(3)
Ex/R/W – Execute/Read/Write.

Table 2-2. L4_WKUP Peripheral Memory Map

Region Name Start Address (hex) End Address (hex) Size Description
L4_WKUP configuration 0x44C0_0000 0x44C0_07FF 2KB Address/Protection (AP)
0x44C0_0800 0x44C0_0FFF 2KB Link Agent (LA)
0x44C0_1000 0x44C0_13FF 1KB Initiator Port (IP0)
0x44C0_1400 0x44C0_17FF 1KB Initiator Port (IP1)
Reserved 0x44C0_1800 0x44C0_1FFF 2KB Reserved (IP2 – IP3)
Reserved 0x44C0_2000 0x44CF_FFFF 1MB-8KB Reserved
Reserved 0x44D0_0000 0x44D0_3FFF 16KB Reserved
0x44D0_4000 0x44D0_4FFF 4KB Reserved
Reserved 0x44D0_5000 0x44D7_FFFF 492KB Reserved
Reserved 0x44D8_0000 0x44D8_1FFF 8KB Reserved
0x44D8_2000 0x44D8_2FFF 4KB Reserved
Reserved 0x44D8_3000 0x44DF_FFFF 500KB Reserved
CM_PER 0x44E0_0000 0x44E0_3FFF 1KB Clock Module Peripheral Registers
CM_WKUP 0x44E0_0400 0x44E0_04FF 256 Bytes Clock Module Wakeup Registers
CM_DPLL 0x44E0_0500 0x44E0_05FF 256 Bytes Clock Module PLL Registers
CM_MPU 0x44E0_0600 0x44E0_06FF 256 Bytes Clock Module MPU Registers
CM_DEVICE 0x44E0_0700 0x44E0_07FF 256 Bytes Clock Module Device Registers
CM_RTC 0x44E0_0800 0x44E0_08FF 256 Bytes Clock Module RTC Registers
CM_GFX 0x44E0_0900 0x44E0_09FF 256 Bytes Clock Module Graphics Controller
Registers
CM_CEFUSE 0x44E0_0A00 0x44E0_0AFF 256 Bytes Clock Module Efuse Registers
PRM_IRQ 0x44E0_0B00 0x44E0_0BFF 256 Bytes Power Reset Module Interrupt
Registers
PRM_PER 0x44E0_0C00 0x44E0_0CFF 256 Bytes Power Reset Module Peripheral
Registers
PRM_WKUP 0x44E0_0D00 0x44E0_0DFF 256 Bytes Power Reset Module Wakeup
Registers
PRM_MPU 0x44E0_0E00 0x44E0_0EFF 256 Bytes Power Reset Module MPU
Registers
PRM_DEVICE 0x44E0_0F00 0x44E0_0FFF 256 Bytes Power Reset Module Device
Registers
PRM_RTC 0x44E0_1000 0x44E0_10FF 256 Bytes Power Reset Module RTC
Registers
PRM_GFX 0x44E0_1100 0x44E0_11FF 256 Bytes Power Reset Module Graphics
Controller Registers
PRM_CEFUSE 0x44E0_1200 0x44E0_12FF 256 Bytes Power Reset Module Efuse
Registers
Reserved 0x44E0_3000 0x44E0_3FFF 4KB Reserved
0x44E0_4000 0x44E0_4FFF 4KB Reserved

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Table 2-2. L4_WKUP Peripheral Memory Map (continued)

Region Name Start Address (hex) End Address (hex) Size Description
DMTIMER0 0x44E0_5000 0x44E0_5FFF 4KB DMTimer0 Registers
0x44E0_6000 0x44E0_6FFF 4KB Reserved
GPIO0 0x44E0_7000 0x44E0_7FFF 4KB GPIO Registers
0x44E0_8000 0x44E0_8FFF 4KB Reserved
UART0 0x44E0_9000 0x44E0_9FFF 4KB UART Registers
0x44E0_A000 0x44E0_AFFF 4KB Reserved
I2C0 0x44E0_B000 0x44E0_BFFF 4KB I2C Registers
0x44E0_C000 0x44E0_CFFF 4KB Reserved
ADC_TSC 0x44E0_D000 0x44E0_EFFF 8KB ADC_TSC Registers
0x44E0_F000 0x44E0_FFFF 4KB Reserved
Control Module 0x44E1_0000 0x44E1_1FFF 128KB Control Module Registers
DDR2/3/mDDR PHY 0x44E1_2000 0x44E1_23FF DDR2/3/mDDR PHY Registers
Reserved 0x44E1_2400 0x44E3_0FFF 4KB Reserved
DMTIMER1_1MS 0x44E3_1000 0x44E3_1FFF 4KB DMTimer1 1ms Registers
(Accurate 1ms timer)
0x44E3_2000 0x44E3_2FFF 4KB Reserved
Reserved 0x44E3_3000 0x44E3_3FFF 4KB Reserved
0x44E3_4000 0x44E3_4FFF 4KB Reserved
WDT1 0x44E3_5000 0x44E3_5FFF 4KB Watchdog Timer Registers
0x44E3_6000 0x44E3_6FFF 4KB Reserved
SmartReflex0 0x44E3_7000 0x44E3_7FFF 4KB L3 Registers
0x44E3_8000 0x44E3_8FFF 4KB Reserved
SmartReflex1 0x44E3_9000 0x44E3_9FFF 4KB L3 Registers
0x44E3_A000 0x44E3_AFFF 4KB Reserved
Reserved 0x44E3_B000 0x44E3_DFFF 12KB Reserved
RTCSS 0x44E3_E000 0x44E3_EFFF 4KB RTC Registers
0x44E3_F000 0x44E3_FFFF 4KB Reserved
DebugSS 0x44E4_0000 0x44E7_FFFF 256KB Debug Registers
Instrumentation
HWMaster1 Port
0x44E8_0000 0x44E8_0FFF 4KB Reserved
Reserved 0x44E8_1000 0x44EF_FFFF 508KB Reserved
Reserved 0x44F0_0000 0x44FF_FFFF 1MB Reserved

Table 2-3. L4_PER Peripheral Memory Map

Device Name Start_address (hex) End_address (hex) Size Description
0x4800_0000 0x4800_07FF 2KB Reserved
0x4800_0800 0x4800_0FFF 2KB Reserved
Reserved 0x4800_1000 0x4800_13FF 1KB Reserved
0x4800_1400 0x4800_17FF 1KB Reserved
0x4800_1800 0x4800_1BFF 1KB Reserved
0x4800_1C00 0x4800_1FFF 1KB Reserved
Reserved 0x4800_2000 0x4800_3FFF 8KB Reserved
Reserved 0x4800_4000 0x4800_7FFF 16KB Reserved
Reserved 0x4800_8000 0x4800_8FFF 4KB Reserved
0x4800_9000 0x4800_9FFF 4KB Reserved
Reserved 0x4800_A000 0x4800_FFFF 24KB Reserved
Reserved 0x4801_0000 0x4801_0FFF 4KB Reserved

158 Memory Map SPRUH73H – October 2011 – Revised April 2013

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Table 2-3. L4_PER Peripheral Memory Map (continued)

Device Name Start_address (hex) End_address (hex) Size Description
0x4801_1000 0x4801_1FFF 4KB Reserved
Reserved 0x4801_2000 0x4801_3FFF 8KB Reserved
Reserved 0x4801_4000 0x4801_FFFF 48KB Reserved
Reserved 0x4802_0000 0x4802_0FFF 4KB Reserved
0x4802_1000 0x4802_1FFF 4KB Reserved
UART1 0x4802_2000 0x4802_2FFF 4KB UART1 Registers
0x4802_3000 0x4802_3FFF 4KB Reserved
UART2 0x4802_4000 0x4802_4FFF 4KB UART2 Registers
0x4802_5000 0x4802_5FFF 4KB Reserved
Reserved 0x4802_6000 0x4802_7FFF 8KB Reserved
Reserved 0x4802_8000 0x4802_8FFF 4KB Reserved
0x4802_9000 0x4802_9FFF 4KB Reserved
I2C1 0x4802_A000 0x4802_AFFF 4KB I2C1 Registers
0x4802_B000 0x4802_BFFF 4KB Reserved
Reserved 0x4802_C000 0x4802_CFFF 4KB Reserved
0x4802_D000 0x4802_DFFF 4KB Reserved
Reserved 0x4802_E000 0x4802_EFFF 4KB Reserved
0x4802_F000 0x4802_FFFF 4KB Reserved
McSPI0 0x4803_0000 0x4803_0FFF 4KB McSPI0 Registers
0x4803_1000 0x4803_1FFF 4KB Reserved
Reserved 0x4803_2000 0x4803_2FFF 4KB Reserved
0x4803_3000 0x4803_3FFF 4KB Reserved
Reserved 0x4803_4000 0x4803_4FFF 4KB Reserved
0x4803_5000 0x4803_5FFF 4KB Reserved
Reserved 0x4803_6000 0x4803_6FFF 4KB Reserved
0x4803_7000 0x4803_7FFF 4KB Reserved
McASP0 CFG 0x4803_8000 0x4803_9FFF 8KB McASP0 CFG Registers
0x4803_A000 0x4803_AFFF 4KB Reserved
Reserved 0x4803_B000 0x4803_BFFF 4KB Reserved
McASP1 CFG 0x4803_C000 0x4803_DFFF 8KB McASP1 CFG Registers
0x4803_E000 0x4803_EFFF 4KB Reserved
Reserved 0x4803_F000 0x4803_FFFF 4KB Reserved
DMTIMER2 0x4804_0000 0x4804_0FFF 4KB DMTimer2 Registers
0x4804_1000 0x4804_1FFF 4KB Reserved
DMTIMER3 0x4804_2000 0x4804_2FFF 4KB DMTimer3 Registers
0x4804_3000 0x4804_3FFF 4KB Reserved
DMTIMER4 0x4804_4000 0x4804_4FFF 4KB DMTimer4 Registers
0x4804_5000 0x4804_5FFF 4KB Reserved
DMTIMER5 0x4804_6000 0x4804_6FFF 4KB DMTimer5 Registers
0x4804_7000 0x4804_7FFF 4KB Reserved
DMTIMER6 0x4804_8000 0x4804_8FFF 4KB DMTimer6 Registers
0x4804_9000 0x4804_9FFF 4KB L4 Interconnect
DMTIMER7 0x4804_A000 0x4804_AFFF 4KB DMTimer7 Registers
0x4804_B000 0x4804_BFFF 4KB Reserved
GPIO1 0x4804_C000 0x4804_CFFF 4KB GPIO1 Registers
0x4804_D000 0x4804_DFFF 4KB Reserved
Reserved 0x4804_E000 0x4804_FFFF 8KB Reserved

SPRUH73H – October 2011 – Revised April 2013 Memory Map 159

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Table 2-3. L4_PER Peripheral Memory Map (continued)

Device Name Start_address (hex) End_address (hex) Size Description
Reserved 0x4805_0000 0x4805_FFFF 64KB Reserved
MMCHS0 0x4806_0000 0x4806_0FFF 4KB MMCHS0 Registers
0x4806_1000 0x4806_1FFF 4KB Reserved
Reserved 0x4806_2000 0x4807_FFFF 120KB Reserved
ELM 0x4808_0000 0x4808_FFFF 64KB ELM Registers
0x4809_0000 0x4809_0FFF 4KB Reserved
Reserved 0x4809_1000 0x4809_FFFF 60KB Reserved
Reserved 0x480A_0000 0x480A_FFFF 64KB Reserved
0x480B_0000 0x480B_0FFF 4KB Reserved
Reserved 0x480B_1000 0x480B_FFFF 60KB Reserved
Reserved 0x480C_0000 0x480C_0FFF 4KB Reserved
0x480C_1000 0x480C_1FFF 4KB Reserved
Reserved 0x480C_2000 0x480C_2FFF 4KB Reserved
0x480C_3000 0x480C_3FFF 4KB Reserved
Reserved 0x480C_4000 0x480C_7FFF 16KB Reserved
Mailbox 0 0x480C_8000 0x480C_8FFF 4KB Mailbox Registers
0x480C_9000 0x480C_9FFF 4KB Reserved
Spinlock 0x480C_A000 0x480C_AFFF 4KB Spinlock Registers
0x480C_B000 0x480C_BFFF 4KB Reserved
Reserved 0x480C_C000 0x480F_FFFF 208KB Reserved
Reserved 0x4810_0000 0x4811_FFFF 128KB Reserved
0x4812_0000 0x4812_0FFF 4KB Reserved
Reserved 0x4812_1000 0x4812_1FFF 4KB Reserved
Reserved 0x4812_2000 0x4812_2FFF 4KB Reserved
0x4812_3000 0x4812_3FFF 4KB Reserved
Reserved 0x4812_4000 0x4813_FFFF 112KB Reserved
Reserved 0x4814_0000 0x4815_FFFF 128KB Reserved
0x4816_0000 0x4816_0FFF 4K Reserved
Reserved 0x4816_1000 0x4817_FFFF 124KB Reserved
Reserved 0x4818_0000 0x4818_2FFF 12KB Reserved
0x4818_3000 0x4818_3FFF 4KB Reserved
Reserved 0x4818_4000 0x4818_7FFF 16KB Reserved
Reserved 0x4818_8000 0x4818_8FFF 4KB Reserved
0x4818_9000 0x4818_9FFF 4KB Reserved
Reserved 0x4818_A000 0x4818_AFFF 4KB Reserved
0x4818_B000 0x4818_BFFF 4KB Reserved
OCP Watchpoint 0x4818_C000 0x4818_CFFF 4KB OCP Watchpoint Registers
0x4818_D000 0x4818_DFFF 4KB Reserved
Reserved 0x4818_E000 0x4818_EFFF 4KB Reserved
0x4818_F000 0x4818_FFFF 4KB Reserved
Reserved 0x4819_0000 0x4819_0FFF 4KB Reserved
0x4819_1000 0x4819_1FFF 4KB Reserved
Reserved 0x4819_2000 0x4819_2FFF 4KB Reserved
0x4819_3000 0x4819_3FFF 4KB Reserved
Reserved 0x4819_4000 0x4819_BFFF 32KB Reserved
I2C2 0x4819_C000 0x4819_CFFF 4KB I2C2 Registers
0x4819_D000 0x4819_DFFF 4KB Reserved

160 Memory Map SPRUH73H – October 2011 – Revised April 2013

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