CAT24WC01/02/04/08/16

1K/2K/4K/8K/16K-Bit Serial E2PROM

FEATURES ■ Self-Timed Write Cycle with Auto-Clear
2
■ 400 KHZ I C Bus Compatible* ■ 1,000,000 Program/Erase Cycles
■ 1.8 to 6.0Volt Operation ■ 100 Year Data Retention
■ Low Power CMOS Technology ■ 8-pin DIP, 8-pin SOIC or 8 pin TSSOP
■ Write Protect Feature ■ Commercial, Industrial and Automotive
— Entire Array Protected When WP at VIH Temperature Ranges
■ Page Write Buffer
DESCRIPTION
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K- 08/16 feature a 16-byte page write buffer. The device
bit Serial CMOS E2PROM internally organized as 128/ operates via the I2C bus serial interface, has a special
256/512/1024/2048 words of 8 bits each. Catalyst’s write protection feature, and is available in 8-pin DIP, 8-
advanced CMOS technology substantially reduces de- pin SOIC or 8-pin TSSOP.
vice power requirements. The the CAT24WC01/02/04/

PIN CONFIGURATION BLOCK DIAGRAM

DIP Package (P) SOIC Package (J)
EXTERNAL LOAD
A0 1 8 VCC A0 1 8 VCC
DOUT SENSE AMPS
A1 2 7 WP A1 2 7 WP SHIFT REGISTERS
3 6 3 6 ACK
A2 SCL A2 SCL
VSS 4 5 SDA VSS 4 5 SDA VCC

VSS WORD ADDRESS COLUMN

5020 FHD F01 BUFFERS DECODERS

TSSOP Package (U)

(* Available for 24WC01 and 24WC02 only) SDA START/STOP
LOGIC
A0 1 8 VCC
A1 2 7 WP
A2 3 6 SCL XDEC E2PROM
VSS 4 5 SDA CONTROL
WP LOGIC

PIN FUNCTIONS
Pin Name Function DATA IN STORAGE

A0, A1, A2 Device Address Inputs

SDA Serial Data/Address HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect SCL STATE COUNTERS

VCC +1.8V to +6.0V Power Supply A0 SLAVE

A1 ADDRESS
VSS Ground A2 COMPARATORS

24WCXX F03
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

© 1999 by Catalyst Semiconductor, Inc. Doc. No. 25051-00 3/98 S-1

Characteristics subject to change without notice 1
CAT24WC01/02/04/08/16

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
Voltage on Any Pin with
the device at these or any other conditions outside of those
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
listed in the operational sections of this specification is not
VCC with Respect to Ground ............... –2.0V to +7.0V implied. Exposure to any absolute maximum rating for
Package Power Dissipation extended periods may affect device performance and
Capability (Ta = 25°C) .................................. 1.0W reliability.
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
NEND(3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC Power Supply Current 3 mA fSCL = 100 KHz
ISB (5) Standby Current (VCC = 5.0V) 0 µA VIN = GND or VCC
ILI Input Leakage Current 10 µA VIN = GND to VCC
ILO Output Leakage Current 10 µA VOUT = GND to VCC
VIL Input Low Voltage –1 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage (VCC = 3.0V) 0.4 V IOL = 3 mA
VOL2 Output Low Voltage (VCC = 1.8V) 0.5 V IOL = 1.5 mA

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions
CI/O(3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN(3) Input Capacitance (A0, A1, A2, SCL, WP) 6 pF VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB) = 0µA (<900nA).

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 CAT24WC01/02/04/08/16

A.C. CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.

Read & Write Cycle Limits

Symbol Parameter 1.8V, 2.5V 4.5V-5.5V

Min. Max. Min. Max. Units
FSCL Clock Frequency 100 400 kHz
TI(1) Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
tAA SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
tHD:STA Start Condition Hold Time 4 0.6 µs
tLOW Clock Low Period 4.7 1.2 µs
tHIGH Clock High Period 4 0.6 µs
tSU:STA Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
tHD:DAT Data In Hold Time 0 0 ns
tSU:DAT Data In Setup Time 50 50 ns
tR(1) SDA and SCL Rise Time 1 0.3 µs
tF (1) SDA and SCL Fall Time 300 300 ns
tSU:STO Stop Condition Setup Time 4 0.6 µs
tDH Data Out Hold Time 100 100 ns

Power-Up Timing(1)(2)
Symbol Parameter Max. Units
tPUR Power-up to Read Operation 1 ms
tPUW Power-up to Write Operation 1 ms

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units
tWR Write Cycle Time 10 ms

The write cycle time is the time from a valid stop interface circuits are disabled, SDA is allowed to remain
condition of a write sequence to the end of the internal high, and the device does not respond to its slave
program/erase cycle. During the write cycle, the bus address.

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

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CAT24WC01/02/04/08/16

FUNCTIONAL DESCRIPTION PIN DESCRIPTIONS

The CAT24WC01/02/04/08/16 supports the I2C Bus SCL: Serial Clock
data transmission protocol. This Inter-Integrated Circuit The CAT24WC01/02/04/08/16 serial clock input pin is
Bus protocol defines any device that sends data to the used to clock all data transfers into or out of the device.
bus to be a transmitter and any device receiving data to This is an input pin.
be a receiver. Data transfer is controlled by the Master
device which generates the serial clock and all START SDA: Serial Data/Address
and STOP conditions for bus access. The CAT24WC01/ The CAT24WC01/02/04/08/16 bidirectional serial data/
02/04/08/16 operates as a Slave device. Both the Mas- address pin is used to transfer data into and out of the
ter and Slave devices can operate as either transmitter device. The SDA pin is an open drain output and can be
or receiver, but the Master device controls which mode wire-ORed with other open drain or open collector
is activated. A maximum of 8 devices (24WC01 and outputs.
24WC02), 4 devices (24WC04), 2 devices (24WC08)
A0, A1, A2: Device Address Inputs
and 1 device (24WC16) may be connected to the bus as
These inputs set device address when cascading mul-
determined by the device address inputs A0, A1, and A2.
tiple devices. When these pins are left floating the
default values are zeros (except for the 24WC01).

A maximum of eight devices can be cascaded when

Figure 1. Bus Timing tF tHIGH tR

tLOW tLOW

SCL

tSU:STA tHD:DAT
tHD:STA tSU:DAT tSU:STO

SDA IN
tBUF
tAA tDH

SDA OUT

5020 FHD F03

Figure 2. Write Cycle Timing

SCL

SDA 8TH BIT ACK

BYTE n
tWR

STOP START ADDRESS

CONDITION CONDITION 5020 FHD F04

Figure 3. Start/Stop Timing

SDA

SCL

5020 FHD F05

START BIT STOP BIT

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 CAT24WC01/02/04/08/16

using either 24WC01 or 24WC02 device. All three (2) During a data transfer, the data line must remain
address pins are used for these densities. If only one stable whenever the clock line is high. Any changes
24WC02 is addressed on the bus, all three address pins in the data line while the clock line is high will be
(A0, A1and A2) can be left floating or connected to VSS. interpreted as a START or STOP condition.
If only one 24WC01 is addressed on the bus, all three
address pins (A0, A1and A2) must be connected to VSS. START Condition
The START Condition precedes all commands to the
A total of four devices can be addressed on a single bus device, and is defined as a HIGH to LOW transition of
when using 24WC04 device. Only A1 and A2 address SDA when SCL is HIGH. The CAT24WC01/02/04/08/16
pins are used with this device. The A0 address pin is a monitor the SDA and SCL lines and will not respond until
no connect pin and can be tied to VSS or left floating. If this condition is met.
only one 24WC04 is being addressed on the bus, the
address pins (A1 and A2) can be left floating or con- STOP Condition
nected to VSS. A LOW to HIGH transition of SDA when SCL is HIGH
Only two devices can be cascaded when using 24WC08. determines the STOP condition. All operations must end
The only address pin used with this device is A2. The A0 with a STOP condition.
and A1 address pins are no connect pins and can be tied
to VSS or left floating. If only one 24WC08 is being DEVICE ADDRESSING
addressed on the bus, the address pin (A2) can be left
floating or connected to VSS. The bus Master begins a transmission by sending a
START condition. The Master then sends the address
The 24WC16 is a stand alone device. In this case, all of the particular slave device it is requesting. The four
address pins (A0, A1and A2) are no connect pins and most significant bits of the 8-bit slave address are fixed
can be tied to VSS or left floating. as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).
The next three significant bits (A2, A1, A0) are the device
WP: Write Protect
address bits and define which device or which part of the
If the WP pin is tied to VCC the entire memory array
device the Master is accessing. Up to eight CAT24WC01/
becomes Write Protected (READ only). When the WP
02, four CAT24WC04, two CAT24WC08, and one
pin is tied to VSS or left floating normal read/write opera-
CAT24WC16 may be individually addressed by the
tions are allowed to the device.
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
I2C BUS PROTOCOL When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus proto-
col: After the Master sends a START condition and the slave
address byte, the CAT24WC01/02/04/08/16 monitors
(1) Data transfer may be initiated only when the bus is the bus and responds with an acknowledge (on the SDA
not busy.

Figure 4. Acknowledge Timing

SCL FROM 1 8 9
MASTER

DATA OUTPUT
FROM TRANSMITTER

DATA OUTPUT
FROM RECEIVER

START ACKNOWLEDGE

5020 FHD F06

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CAT24WC01/02/04/08/16

Figure 5. Slave Address Bits

24WC01/02 1 0 1 0 A2 A1 A0 R/W

24WC04 1 0 1 0 A2 A1 a8 R/W

24WC08 1 0 1 0 A2 a9 a8 R/W

24WC16 1 0 1 0 a10 a9 a8 R/W

* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.

** a8, a9 and a10 correspond to the address of the memory array address word.
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).

line) when its address matches the transmitted slave WRITE OPERATIONS
address. The CAT24WC01/02/04/08/16 then performs
a Read or Write operation depending on the state of the Byte Write
R/W bit. In the Byte Write mode, the Master device sends the
Acknowledge START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
After a successful data transfer, each receiving device is the Slave generates an acknowledge, the Master sends
required to generate an acknowledge. The Acknowledg- the byte address that is to be written into the address
ing device pulls down the SDA line during the ninth clock pointer of the CAT24WC01/02/04/08/16. After receiving
cycle, signaling that it received the 8 bits of data. another acknowledge from the Slave, the Master device
The CAT24WC01/02/04/08/16 responds with an ac- transmits the data byte to be written into the addressed
knowledge after receiving a START condition and its memory location. The CAT24WC01/02/04/08/16 ac-
slave address. If the device has been selected along knowledge once more and the Master generates the
with a write operation, it responds with an acknowledge STOP condition, at which time the device begins its
after receiving each 8-bit byte. internal programming cycle to nonvolatile memory. While
this internal cycle is in progress, the device will not
When the CAT24WC01/02/04/08/16 is in a READ mode respond to any request from the Master device.
it transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives Page Write
this acknowledge, the CAT24WC01/02/04/08/16 will The CAT24WC01/02/04/08/16 writes up to 16 bytes of
continue to transmit data. If no acknowledge is sent by data in a single write cycle, using the Page Write
the Master, the device terminates data transmission and operation. The Page Write operation is initiated in the
waits for a STOP condition. same manner as counter will ‘wrap around’ to address

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 CAT24WC01/02/04/08/16

the Byte Write operation, however instead of terminating

after the initial word is transmitted, the Master is allowed WRITE PROTECTION
to send up to P (P=7 for 24WC01 and P=15 for
CAT24WC02/04/08/16) additional bytes. After each byte The Write Protection feature allows the user to protect
has been transmitted the CAT24WC01/02/04/08/16 will against inadvertent programming of the memory array.
respond with an acknowledge, and internally increment If the WP pin is tied to VCC, the entire memory array is
the low order address bits by one. The high order bits protected and becomes read only. The CAT24WC01/
remain unchanged. 02/04/08/16 will accept both slave and byte addresses,
but the memory location accessed is protected from
If the Master transmits more than P+1 bytes prior to programming by the device’s failure to send an acknowl-
sending the STOP condition, the address counter ‘wraps edge after the first byte of data is received.
around’, and previously transmitted data will be overwrit-
ten.
READ OPERATIONS
Once all P+1 bytes are received and the STOP condition
The READ operation for the CAT24WC01/02/04/08/16
has been sent by the Master, the internal programming
is initiated in the same manner as the write operation
cycle begins. At this point all received data is written to
with the one exception that the R/W bit is set to a one.
the CAT24WC01/02/04/08/16 in a single write cycle.
Three different READ operations are possible: Immedi-
Acknowledge Polling ate Address READ, Selective READ and Sequential
READ.
The disabling of the inputs can be used to take advan-
tage of the typical write cycle time. Once the stop Immediate Address Read
condition is issued to indicate the end of the host’s write
The CAT24WC01/02/04/08/16’s address counter con-
operation, the CAT24WC01/02/04/08/16 initiates the
tains the address of the last byte accessed, incremented
internal write cycle. ACK polling can be initiated imme-
by one. In other words, if the last READ or WRITE
diately. This involves issuing the start condition followed
access was to address N, the READ immediately follow-
by the slave address for a write operation. If the
ing would access data from address N+1. If N=E (where
CAT24WC01/02/04/08/16 is still busy with the write
E = 127 for 24WC01, 255 for 24WC02, 511 for 24WC04,
operation, no ACK will be returned. If the CAT24WC01/
1023 for 24WC08, and 2047 for 24WC16), then the
02/04/08/16 has completed the write operation, an ACK
counter will 'wrap around' to address 0 and continue to
will be returned and the host can then proceed with
thenext read or write operation.
Figure 6. Byte Write Timing

S
T S
BUS ACTIVITY: A SLAVE BYTE T
MASTER R ADDRESS ADDRESS DATA O
T P
*
SDA LINE S P

A A A
C C C 5020 FHD F08
K K K

Figure 7. Page Write Timing

S
T S
BUS ACTIVITY: A SLAVE BYTE T
MASTER R ADDRESS ADDRESS (n) DATA n DATA n+1 DATA n+P O
T P

SDA LINE S * P

A A A A A
C C C C C
K K K K K

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16
24WCXX F09
* = Don't care for CAT24WC01

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CAT24WC01/02/04/08/16

clock out data. After the CAT24WC01/02/04/08/16 re-

ceives its slave address information (with the R/W bit set
to one), it issues an acknowledge, then transmits the 8-
bit byte requested. The master device does not send an
acknowledge but will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
wril goperatione r sending the START condition, slave

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 CAT24WC01/02/04/08/16

Figure 9. Selective Read Timing

S S
T T S
BUS ACTIVITY: A SLAVE BYTE A SLAVE T
MASTER R ADDRESS ADDRESS (n) R ADDRESS O
T T P

SDA LINE S * S P

A A A N
C C C DATA n O
K K K
A
C
* = Don't Care for 24WC01 K 24WCXX F11

Figure 10. Sequential Read Timing

S
BUS ACTIVITY: SLAVE T
MASTER ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x O
P

SDA LINE P

A A A A N
C C C C O
K K K K
A
C
K 5020 FHD F12

ORDERING INFORMATION

Prefix Device # Suffix

CAT 24WC02 J I -1.8 TE13

Optional Product Number Temperature Range Tape & Reel

Company ID 24WC01: 1K Blank = Commercial (0˚ - 70˚C) TE13: 2000/Reel
24WC02: 2K I = Industrial (-40˚ - 85˚C)
24WC04: 4K A = Automotive (-40˚ - 105˚C)*
24WC08: 8K
24WC16: 16K
Package Operating Voltage
P: PDIP Blank: 2.5V - 6.0V
J: SOIC (JEDEC) 1.8: 1.8V - 6.0V
U: TSSOP**

* -40˚ to +125˚C is available upon request 24WCXX F14

** Available for 24WC01 and 24WC02

Notes:
(1) The device used in the above example is a 24WC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)

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