GEN FR

ALO
CAT24WC32/64

EE
H
32K/64K-Bit I2C Serial CMOS EEPROM
LE
A D F R E ETM
FEATURES
■ 400 KHz I2C bus compatible* ■ Commercial, industrial, automotive and
■ 1.8 to 6 volt read and write operation extended automotive temperature ranges
■ Cascadable for up to eight devices ■ Write protection
– Entire array protected when WP at VIH
■ 32-Byte page write buffer
■ 1,000,000 Program/erase cycles
■ Self-timed write cycle with auto-clear
■ 100 year data retention
■ 8-pin DIP or 8-pin SOIC
■ Schmitt trigger inputs for noise protection

DESCRIPTION
The CAT24WC32/64 is a 32K/64K-bit Serial CMOS CAT24WC32/64 features a 32-byte page write buffer.
E2PROM internally organized as 4096/8192 words of 8 The device operates via the I2C bus serial interface and
bits each. Catalyst’s advanced CMOS technology sub- is available in 8-pin DIP or 8-pin SOIC packages.
stantially reduces device power requirements. The

PIN CONFIGURATION BLOCK DIAGRAM

DIP Package (P, L) EXTERNAL LOAD

1 8 DOUT SENSE AMPS

A0 VCC
SHIFT REGISTERS
A1 2 7 WP ACK
A2 3 6 SCL VCC
VSS 4 5 SDA WORD ADDRESS COLUMN
VSS
BUFFERS DECODERS

256
SOIC Package (J, W, K, X) SDA START/STOP
LOGIC
A0 1 8 VCC
A1 2 7 WP
E2PROM
A2 3 6 SCL XDEC 128/256 128/256 X 256
VSS 4 5 SDA CONTROL
WP LOGIC

PIN FUNCTIONS
Pin Name Function DATA IN STORAGE
A0, A1, A2 Device Address Inputs
SDA Serial Data/Address HIGH VOLTAGE/
TIMING CONTROL
SCL Serial Clock
WP Write Protect SCL STATE COUNTERS
VCC +1.8V to +6V Power Supply A0 SLAVE
A1 ADDRESS
VSS Ground COMPARATORS
A2
24WC32/64 F02
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

© 2004 by Catalyst Semiconductor, Inc. Doc. No. 1039, Rev. F

Characteristics subject to change without notice 1
CAT24WC32/64

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
Voltage on Any Pin with the device at these or any other conditions outside of those
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V listed in the operational sections of this specification is not
VCC with Respect to Ground ............... –2.0V to +7.0V implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
Package Power Dissipation reliability.
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA

RELIABILITY CHARACTERISTICS
Symbol Parameter Min. Max. Units Reference Test Method
NEND(3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033
TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008
VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015
ILTH(3)(4) Latch-up 100 mA JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC Power Supply Current 3 mA fSCL = 100 KHz
ISB(5) Standby Current (VCC = 5V) 1 µA VIN = GND or VCC
ILI Input Leakage Current 10 µA VIN = GND to VCC
ILO Output Leakage Current 10 µA VOUT = GND to VCC
VIL Input Low Voltage –1 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA
VOL2 Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Max. Units Conditions
CI/O(3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN(3) Input Capacitance (A0, A1, A2, SCL, WP) 6 pF VIN = 0V

Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range.

Doc. No. 1039, Rev. F

2
 CAT24WC32/64

A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
1.8V - 6.0 V
2.5V - 6.0V 4.5V-5.5V
Symbol Parameter Min. Max. Min. Max. Units
FSCL Clock Frequency 100 400 kHz
TI(1) Noise Suppression Time 200 200 ns
Constant at SCL, SDA Inputs
tAA SCL Low to SDA Data Out 3.5 1 µs
and ACK Out
tBUF(1) Time the Bus Must be Free Before 4.7 1.2 µs
a New Transmission Can Start
tHD:STA Start Condition Hold Time 4 0.6 µs
tLOW Clock Low Period 4.7 1.2 µs
tHIGH Clock High Period 4 0.6 µs
tSU:STA Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)
tHD:DAT Data In Hold Time 0 0 ns
tSU:DAT Data In Setup Time 50 50 ns
tR(1) SDA and SCL Rise Time 1 0.3 µs
tF(1) SDA and SCL Fall Time 300 300 ns
tSU:STO Stop Condition Setup Time 4 0.6 µs
tDH Data Out Hold Time 100 100 ns

Power-Up Timing (1)(2)

Symbol Parameter Max. Units
tPUR Power-Up to Read Operation 1 ms
tPUW Power-Up to Write Operation 1 ms

Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Write Cycle Limits

Symbol Parameter Min. Typ. Max Units
tWR Write Cycle Time 10 ms

The write cycle time is the time from a valid stop interface circuits are disabled, SDA is allowed to remain
condition of a write sequence to the end of the internal high, and the device does not respond to its slave
program/erase cycle. During the write cycle, the bus address.

Doc. No. 1039, Rev. F

3
CAT24WC32/64

FUNCTIONAL DESCRIPTION SDA: Serial Data/Address

The bidirectional serial data/address pin is used to
The CAT24WC32/64 supports the I2C Bus data trans- transfer all data into and out of the device. The SDA pin
mission protocol. This Inter-Integrated Circuit Bus proto- is an open drain output and can be wire-ORed with other
col defines any device that sends data to the bus to be open drain or open collector outputs.
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device A0, A1, A2: Device Address Inputs
which generates the serial clock and all START and These pins are hardwired or left unconnected (for hard-
STOP conditions for bus access. The CAT24WC32/64 ware compatibility with CAT24WC16). When hardwired,
operates as a Slave device. Both the Master device and up to eight CAT24WC32/64s may be addressed on a
Slave device can operate as either transmitter or re- single bus system (refer to Device Addressing ). When
ceiver, but the Master device controls which mode is the pins are left unconnected, the default values are
activated. zeros.
WP: Write Protect
PIN DESCRIPTIONS This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC32/64 when this pin
SCL: Serial Clock is tied to Vcc, the entire memory is write protected.
The serial clock input clocks all data transferred into or When left floating, memory is unprotected.
out of the device.

Figure 1. Bus Timing tF tHIGH tR

tLOW tLOW

SCL

tSU:STA tHD:DAT
tHD:STA tSU:DAT tSU:STO

SDA IN
tBUF
tAA tDH

SDA OUT

5020 FHD F03

Figure 2. Write Cycle Timing

SCL

SDA 8TH BIT ACK

BYTE n
tWR

STOP START ADDRESS

CONDITION CONDITION 5020 FHD F04

Figure 3. Start/Stop Timing

SDA

SCL

5020 FHD F05

START BIT STOP BIT

Doc. No. 1039, Rev. F

4
 CAT24WC32/64

I2C BUS PROTOCOL compare to the hardwired input pins, A2, A1 and A0. The
last bit of the slave address specifies whether a Read or
The features of the I2C bus protocol are defined as Write operation is to be performed. When this bit is set
follows: to 1, a Read operation is selected, and when set to 0, a
(1) Data transfer may be initiated only when the bus is Write operation is selected.
not busy. After the Master sends a START condition and the slave
(2) During a data transfer, the data line must remain address byte, the CAT24WC32/64 monitors the bus and
stable whenever the clock line is high. Any changes responds with an acknowledge (on the SDA line) when
in the data line while the clock line is high will be its address matches the transmitted slave address. The
interpreted as a START or STOP condition. CAT24WC32/64 then performs a Read or Write opera-
tion depending on the state of the R/W bit.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of After a successful data transfer, each receiving device is
SDA when SCL is HIGH. The CAT24WC32/64 monitors required to generate an acknowledge. The Acknowledg-
the SDA and SCL lines and will not respond until this ing device pulls down the SDA line during the ninth clock
condition is met. cycle, signaling that it received the 8 bits of data.

STOP Condition The CAT24WC32/64 responds with an acknowledge

after receiving a START condition and its slave address.
A LOW to HIGH transition of SDA when SCL is HIGH If the device has been selected along with a write
determines the STOP condition. All operations must end operation, it responds with an acknowledge after receiv-
with a STOP condition. ing each 8-bit byte.

When the CAT24WC32/64 begins a READ mode it

DEVICE ADDRESSING transmits 8 bits of data, releases the SDA line, and
The bus Master begins a transmission by sending a monitors the line for an acknowledge. Once it receives
START condition. The Master sends the address of the this acknowledge, the CAT24WC32/64 will continue to
particular slave device it is requesting. The four most transmit data. If no acknowledge is sent by the Master,
significant bits of the 8-bit slave address are fixed as the device terminates data transmission and waits for a
1010 (Fig. 5). The next three bits (A2, A1, A0) are the STOP condition. The master must then issue a stop
device address bits; up to eight 32K/64K devices may condition to return the CAT24WC32/64 to the standby
to be connected to the same bus. These bits must power mode and place the device in a known state.

Figure 4. Acknowledge Timing

SCL FROM 1 8 9
MASTER

DATA OUTPUT
FROM TRANSMITTER

DATA OUTPUT
FROM RECEIVER

START ACKNOWLEDGE
5020 FHD F06

Figure 5. Slave Address Bits

1 0 1 0 A2 A1 A0 R/W

5027 FHD F07

Doc. No. 1039, Rev. F

5
CAT24WC32/64

WRITE OPERATIONS If the Master transmits more than 32 bytes before sending
the STOP condition, the address counter ‘wraps around’,
Byte Write and previously transmitted data will be overwritten.
In the Byte Write mode, the Master device sends the
When all 32 bytes are received, and the STOP condition
START condition and the slave address information
has been sent by the Master, the internal programming
(with the R/W bit set to zero) to the Slave device. After
cycle begins. At this point, all received data is written to
the Slave generates an acknowledge, the Master sends
the CAT24WC32/64 in a single write cycle.
two 8-bit address words that are to be written into the
address pointers of the CAT24WC32/64. After receiving Acknowledge Polling
another acknowledge from the Slave, the Master device
Disabling of the inputs can be used to take advantage of
transmits the data to be written into the addressed
the typical write cycle time. Once the stop condition is
memory location. The CAT24WC32/64 acknowledges
issued to indicate the end of the host's write operation,
once more and the Master generates the STOP condi-
CAT24WC32/64 initiates the internal write cycle. ACK
tion. At this time, the device begins an internal program-
polling can be initiated immediately. This involves issu-
ming cycle to nonvolatile memory. While the cycle is in
ing the start condition followed by the slave address for
progress, the device will not respond to any request from
a write operation. If CAT24WC32/64 is still busy with the
the Master device.
write operation, no ACK will be returned. If
Page Write CAT24WC32/64 has completed the write operation, an
ACK will be returned and the host can then proceed with
The CAT24WC32/64 writes up to 32 bytes of data, in a
the next read or write operation.
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating WRITE PROTECTION
after the initial byte is transmitted, the Master is allowed
to send up to 31 additional bytes. After each byte has The Write Protection feature allows the user to protect
been transmitted, CAT24WC32/64 will respond with an against inadvertent programming of the memory array.
acknowledge, and internally increment the five low order If the WP pin is tied to VCC, the entire memory array is
address bits by one. The high order bits remain un- protected and becomes read only. The CAT24WC32/64
changed. will accept both slave and byte addresses, but the

Figure 6. Byte Write Timing

S
T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS T
MASTER R ADDRESS A15–A8 A7–A0 DATA O
T P
SDA LINE S X XX * P

A A A A
C C C C
K K K K
24WC32/64 F08

Figure 7. Page Write Timing

S
T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS T
MASTER R ADDRESS A15–A8 A7–A0 DATA DATA n DATA n+31 O
T P

SDA LINE S X XX * P

A A A A A A A
C C C C C C C
K K K K K K K

* = Don't care bit for 24WC32

X= Don't care bit 24WC32/64 F09

Doc. No. 1039, Rev. F

6
 CAT24WC32/64

memory location accessed is protected from program- ‘dummy’ write operation by sending the START condi-
ming by the device’s failure to send an acknowledge tion, slave address and byte addresses of the location it
after the first byte of data is received. wishes to read. After CAT24WC32/64 acknowledges,
the Master device sends the START condition and the
slave address again, this time with the R/W bit set to one.
READ OPERATIONS
The CAT24WC32/64 then responds with its acknowl-
The READ operation for the CAT24WC32/64 is initiated edge and sends the 8-bit byte requested. The master
in the same manner as the write operation with one device does not send an acknowledge but will generate
exception, that R/W bit is set to one. Three different a STOP condition.
READ operations are possible: Immediate/Current Ad-
Sequential Read
dress READ, Selective/Random READ and Sequential
READ. The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
Immediate/Current Address Read operations. After the CAT24WC32/64 sends the initial 8-
The CAT24WC32/64’s address counter contains the bit byte requested, the Master will respond with an
address of the last byte accessed, incremented by one. acknowledge which tells the device it requires more
In other words, if the last READ or WRITE access was data. The CAT24WC32/64 will continue to output an 8-
to address N, the READ immediately following would bit byte for each acknowledge sent by the Master. The
access data from address N+1. If N=E (where E=4095 operation will terminate when the Master fails to respond
for 24WC32 and E=8191 for 24WC64), then the counter with an acknowledge, thus sending the STOP condition.
will ‘wrap around’ to address 0 and continue to clock out
The data being transmitted from CAT24WC32/64 is
data. After the CAT24WC32/64 receives its slave ad-
outputted sequentially with data from address N fol-
dress information (with the R/W bit set to one), it issues
lowed by data from address N+1. The READ operation
an acknowledge, then transmits the 8 bit byte requested.
address counter increments all of the CAT24WC32/64
The master device does not send an acknowledge, but
address bits so that the entire memory array can be read
will generate a STOP condition.
during one operation. If more than E (where E=4095 for
Selective/Random Read 24WC32 and E=8191 for 24WC64) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
Selective/Random READ operations allow the Master
data bytes.
device to select at random any memory location for a
READ operation. The Master device first performs a

Figure 8. Immediate Address Read Timing

S
T S
BUS ACTIVITY: A SLAVE T
MASTER R ADDRESS DATA O
T P
SDA LINE S P

A N
C O
K A
C
K

SCL 8 9

SDA 8TH BIT

DATA OUT NO ACK STOP

24WC32/64 F10

Doc. No. 1039, Rev. F

7
CAT24WC32/64

Figure 9. Selective Read Timing

S S
T T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS A SLAVE T
MASTER R ADDRESS A15–A8 A7–A0 R ADDRESS DATA O
T T P
SDA LINE S XXX * S P

A A A A N
C C C C O
K K K K A
C
K

* = Don't care bit for 24WC32 24WC32/64 F11

X= Don't care bit

Figure 10. Sequential Read Timing

S
BUS ACTIVITY: SLAVE T
MASTER ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x O
P
SDA LINE P

A A A A N
C C C C O
K K K K
A
C
K
5020 FHD F12

Doc. No. 1039, Rev. F

8
 CAT24WC32/64

ORDERING INFORMATION

Prefix Device # Suffix

CAT 24WC32 J I -1.8 TE13 Rev B(2)

Optional Product Temperature Range Tape & Reel

Company ID Number Blank = Commercial (0˚C to +70˚C) TE13: 2000/Reel
24WC32: 32K I = Industrial (-40˚C to +85˚C)
24WC64: 64K A = Automotive (-40˚ to +105˚C)
E = Extended (-40˚C to +125˚C)

Package Operating Voltage Die Revision

P: 8-Pin PDIP Blank = 2.5 to 6.0V 24WC32: B
J: 8-Pin SOIC (JEDEC) 1.8 = 1.8 to 6.0V 24WC64: B
K: 8-Pin SOIC (EIAJ)
L: 8-Pin PDIP (Lead-free, Halogen-free)
W: 8-Pin SOIC (JEDEC, Lead-free, Halogen-free)
X: 8-Pin SOIC (EIAJ, Lead-free, Halogen-free)

Notes:
(1) The device used in the above example is a 24WC32JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWB). For additional
information, please contact your Catalyst sales office.

Doc. No. 1039, Rev. F

9
REVISION HISTORY
Date Rev. Reason
7/7/2004 E Added die revision to Ordering Information
7/28/2004 F Updated Features
Updated DC operating characteristics and notes

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Phone: 408.542.1000 Publication #: 1039
Fax: 408.542.1200 Revison: F
www.catalyst-semiconductor.com Issue date: 7/28/04
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