ST24/25C04, ST24C04R

ST24/25W04

SERIAL 4K (512 x 8) EEPROM

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for ST24x04 versions
– 2.5V to 5.5V for ST25x04 versions
– 1.8V to 5.5V for ST24C04R version only 8
8
HARDWARE WRITE CONTROL VERSIONS:
ST24W04 and ST25W04 1
1
PROGRAMMABLE WRITE PROTECTION
TWO WIRE SERIAL INTERFACE, FULLY I2C PSDIP8 (B) SO8 (M)
BUS COMPATIBLE 0.25mm Frame 150mil Width
BYTE and MULTIBYTE WRITE (up to 4
BYTES)
PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ
MODES Figure 1. Logic Diagram
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES

VCC
DESCRIPTION
This specification covers a range of 4K bits I2C bus
EEPROM prod ucts, t he ST 24 /25C04, the 2
ST24C04R and the ST24/25W04. In the text, prod- E1-E2 SDA
ucts are referred to as ST24/25x04, where ”x” is:
”C” for Standard version and ”W” for hardware PRE ST24x04
Write Control version. ST25x04
SCL St24C04R
Table 1. Signal Names MODE/WC*
PRE Write Protect Enable
E1-E2 Chip Enable Inputs
SDA Serial Data Address Input/Output VSS
AI00851D
SCL Serial Clock
Multibyte/Page Write Mode
MODE
(C version)
WC Write Control (W version)
VCC Supply Voltage
VSS Ground Note: WC signal is only available for ST24/25W04 products.

July 1996 1/16

ST24/25C04, ST24C04R, ST24/25W04

Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections

ST24x04 ST24x04
ST25x04 ST25x04
ST24C04R ST24C04R

PRE 1 8 VCC PRE 1 8 VCC

E1 2 7 MODE/WC E1 2 7 MODE/WC
E2 3 6 SCL E2 3 6 SCL
VSS 4 5 SDA VSS 4 5 SDA
AI00852D AI01107D

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit
TA Ambient Operating Temperature –40 to 125 °C
TSTG Storage Temperature –65 to 150 °C
TLEAD Lead Temperature, Soldering (SO8 package) 40 sec 215
°C
(PSDIP8 package) 10 sec 260
VIO Input or Output Voltages –0.6 to 6.5 V
VCC Supply Voltage –0.3 to 6.5 V
(2)
Electrostatic Discharge Voltage (Human Body model) 4000 V
VESD
(3)
Electrostatic Discharge Voltage (Machine model) 500 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d) tional data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
The ST24/25x04 are 4K bit electrically erasable code (1010) corresponding to the I2C bus defini-
programmable memories (EEPROM), organized tion. This is used together with 2 chip enable inputs
as 2 blocks of 256 x 8 bits. They are manufactured (E2, E1) so that up to 4 x 4K devices may be
in SGS-THOMSON’s Hi-Endurance Advanced attached to the I2C bus and selected individually.
CMOS technology which guarantees an endur- The memories behave as a slave device in the I2C
ance of one million erase/write cycles with a data protocol with all memory operations synchronized
retention of 40 years. The memories operate with by the serial clock. Read and write operations are
a power supply value as low as 1.8V for the initiated by a START condition generated by the
ST24C04R only. bus master. The START condition is followed by a
stream of 7 bits (identification code 1010), plus one
Both Plastic Dual-in-Line and Plastic Small Outline read/write bit and terminated by an acknowledge
packages are available. bit.
The memories are compatible with the I2C stand-
ard, two wire serial interface which uses a bi-direc-

2/16
 ST24/25C04, ST24C04R, ST24/25W04

Table 3. Device Select Code

Block
Device Code Chip Enable RW
Select
Bit b7 b6 b5 b4 b3 b2 b1 b0

Device Select 1 0 1 0 E2 E1 A8 RW
Note: The MSB b7 is sent first.

Table 4. Operating Modes (1)

Mode RW bit MODE Bytes Initial Sequence

Current Address Read ’1’ X 1 START, Device Select, RW = ’1’

’0’ START, Device Select, RW = ’0’, Address,

Random Address Read X 1
’1’ reSTART, Device Select, RW = ’1’
Sequential Read ’1’ X 1 to 512 Similar to Current or Random Mode
Byte Write ’0’ X 1 START, Device Select, RW = ’0’
(2)
Multibyte Write ’0’ VIH 4 START, Device Select, RW = ’0’
Page Write ’0’ VIL 8 START, Device Select, RW = ’0’
Notes: 1. X = VIH or VIL
2. Multibyte Write not available in ST24/25W04 versions.

When writing data to the memory it responds to the with other open drain or open collector signals on
8 bits received by asserting an acknowledge bit the bus. Aresistor must be connectedfrom the SDA
during the 9th bit time. When data is read by the bus line to VCC to act as pull up (see Figure 3).
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi- Chip Enable (E1 - E2). These chip enable inputs
are used to set the 2 least significant bits (b2, b3)
nated with a STOP condition. of the 7 bit device select code. These inputs may
Power On Reset: VCC lock out write protect. In be driven dynamically or tied to VCC or VSS to
order to prevent data corruption and inadvertent establish the device select code.
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC Protect Enable (PRE). The PRE input pin, in ad-
voltage has reached the POR threshold value, the dition to the status of the Block Address Pointer bit
internal reset is active, all operations are disabled (b2, location 1FFh as in Figure 7), sets the PRE
and the device will not respond to any command. write protection active.
In the same way, when VCC drops down from the Mode (MODE). The MODE input is available on pin
operating voltage to below the POR threshold 7 (see also WC feature) and may be driven dynami-
value, all operations are disabled and the device cally. It must be at VIL or VIH for the Byte Write
will not respond to any command. A stable VCC mode, VIH for Multibyte Write mode or VIL for Page
must be applied before applying any logic signal. Write mode. When unconnected, the MODE input
is internally read as VIH (Multibyte Write mode).
SIGNAL DESCRIPTIONS Write Control (WC). An hardware Write Control
feature (WC) is offered only for ST24W04 and
Serial Clock (SCL). The SCL input pin is used to ST25W04 versions on pin 7. This feature is usefull
synchronize all data in and out of the memory. A to protect the contents of the memory from any
resistor can be connected from the SCL line to VCC erroneous erase/write cycle. The Write Control sig-
to act as a pull up (see Figure 3). nal is used to enable (WC = VIH) or disable (WC =
Serial Data (SDA). The SDA pin is bi-directional VIL) the internal write protection. When uncon-
and is used to transfer data in or out of the memory. nected, the WC input is internally read as VIL and
It is an open drain output that may be wire-OR’ed the memory area is not write protected.

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ST24/25C04, ST24C04R, ST24/25W04

SIGNAL DESCRIPTIONS (cont’d) Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is
The devices with this Write Control feature no stable in the high state. A STOP condition termi-
longer support the Multibyte Write mode of opera- nates communication between the ST24/25x04
tion, however all other write modes are fully sup- and the bus master. A STOP condition at the end
ported. of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
Refer to the AN404 Application Note for more de- condition at the end of a Write command triggers
tailed information about Write Control feature.
the internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
DEVICE OPERATION is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
I2C Bus Background the SDA bus after sending 8 bits of data. During the
The ST24/25x04 support the I2C protocol. This 9th clock pulse period the receiver pulls the SDA
protocol defines any device that sends data onto bus low to acknowledge the receipt of the 8 bits of
the bus as a transmitter and any device that reads data.
the data as a receiver. The device that controls the Data Input. During data input the ST24/25x04
data transfer is known as the master and the other sample the SDA bus signal on the rising edge of
as the slave. The master will always initiate a data the clock SCL. Note that for correct device opera-
transfer and will provide the serial clock for syn- tion the SDA signal must be stable during the clock
chronisation. The ST24/25x04 are always slave low to high transition and the data must change
devices in all communications. ONLY when the SCL line is low.
Start Condition. START is identified by a high to Memory Addressing. To start communication be-
low transition of the SDA line while the clock SCL tween the bus master and the slave ST24/25x04,
is stable in the high state. A START condition must the master must initiate a START condition. Follow-
precede any command for data transfer. Except ing this, the master sends onto the SDA bus line 8
during a programming cycle, the ST24/25x04 con- bits (MSB first) corresponding to the device select
tinuously monitor the SDA and SCL signals for a code (7 bits) and a READ or WRITE bit.
START condition and will not respond unless one
is given.

Figure 3. Maximum RL Value versus Bus Capacitance (C BUS) for an I2C Bus

20

VCC

16

RL RL
12
RL max (kΩ)

SDA

MASTER CBUS
SCL
8

CBUS

4
VCC = 5V

0
100 200 300 400

CBUS (pF) AI01100

4/16
 ST24/25C04, ST24C04R, ST24/25W04

Table 5. Input Parameters (1) (TA = 25 °C, f = 100 kHz )

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance (SDA) 8 pF

CIN Input Capacitance (other pins) 6 pF

ZWCL WC Input Impedance (ST24/25W04) VIN ≤ 0.3 VCC 5 20 kΩ

ZWCH WC Input Impedance (ST24/25W04) VIN ≥ 0.7 VCC 500 kΩ

Low-pass filter input time constant

tLP 100 ns
(SDA and SCL)
Note: 1. Sampled only, not 100% tested.

Table 6. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2 µA
0V ≤ VOUT ≤ VCC
ILO Output Leakage Current ±2 µA
SDA in Hi-Z
VCC = 5V, fC = 100kHz
Supply Current (ST24 series) 2 mA
ICC (Rise/Fall time < 10ns)
Supply Current (ST25 series) VCC = 2.5V, fC = 100kHz 1 mA
VIN = VSS or VCC,
100 µA
Supply Current (Standby) VCC = 5V
ICC1
(ST24 series)
VIN = VSS or VCC,
300 µA
VCC = 5V, fC = 100kHz
VIN = VSS or VCC,
5 µA
Supply Current (Standby) VCC = 2.5V
ICC2
(ST25 series)
VIN = VSS or VCC,
50 µA
VCC = 2.5V, fC = 100kHz
VIN = VSS or VCC,
20 µA
Supply Current (Standby) VCC = 3.6V
ICC3
(ST24C04R)
VIN = VSS or VCC,
60 µA
VCC = 3.6V, fC = 100kHz
VIN = VSS or VCC,
10 µA
Supply Current (Standby) VCC = 1.8V
ICC4
(ST24C04R)
VIN = VSS or VCC,
20 µA
VCC = 1.8V, fC = 100kHz
VIL Input Low Voltage (SCL, SDA) –0.3 0.3 VCC V
VIH Input High Voltage (SCL, SDA) 0.7 VCC VCC + 1 V
Input Low Voltage
VIL –0.3 0.5 V
(E1-E2, PRE, MODE, WC)
Input High Voltage
VIH VCC – 0.5 VCC + 1 V
(E1-E2, PRE, MODE, WC)
Output Low Voltage (ST24 series) IOL = 3mA, VCC = 5V 0.4 V
VOL Output Low Voltage (ST25 series) IOL = 2.1mA, VCC = 2.5V 0.4 V
Output Low Voltage
IOL = 1mA, VCC = 1.8V 0.3 V
(ST24C04R)

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ST24/25C04, ST24C04R, ST24/25W04

Table 7. AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)
Symbol Alt Parameter Min Max Unit

tCH1CH2 tR Clock Rise Time 1 µs

tCL1CL2 tF Clock Fall Time 300 ns

tDH1DH2 tR Input Rise Time 1 µs

tDL1DL1 tF Input Fall Time 300 ns

(1)
tCHDX tSU:STA Clock High to Input Transition 4.7 µs

tCHCL tHIGH Clock Pulse Width High 4 µs

tDLCL tHD:STA Input Low to Clock Low (START) 4 µs

tCLDX tHD:DAT Clock Low to Input Transition 0 µs

tCLCH tLOW Clock Pulse Width Low 4.7 µs

tDXCX tSU:DAT Input Transition to Clock Transition 250 ns

tCHDH tSU:STO Clock High to Input High (STOP) 4.7 µs

tDHDL tBUF Input High to Input Low (Bus Free) 4.7 µs

(2)
tCLQV tAA Clock Low to Next Data Out Valid 0.3 3.5 µs

tCLQX tDH Data Out Hold Time 300 ns

fC fSCL Clock Frequency 100 kHz

(3)
tW tWR Write Time 10 ms
Notes: 1. For a reSTART condition, or following a write cycle.
2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the
maximum programming time is doubled to 20ms.

AC MEASUREMENT CONDITIONS DEVICE OPERATION (cont’d)

Input Rise and Fall Times ≤ 50ns

The 4 most significant bits of the device select code
are the device type identifier, corresponding to the
Input Pulse Voltages 0.2VCC to 0.8VCC
I2C bus definition. For these memories the 4 bits
are fixed as 1010b. The following 2 bits identify the
Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC specific memory on the bus. They are matched to
the chip enable signals E2, E1. Thus up to 4 x 4K
memories can be connected on the same bus
giving a memory capacity total of 16K bits. After a
Figure 4. AC Testing Input Output Waveforms START condition any memory on the bus will iden-
tify the device code and compare the following 2
bits to its chip enable inputs E2, E1.
0.8VCC
0.7VCC The 7th bit sent is the block number (one block =
256 bytes). The 8th bit sent is the read or write bit
0.3VCC (RW), this bit is set to ’1’ for read and ’0’ for write
0.2VCC
operations. If a match is found, the corresponding
AI00825 memory will acknowledge the identification on the
SDA bus during the 9th bit time.

6/16
 ST24/25C04, ST24C04R, ST24/25W04

Figure 5. AC Waveforms

tCHCL tCLCH

SCL

tDLCL tDXCX tCHDH

SDA IN

tCHDX tCLDX tDHDL

START SDA SDA STOP &

CONDITION INPUT CHANGE BUS FREE

SCL

tCLQV tCLQX

SDA OUT DATA VALID

DATA OUTPUT

tDHDL

SCL

tW

SDA IN

tCHDH tCHDX

STOP WRITE CYCLE START

CONDITION CONDITION

AI00795

Write Operations For the ST24/25W04 versions, any write command

with WC = 1 will not modify the memory content.
The Multibyte Write mode (only available on the
ST24/25C04 and ST24C04R versions) is selected Byte Write. In the Byte Write mode the master
when the MODE pin is at VIH and the Page Write sends one data byte, which is acknowledged by the
mode when MODE pin is at VIL. The MODE pin may memory. The master then terminates the transfer
be driven dynamically with CMOS input levels. by generating a STOP condition. The Write mode
is independantof the state of the MODE pin which
Following a START condition the master sends a could be left floating if only this mode was to be
device select code with the RW bit reset to ’0’. The used. However it is not a recommended operating
memory acknowledges this and waits for a byte mode, as this pin has to be connected to either VIH
address. The byte address of 8 bits provides ac- or VIL, to minimize the stand-by current.
cess to one block of 256 bytes of the memory. After
receipt of the byte address the device again re-
sponds with an acknowledge.

7/16
ST24/25C04, ST24C04R, ST24/25W04

Figure 6. I2C Bus Protocol

SCL

SDA

START SDA SDA STOP

CONDITION INPUT CHANGE CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

START
CONDITION

SCL 1 2 3 7 8 9

SDA MSB ACK

STOP
CONDITION

AI00792

Multibyte Write. For the Multibyte Write mode, the Multibyte Write mode may modify data bytes in an
MODE pin must be at VIH. The Multibyte Write adjacent row (one row is 8 bytes long). However,
mode can be started from any address in the the Multibyte Write can properly write up to 8
memory. The master sends from one up to 4 bytes consecutive bytes as soon as the first address of
of data, which are each acknowledgedby the mem- these 8 bytes is the first address of the row, the 7
ory. The transfer is terminated by the master gen- following bytes being written in the 7 following bytes
erating a STOP condition. The duration of the write of this same row.
cycle is t W = 10ms maximum except when bytes Page Write. For the Page Write mode, the MODE
are accessed on 2 rows (that is have different pin must be at VIL. The Page Write mode allows up
values for the 6 most significant address bits A7- to 8 bytes to be written in a single write cycle,
A2), the programming time is then doubled to a provided that they are all located in the same ’row’
maximum of 20ms. Writing more than 4 bytes in the in the memory: that is the 5 most significant mem-

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 ST24/25C04, ST24C04R, ST24/25W04

ory address bits (A7-A3) are the same inside one Figure 7. Memory Protection
block. The master sends from one up to 8 bytes of
data, which are each acknowledged by the mem-
ory. After each byte is transfered, the internal byte Protect Location
address counter (3 least significant bits only) is
8 byte Protect Flag
incremented. The transfer is terminated by the boundary Enable = 0
master generating a STOP condition. Care must be address Disable = 1
taken to avoid address counter ’roll-over’ which
could result in data being overwritten. Note that, for b7 b3 b2
any write mode, the generationby the master of the 1FFh X X
STOP condition starts the internal memory pro-
gram cycle. All inputs are disabled until the comple-
tion of this cycle and the memory will not respond Block 1
to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon- 100h
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is Block 0
shorter, the time seen by the system may be re- AI00855B
duced by an ACK polling sequence issued by the
master.

Figure 8. Write Cycle Polling using ACK

WRITE Cycle
in Progress

START Condition

DEVICE SELECT
with RW = 0

NO ACK
Returned

First byte of instruction YES

with RW = 0 already
decoded by ST24xxx

Next
NO Operation is YES
Addressing the
Memory
Send
Byte Address
ReSTART

STOP

Proceed Proceed
WRITE Operation Random Address
READ Operation

AI01099B

9/16
ST24/25C04, ST24C04R, ST24/25W04

Figure 9. Write Modes Sequence (ST24/25C04 and ST24C04R)

ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

STOP
R/W

ACK ACK ACK

MULTIBYTE
AND DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
PAGE WRITE
START

R/W

ACK ACK

DATA IN N
STOP

AI00793

DEVICE OPERATION (cont’d) ’0’. This Address Pointer can therefore address a
boundary in steps of 8 bytes.
The sequence is as follows: The sequence to use the Write Protected feature
– Initial condition:a Write is in progress (see Figure is:
8).
– write the data to be protected into the top of the
– Step 1: the Master issues a START condition memory, up to, but not including, location 1FFh;
followed by a Device Select byte (1st byte of the
new instruction). – set the protection by writing the correct bottom
boundary address in the Address Pointer (5
– Step 2: if the memory is busy with the internal MSBs of location 1FFh) with bit b2 (Protect flag)
write cycle, no ACK will be returned and the set to ’0’. Note that for a correct fonctionality of
master goes back to Step 1. If the memory has the memory, all the 3 LSBs of the Block Address
terminated the internal write cycle, it will re- Pointer must also be programmed at ’0’.
spond with an ACK, indicating that the memory
is ready to receive the second part of the next The area will now be protected when the PRE input
instruction (the first byte of this instruction was pin is taken High. While the PRE input pin is read
already sent during Step 1). at ’0’ by the memory, the location 1FFh can be used
Write Protection. Data in the upper block of 256 as a normal EEPROM byte.
bytes of the memory may be write protected. The Caution: Special attention must be used when
memory is write protected between a boundary using the protect mode together with the Multibyte
address and the top of memory (address 1FFh) Write mode (MODE input pin High). If the Multibyte
when the PRE input pin is taken high and when the Write starts at the location right below the first byte
Protect Flag (bit b2 in location 1FFh) is set to ’0’. of the Write Protected area, then the instruction will
The boundary address is user defined by writing it write over the first 3 bytes of the Write Protected
in the Block Address Pointer. The Block Address area. The area protected is therefore smaller than
Pointer is an 8 bit EEPROM register located at the the content defined in the location 1FFh, by 3 bytes.
address 1FFh. It is composed by 5 MSBs Address This does not apply to the Page Write mode as the
Pointer, which defines the bottom boundary ad- address counter ’roll-over’ and thus cannot go
dress, and 3 LSBs which must be programmed at above the 8 bytes lower boundary of the protected
area.

10/16
 ST24/25C04, ST24C04R, ST24/25W04

Figure 10. Write Modes Sequence with Write Control = 1 (ST24/25W04)

WC

ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2

START

R/W

WC (cont’d)

ACK ACK

PAGE WRITE DATA IN N

(cont’d)
STOP

AI01101B

Read Operations Random Address Read. A dummy write is per-

Read operationsare independentof the state of the formed to load the address into the address
MODE pin. On delivery, the memory content is set counter, see Figure 11. This is followed by another
at all ”1’s” (or FFh). START condition from the master and the byte
address is repeated with the RW bit set to ’1’. The
Current Address Read. The memory has an inter- memory acknowledges this and outputs the byte
nal byte address counter. Each time a byte is read,
addressed. The master have to NOT acknowledge
this counter is incremented. For the Current Ad- the byte output, but terminates the transfer with a
dress Read mode, following a START condition, STOP condition.
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and Sequential Read. This mode can be initiated with
outputs the byte addressed by the internal byte either a Current Address Read or a Random Ad-
address counter. This counter is then incremented. dress Read. However, in this case the master
The master does NOT acknowledge the byte out- DOES acknowledge the data byte output and the
put, but terminates the transfer with a STOP con- memory continues to output the next byte in se-
dition. quence. To terminate the stream of bytes, the
master must NOT acknowledge the last byte out-

11/16
ST24/25C04, ST24C04R, ST24/25W04

DEVICE OPERATION (cont’d) counter will ’roll- over’ and the memory will continue
to output data.
put, but MUST generate a STOP condition. The Acknowledge in Read Mode. In all read modes
output data is from consecutive byte addresses, the ST24/25x04wait for anacknowledge during the
with the internal byte address counter automat- 9th bit time. If the master does not pull the SDA line
ically incremented after each byte output. After a low during this time, the ST24/25x04terminate the
count of the last memory address, the address data transfer and switches to a standby state.

Figure 11. Read Modes Sequence

ACK NO ACK
CURRENT
ADDRESS DEV SEL DATA OUT
READ

STOP
START

R/W

ACK ACK ACK NO ACK

RANDOM
ADDRESS DEV SEL * BYTE ADDR DEV SEL * DATA OUT
READ
START

START

STOP
R/W R/W

ACK ACK ACK NO ACK

SEQUENTIAL
CURRENT DEV SEL DATA OUT 1 DATA OUT N
READ
START

STOP

R/W

ACK ACK ACK ACK

SEQUENTIAL
RANDOM DEV SEL * BYTE ADDR DEV SEL * DATA OUT 1
READ
START

START

R/W R/W

ACK NO ACK

DATA OUT N
STOP

AI00794C

Note: * The 7 Most Significant bits of DEV SEL bytes of a Random Read (1st byte and 3rd byte) must be identical.

12/16
 ST24/25C04, ST24C04R, ST24/25W04

ORDERING INFORMATION SCHEME

Example: ST24C04 M 1 TR

Operating Voltage Range

ST24C04 3V to 5.5V Standard
ST24W04 3V to 5.5V Hardware Write Control
ST25C04 2.5V to 5.5V Standard
ST25W04 2.5V to 5.5V Hardware Write Control
ST24C04R 1.8V to 5.5V Standard

Package Temperature Range Option

B PSDIP8 1 0 to 70 °C TR Tape & Reel
0.25mm Frame Packing
5* –20 to 85 °C
M SO8 150mil Width
6 –40 to 85 °C
3* –40 to 125 °C

Notes: 3 * Temperature range on special request only.

5 * Temperature range for ST24C04R only.

Parts are shipped with the memory content set at all ”1’s” (FFh).
For a list of available options (Operating Voltage, Range, Package, etc...) refer to the current Memory
Shortform catalogue.
For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office
nearest to you.

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ST24/25C04, ST24C04R, ST24/25W04

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches
Symb
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –

eB 10.00 0.394
L 3.00 3.80 0.118 0.150

N 8 8
PSDIP8

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Drawing is not to scale

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 ST24/25C04, ST24C04R, ST24/25W04

SO8 - 8 lead Plastic Small Outline, 150 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.90 0.016 0.035

α 0° 8° 0° 8°

N 8 8
CP 0.10 0.004
SO8

h x 45°

A
C
B
e CP

E H
1

A1 α L

SO-a

Drawing is not to scale

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ST24/25C04, ST24C04R, ST24/25W04

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress
written approval of SGS-THOMSON Microelectronics.

 1996 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I2C Components by SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in an I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

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