LP3470 (D30C SOT23-5)

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LP3470
SNVS003G – JUNE 1999 – REVISED APRIL 2016
LP3470 Voltage Supervisor With Programmable Delay and 1% Reset Threshold

1 Features 3 Description
•
1 5-Pin SOT-23 Package The LP3470 device is a micropower voltage
supervisory circuit designed to monitor voltages
• Open-Drain Reset Output within 1% of reset threshold over temperature. It
• Programmable Reset Time-Out Period Using an provides maximum adjustability for power-on-reset
External Capacitor (POR) and supervisory functions.
• Immune to Short VCC Transients The LP3470 asserts a reset signal whenever the VCC
• ±1% Reset Threshold Accuracy Over supply voltage falls below a reset threshold. The
Temperature reset time-out period is adjustable using an external
• Low Quiescent Current (16 µA typical) capacitor. Reset remains asserted for an interval
(programmed by an external capacitor) after VCC has
• Reset Valid Down to VCC = 0.5 V risen above the threshold voltage.
2 Applications For information on available reset threshold voltage

options, see Mechanical, Packaging, and Orderable
• Critical µP and µC Power Monitoring Information.
• Intelligent Instruments
• Computers Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Portable and Battery-Powered Equipment
LP3470 SOT-23 (5) 1.60 mm × 2.90 mm
(1) For all available packages, see the Package Option
Addendum at the end of the data sheet.
Basic Operating Circuit
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP3470
SNVS003G – JUNE 1999 – REVISED APRIL 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................... 8
2 Applications ........................................................... 1 7.4 Device Functional Modes.......................................... 9
3 Description ............................................................. 1 8 Application and Implementation ........................ 10
4 Revision History..................................................... 2 8.1 Application Information............................................ 10
8.2 Typical Application ................................................. 10
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 12
6.1 Absolute Maximum Ratings ..................................... 4 10 Layout................................................................... 12
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 12
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 12
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 13
6.5 Electrical Characteristics........................................... 5 11.1 Community Resources.......................................... 13
6.6 Typical Characteristics .............................................. 6 11.2 Trademarks ........................................................... 13
7 Detailed Description .............................................. 8 11.3 Electrostatic Discharge Caution ............................ 13
7.1 Overview ................................................................... 8 11.4 Glossary ................................................................ 13
7.2 Functional Block Diagram ......................................... 8 12 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2013) to Revision G Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Moved Operating temperature parameters from Absolute Maximum Ratings to Recommended Operating Conditions....... 4
Changes from Revision E (September 2009) to Revision F Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated
Product Folder Links: LP3470

LP3470
www.ti.com SNVS003G – JUNE 1999 – REVISED APRIL 2016
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
SRT 1 5 Reset
GND 2
VCC1 3 4 VCC
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
Set reset time-out. Connect a capacitor between this pin and ground to select the reset time-out period (tRP).
1 SRT O
tRP = 2000 × C1 (C1 in µF and tRP in ms). If no capacitor is connected, leave this pin floating.
2 GND — Ground pin.
3 VCC1 I Always connect to pin VCC (Pin 4).
4 VCC I Supply voltage, and reset threshold monitor input.
Open-drain, active-low reset output. Connect to an external pullup resistor. Reset changes from high to low
5 Reset O whenever the monitored voltage (VCC) drops below the reset threshold voltage (VRTH). Once VCC exceeds
VRTH, Reset remains low for the reset time-out period (tRP) and then goes high.
Copyright © 1999–2016, Texas Instruments Incorporated Submit Documentation Feedback 3

LP3470
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VCC voltage –0.3 6 V
Reset voltage –0.3 6 V
Output current (Reset) 10 mA
Power dissipation (TA = 25°C) (3) 300 mW
Lead temperature (soldering, 5 sec) 260 °C
Junction temperature, TJMAX 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
θJA (junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PDmax = (TJmax − TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower.
6.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Operating voltage 0.5 5.5 V
LP3470 –20 85
TA Operating temperature °C
LP3470I –40 85
6.4 Thermal Information

LP3470
THERMAL METRIC (1) DBV (SOT-23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 171 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 124.8 °C/W
RθJB Junction-to-board thermal resistance 30.9 °C/W
ψJT Junction-to-top characterization parameter 17.9 °C/W
ψJB Junction-to-board characterization parameter 30.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

LP3470
6.5 Electrical Characteristics

Limits and typical numbers are for TJ = 25°C, and VCC = 2.4 V to 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
VCC Operating voltage TJ = –20°C to 85°C 0.5 5.5 V
TJ = 25°C 16
ICC VCC supply current VCC = 4.5 V µA
TJ = –20°C to 85°C 30
LP3470 0.99 × VRTH VRTH 1.01 × VRTH
VRTH Reset threshold voltage TJ = 25°C 0.99 × VRTH VRTH 1.01 × VRTH V
LP3470I
TJ = –40°C to 85°C 0.985 × VRTH 1.015 × VRTH
TJ = 25°C 35
VHYST Hysteresis voltage (3) mV
TJ = –20°C to 85°C 15 65
TJ = 25°C 100
tPD VCC to reset delay VCC falling at 1 mV/µs µs
TJ = –20°C to 85°C 300
TJ = 25°C 2
tRP Reset time-out period (4) C1 = 1 nF ms
TJ = –20°C to 85°C 1 3.5
VCC = 0.5 V, IOL = 30 µA, TJ = –20°C to 85°C 0.1
VCC = 1 V, IOL = 100 µA, TJ = –20°C to 85°C 0.1
VOL Reset output voltage low V
VCC =VRTH − 100 mV, IOL = 4 mA,
0.4
TJ = –20°C to 85°C
R1 External pullup resistor 0.68 20 68 kΩ
TJ = 25°C 0.15 1
ILEAK Reset output leakage current µA
TJ = –20°C to 85°C 6
(1) Minimum and maximum limits in standard typeface are 100% production tested at 25°C. Minimum and maximum limits in full operating
temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's
Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely parametric norm.
(3) VHYST affects the relation between VCC and Reset as shown in the timing diagram.
(4) tRP is programmable by varying the value of the external capacitor (C1) connected to pin SRT. The equation is: tRP = 2000 × C1 (C1 in
µF and tRP in ms).

LP3470
6.6 Typical Characteristics

at TA = 25°C (unless otherwise noted)
Figure 1. ICC vs Temperature Figure 2. ICC vs VCC
Figure 3. VCC to Reset Delay vs Temperature Figure 4. Normalized tRP vs Temperature
Figure 5. Normalized VRTH vs Temperature Figure 6. Transient Rejection

LP3470
Typical Characteristics (continued)

at TA = 25°C (unless otherwise noted)
Figure 7. VHYST vs VRTH Figure 8. VHYST vs Temperature

LP3470
7 Detailed Description
7.1 Overview
The LP3470 micropower voltage supervisory circuit provides a simple solution to monitor the power supplies in
microprocessor and digital systems and provides a reset controlled by the factory-programmed reset threshold
on the VCC supply voltage pin. When the voltage declines below the reset threshold, the reset signal is asserted
and remains asserted for an interval programmed by an external capacitor after VCC has risen above the
threshold voltage. The reset threshold options are 2.63 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V.
7.2 Functional Block Diagram
SRT
LP3470
VCC
VCC1 VREF
Reset
RA
QA
+
_
DELAY
RB
GND
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description

7.3.1 Reset Time-Out Period
The reset time-out period (tRP) is programmable using an external capacitor (C1) connected to pin SRT of
LP3470. A ceramic chip capacitor rated at or above 10 V is sufficient. The reset time-out period (tRP) can be
calculated using Equation 1.
tRP (ms) = 2000 x C1 (µF) (1)
For example a C1 of 100 nF will achieve a tRP of 200 ms. If no delay due to tRP is needed in a certain application,
the pin SRT must be left floating.
7.3.2 Reset Output

In applications like microprocessor (µP) systems, errors might occur in system operation during power up, power
down, or brownout conditions. It is imperative to monitor the power supply voltage to prevent these errors from
occurring.
The LP3470 asserts a reset signal whenever the VCC supply voltage is below a threshold (VRTH) voltage. Reset is
ensured to be a logic low for VCC > 0.5 V. Once VCC exceeds the reset threshold, the reset is kept asserted for a
time period (tRP) programmed by an external capacitor (C1); after this interval Reset goes to logic high. If a
brownout condition occurs (monitored voltage falls below the reset threshold minus a small hysteresis), Reset
goes low. When VCC returns above the reset threshold, Reset remains low for a time period tRP before going to
logic high. Figure 9 shows this behavior.

LP3470
Feature Description (continued)
Figure 9. Reset Output Timing Diagram
7.3.3 Pullup Resistor Selection

The Reset output structure of the LP3470 is a simple open-drain N-channel MOSFET switch. A pullup resistor
(R1) must be connected to VCC.
R1 must be large enough to limit the current through the output MOSFET (Q1) below 10 mA. A resistor value of
more than 680 Ω ensures this. R1 must also be small enough to ensure a logic high while supplying all the
leakage current through the Reset pin. A resistor value of less than 68 kΩ satisfies this condition. A typical pullup
resistor value of 20 kΩ is sufficient in most applications.
7.3.4 Negative-Going VCC Transients

The LP3470 is relatively immune to short duration negative-going VCC transients (glitches). The Typical
Characteristics show the maximum transient duration versus negative transient amplitude (see Figure 6), for
which reset pulses are not generated. This graph shows the maximum pulse width a negative-going VCC
transient may typically have without causing a reset pulse to be issued. As the transient amplitude increases (in
other words, goes farther below the reset threshold), the maximum allowable pulse width decreases. A 0.1-µF
bypass capacitor mounted close to VCC provides additional transient immunity.
7.4 Device Functional Modes

7.4.1 Reset Output Low
When the VCC supply voltage is below a threshold (VRTH) voltage minus a hysteresis (VHYST) voltage, the Reset
pin will output logic low. Reset is ensured to be a logic low for VCC > 0.5 V.
7.4.2 Reset Output High

When the VCC supply voltage exceeds the reset threshold, the Reset is kept asserted for a time period (tRP)
programmed by an external capacitor (C1); after this interval Reset goes to logic high.

LP3470
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The LP3470 is a micropower CMOS voltage supervisor that is ideal for use in battery-powered microprocessor
and other digital systems. It is small in size and provides maximum adjustability for power-on-reset (POR) and
supervisory functions, making it a good solution in a variety of applications. The LP3470 is available in six
standard reset threshold voltage options, and the reset time-out period is adjustable using an external capacitor
providing maximum flexibility in any application. This device can ensure system reliability and ensures that a
connected microprocessor will operate only when a minimum Vin supply is satisfied.
8.2 Typical Application

The LP3470 can be used as a simple supervisor circuit to monitor the input supply to a microprocessor as shown
in Figure 10.
Figure 10. Power-On Reset Circuit
8.2.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input supply voltage 0.5 to 5.5 V
Reset threshold voltage 2.63 V, 2.93 V, 3.08 V, 3.65 V, 4 V, 4.38 V, 4.63 V
External pullup resistor 0.68 to 68 kΩ
External reset time-out period capacitor C1 = 1 nF
Reset time-out period 2 ms

LP3470
8.2.2 Detailed Design Procedure

The minimum application circuit requires the LP3470 Power-On Reset Circuit IC and a pullup resistor connecting
the reset pin to VCC. The reset delay can be programmed with an additional capacitor connected from the SRT
pin to GND. See Reset Time-Out Period and Pullup Resistor Selection for information on choosing specific
values for components.
8.2.3 Application Curves

Two capacitor values for CD (0.1 µF and 1 µF) are used as examples to show the programmability of the output
time delay as shown in Figure 11 and Figure 12.
Figure 11. 0.1-µF Capacitor Programmed Delay Figure 12. 1-µF Capacitor Programmed Delay

LP3470
9 Power Supply Recommendations

The input of the LP3470 is designed to handle up to the supply voltage absolute maximum rating of 6 V. If the
input supply is susceptible to any large transients above the maximum rating, then take extra precautions. An
input capacitor is optional but not required to help avoid false reset output triggers due to noise.
10 Layout
10.1 Layout Guidelines

• Place components as close as possible to the IC
• Keep traces short between the IC and the C1 capacitor to ensure the timing delay is as accurate as possible.
10.2 Layout Example

Figure 13 shows a layout example.
Figure 13. LP3470 Layout Example

LP3470
11 Device and Documentation Support
11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 17-Jan-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LP3470IM5-2.63/NOPB NRND SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 D25C
LP3470IM5-2.75/NOPB NRND SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM D38C
LP3470IM5X-2.63/NOPB NRND SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 D25C
LP3470IM5X-2.83/NOPB NRND SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM D39C
LP3470M5-2.63/NOPB NRND SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM 0 to 0 D25B
LP3470M5X-2.93/NOPB NRND SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM 0 to 0 D26B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3470IM5-2.63/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470IM5X-2.63/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3470M5-2.63/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470M5-2.93/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470M5-3.08/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470M5-4.00/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470M5-4.38/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470M5-4.63/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LP3470M5X-2.93/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3470IM5-2.63/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-2.75/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-2.83/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-2.93/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-3.08/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-3.65/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-4.00/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-4.38/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-4.63/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5-4.8/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470IM5X-2.63/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LP3470M5-2.63/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP3470M5-2.93/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470M5-3.08/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470M5-4.00/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470M5-4.38/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470M5-4.63/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LP3470M5X-2.93/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LP3470M5X-3.08/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LP3470M5X-4.00/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LP3470M5X-4.63/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1 5
2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)
4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
ALTERNATIVE PACKAGE SINGULATION VIEW
4214839/J 02/2024
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/J 02/2024
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/J 02/2024
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Product Sample & Technical Tools & Support &

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LP3470 Voltage Supervisor With Programmable Delay and 1% Reset Threshold

2 Applications For information on available reset threshold voltage

Basic Operating Circuit

Changes from Revision F (March 2013) to Revision G Page

Changes from Revision E (September 2009) to Revision F Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

2 Submit Documentation Feedback Copyright © 1999–2016, Texas Instruments Incorporated

Product Folder Links: LP3470

5 Pin Configuration and Functions

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6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.5 Electrical Characteristics

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6.6 Typical Characteristics

Figure 1. ICC vs Temperature Figure 2. ICC vs VCC

Figure 3. VCC to Reset Delay vs Temperature Figure 4. Normalized tRP vs Temperature

Figure 5. Normalized VRTH vs Temperature Figure 6. Transient Rejection

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Typical Characteristics (continued)

Figure 7. VHYST vs VRTH Figure 8. VHYST vs Temperature

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7.2 Functional Block Diagram

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7.3 Feature Description

7.3.2 Reset Output

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Feature Description (continued)

Figure 9. Reset Output Timing Diagram

7.3.3 Pullup Resistor Selection

7.3.4 Negative-Going VCC Transients

7.4 Device Functional Modes

7.4.2 Reset Output High

Copyright © 1999–2016, Texas Instruments Incorporated Submit Documentation Feedback 9

8 Application and Implementation

8.1 Application Information

8.2 Typical Application

Figure 10. Power-On Reset Circuit

8.2.1 Design Requirements

Table 1. Design Parameters

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8.2.2 Detailed Design Procedure

8.2.3 Application Curves

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9 Power Supply Recommendations

10.1 Layout Guidelines

10.2 Layout Example

Figure 13. LP3470 Layout Example

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11 Device and Documentation Support

11.1 Community Resources