Lab3-Pro1-fix

Procedure 1 Differential amplifier
Comment:
A differential amplifier is designed to amplify the difference between two

input voltages. It is also designed to reject the average between the two input
voltages. The difference between two signals is termed the differential-mode
signal, while the arithmetic average of two signals is termed the common-
mode signal. When only one signal is applied to, or taken from, a differential
input or output, it is termed an unbalanced, single-ended or unipolar input or
output. A balanced signal is a pair of signals whose magnitudes are the same
but whose polarities are opposite. When a balanced signal is applied to, or
taken from, a differential input or output, it is termed a balanced,
doubleended, or bipolar input or output. The common-mode rejection ratio
(CMRR) is the differential-mode gain divided by the common-mode gain.
Set-Up:
Produce the circuit of Fig. E4.1 using the following components: RC1, RC2,
RE = 5.1 k 5% 1/4 W Q1, Q2 = CA3046 npn BJT array
Ground the bases of both Q1 and Q2 by connecting them both to the system
ground. Set PPS1 to +6.0 V and PPSp2 to -6.0 V. Verify that the two power
rails are at 6.0 V. Verify that both Q1 and Q2 are in the forward active
region of operation by measuring the DC voltage on the emitter, base, and
collector terminals of each. Voltages on the collectors of both Q1 and Q2
should be around +3 V. If this is not the case, identify and fix the problem
before proceding further.
Turn the two DC power supplies OFF by setting them to +0.0 V. Configure
the signal generator to produce a 100 mVpp (peak-to-peak) sinewave at 1.0
kHz. Make sure that any DC offset on the signal generator is turned off.
Connect the ground of the signal generator to the system ground of the
circuit. Disconnect the wire shorting the base of Q1 to ground. Connect the
output of the signal generator to the base of Q1, node B1. The base of Q2
(node B2) remains grounded.
Connect a 10 probe to the Ch-1 and Ch-2 inputs of the oscilloscope.
Configure the oscilloscope to display both channels versus time with a 1
ms/div sweep rate. Configure Ch-1 for 50 mV/div and DC coupling, and Ch-
2 for 2 V/div with DC coupling. Trigger the oscilloscope off of the Ch-1
input. Connect both probe ground leads to the system ground, connect the
Ch-1 probe to the input of the signal generator (node B1 in Fig. E4.1), and
connect the Ch-2 probe to the collector of Q1 (node C1 in Fig. E4.1).
Measurement:
Energize the circuit by setting PPS1 to +6.0 V and PPS2 to -6.0 V. You
should observe about 10 cycles of the input and output sinewaves. The
output sinewave, taken from the collector of Q1 should be centered about a
DC level of about 3 V, and it should have an amplitude that is significantly
larger than the amplitude of the input sinewave on Ch-1. Note the polarity of
the output sinewave relative to the signal generator input. Move the Ch-2
probe to the collector of Q2 (node C2 in Fig. E4.1) and again note the
polarity of the output sinewave relative to the signal generator input. You
should observe that the amplitudes of the two signals on C1 and C2 are the
same.
Connecting sinewave (100mVPP, 1kHz) to base of Q1, Base Q2 to ground

Simulation result:
Then, adjust the amplitude of the signal generator so that the output
sinewave is as large as possible, but not yet clipping on either polarity peak.
Calculate the voltage gain of the amplifier by dividing the amplitude of the
output sinewave by the amplitude of the input sinewave and record the result
in your lab notebook. Note that this voltage gain represents that from a
double-ended input to a single-ended output. This is because the input signal
is applied between the bases of the two transistors, but the output is taken
from only one of the collectors. (A double-ended output would have been
taken from between the two collectors.) This voltage gain is the differential
voltage gain of the amplifier.
(VPP=150mV where its start clipping)
Simulation result
Adjust the amplitude of the signal generator until the output sinewave is not
clipped. Increase the frequency of the signal generator until the amplitude of
the output sinewave has fallen to about 70 percent of its initial value at 1
kHz. (1MHz kh ra kết quả), This will probably occur around 1 MHz, so the
oscilloscope and the input signal will need to have their time bases adjusted
together to retain 5-20 complete cycles on the oscilloscope display. Record
in your lab notebook the frequency at which the ratio of the output to input
amplitude has fallen to the 70 percent point. This is the –3 dB bandwidth for
the differential gain of this amplifier.
Next, turn off the PPS power supplies. Disconnect the wire shorting the base
of Q2 to ground and connect the bases of Q1 and Q2 together and to the
signal generator. This will apply a common-mode input signal to the
differential amplifier from which the common mode gain can be determined.
Turn on the PPS power supplies.
Configure the signal generator to produce a 1.0 kHz sinewave with a peak-
to-peak amplitude of 3 Vpp. Adjust both Ch-1 and Ch-2 gains on the
oscilloscope to 2 V/div. Move the Ch-2 probe to and from C1 and C2, noting
the polarity of the output waveforms relative to the signal generator input.
Measure the common-mode gain of the differential amplifier by taking the
ratio of the output amplitude at either C1 or C2 to the input amplitude at
either B1 or B2 and record this in your lab notebook.
Vsine = 3VPP, 1kHz

Simulation result
Using the procedures described previously, measure the –3 Db bandwidth of

the common-mode gain and record this in your lab notebook.
Question 1:
2.42
a. Add = 75 m = 32.2667
740 m
Acc = 1.5 = 0.49333
Add 32.2667
With CMRR = Acc = 0.49333 = 65.40
In decibels (dB) => 20log (65.4) = 36.31
b. Explain why the common-mode gain is approximately 0.5:

We draw small-signal model
From the small-signal model:
vic = ib.r π + ve = ib.[r π + 2(βo+1)REE]

vic
Ib = r π +2( βo+1)REE
The voltage at the emitter is:

2(βo+1)REE
Ve = 2(βo+1).Ib .REE = r π +2( βo+1)REE Vic (1)
We recognize that the (1) is identical to the gain of an emitter-follower with

a resistance of 2REE in its emitter, and therefore emitter node voltage is
approximately equal to the common-mode input signal. (Note that the circuit
has been changed to the current-controlled form of the small-signal model.)
The output voltage at either collector is given by.

−βoRc
Vc1 = Vc2 = −βo .Ib.Rc = r π +2( βo+1)REE Vic
So, the common-mode gain Acc is

Voc −βoRc Rc
Acc = Vic = r π +2( βo+1)REE = - 2 REE (2)
for large βo, the equation (2) is identical to the gain of an inverting amplifier
with a resistance of 2 REE in its emitter and a collector load resistance RC.
By multiplying and dividing Eq. (2) by collector current IC, Eq. (2) can be
rewritten as
Vcc
IcRc Vcc Vcc
Acc = - 2. Ic . REE = 2 = 2(VEE−VBE ) = 2VEE (3)
2 Ie . REE
where it is assumed that αF = αo and IC RC = VCC/2. In Eq. (3) we see that

the common mode gain Acc is determined by the ratio of the two power
supplies, and for symmetrical supplies, Acc = 0.5
Explain why the common-mode gain inverting when no DC offset is applied

from the signal generator.
The differential pair behaves the same as a common-emitter (BJT) amplifier

for differential-mode input signals and the characteristics of the differential
pair with a common-mode input are also similar to those of a common-
emitter amplifier.
And we know that in Common-Emitter amplifier, the input voltage at the

base of the transistor and the output at the collector of the transistor is out of
phase with each other by 180 degrees. So, the common-mode gain inverting
when no DC offset is applied from the signal generator.
c. Suggest a way to increase the CMRR of this differential amplifier.

Hint: think about how ideal the current source RE is and how it might
be improved.
That is the better way to increase the CMRR of this differential amplifier
when we replace using only a resistor Ree by using the circuit below 9 (It has
a BJT connected with three resistors R1 , R 2 , Ree )
The reason why we use this circuit instead of a resistor. Because when we
use this circuit, we can have a better CMRR (Common-Mode Rejection
Ratio) that has the formula:
CMRR=2 gm . Ree
So, if we use this circuit, we have the formula:
β3 RE
Ree equivalent =r 03 ( 1 + )
R th +r π + R E
3
Rth =R1 /¿ R2 when we increase the Ree equivalent and can still provide a
constant I c which make to gmstill constant. That is the best way to increase
the CMRR of this differential amplifier effectively.
By contrast, if you replace this circuit with only a resistor Ree and when we
increase the Ree , gm will decrease.
gm =40 I c
(because Ree increases that can make I c decrease so gm will decrease) that mean
CMRR doesn’t change anything.

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Procedure 1 Differential amplifier

A differential amplifier is designed to amplify the difference between two

Connecting sinewave (100mVPP, 1kHz) to base of Q1, Base Q2 to ground

(VPP=150mV where its start clipping)

Vsine = 3VPP, 1kHz

Using the procedures described previously, measure the –3 Db bandwidth of

In decibels (dB) => 20log (65.4) = 36.31

b. Explain why the common-mode gain is approximately 0.5:

vic = ib.r π + ve = ib.[r π + 2(βo+1)REE]

The voltage at the emitter is:

We recognize that the (1) is identical to the gain of an emitter-follower with

The output voltage at either collector is given by.

So, the common-mode gain Acc is

where it is assumed that αF = αo and IC RC = VCC/2. In Eq. (3) we see that

Explain why the common-mode gain inverting when no DC offset is applied

The differential pair behaves the same as a common-emitter (BJT) amplifier

And we know that in Common-Emitter amplifier, the input voltage at the

c. Suggest a way to increase the CMRR of this differential amplifier.

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