VI Semester

TECHNOLOGICAL INNOVATION MANAGEMENT AND

ENTREPRENEURSHIP
Course Code (HSMC) 21EI61/21BM61/21EC61 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 2:2:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Course objectives: This course will enable students to:
• Understand basic skills of Management
• Understand the need for Entrepreneurs and their skills
• Identify the Management functions and Social responsibilities.
• Understand the identification of Business, drafting the Business plan and sources of funding.
Teaching-Learning Process (General Instructions)
The sample strategies, which the teacher can use to accelerate the attainment of the various courseoutcomes are
listed in the following:
• Lecture method (L) does not mean only the traditional lecture method, but a different type ofteaching
method may be adopted to develop the outcomes.
• Show Video/animation films to explain the functioning of various techniques.
• Encourage collaborative (Group) Learning in the class
• Ask at least three HOTS (Higher-order Thinking) questions in the class, which promotes critical thinking
• Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking skills such
as the ability to evaluate, generalize, and analyze information rather than simply recall it.
• Topics will be introduced in multiple representations.
• Show the different ways to solve the same problem and encourage the students to come up withtheir own
creative ways to solve them.
• Discuss how every concept can be applied to the real world - and when that's possible, it helps to improve
the students' understanding.
Module-1
Management: Nature and Functions of Management – Importance, Definition, Management Functions, Levels of
Management, Roles of Manager, Managerial Skills, Management & Administration, Management as a Science, Art &
Profession (Selected topics of Chapter 1, Text 1).
Planning: Planning-Nature, Importance, Types, Steps and Limitations of Planning; Decision Making – Meaning,
Types and Steps in Decision Making( Text 1).
Teaching-Learning Chalk and talk method, Power point presentation, Case studies
Process RBT Level:L2,L3
Module-2
Organizing and Staffing: Organization-Meaning, Characteristics, Process of Organizing, Principles of Organizing,
Span of Management (meaning and importance only), Departmentalization-Process Departmentalization, Purpose
Departmentalization ,Committees– Meaning, Types of Committees.
Staffing-Need and Importance, Recruitment and Selection Process.
Directing and Controlling: Meaning and Requirements of Effective Direction, Giving Orders; Motivation-Nature
of Motivation, Motivation Theories (Maslow’s Need-Hierarchy Theory and Herzberg’s Two Factor Theory);
Communication – Meaning, Importance and Purposes of Communication (Text 1).

Teaching-Learning Chalk and talk method, Power point presentation, Industrial visit
Process RBT Level:L2,L3
Module-3
Leadership-Meaning, Characteristics, Behavioral Approach of Leadership; Coordination-Meaning, Types,
Techniques of Coordination; Controlling – Meaning, Need for Control System, Benefits of Control, Essentials of
Effective Control System, Steps in Control Process ( Text 1).
Social Responsibilities of Business: Meaning of Social Responsibility, Social Responsibilities of Business towards
Different Groups, Social Audit, Business Ethics and Corporate Governance (Text 1).
Teaching-Learning Chalk and talk method, Power point presentation, Field visit to understand present
Process scenario.
RBT Level:L2,L3,L4
Module-4
Entrepreneurship: Introduction, Evolution of the concept of Entrepreneurship, Entrepreneurship today, Types of
Entrepreneurs, Intrapreneurship, Entrepreneurial competencies, Capacity Building for Entrepreneurs.
Identification of Business Opportunities: Introduction, Mobility of Entrepreneurs, Business opportunities in
India, Models for Opportunity Evaluation.

Teaching-Learning Chalk and talk method, Power point presentation, Field visit to understand present
Process scenario.
RBT Level:L2,L3,L4
Module-5
Business plans: Introduction, purpose of a Business plan, contents of a Business plan, presenting a Business plan,
why do some Business plan fail? Procedure for setting up an Enterprise.
Institutions supporting Business opportunities: Central level institutions- National Board for micro, small &
medium Enterprises(NBMSME),MSME-DO, National Small Industries Corporation. State level institutions- state
Directorate Industries and commerce, District Industries Centres, state financial Corporations, State Industrial
Development Corporation(SIDC),State Industrial Area Development Board (SIADB).
Other Institutions - NABARD, Technical consultancy organisation (TCO), Small Industries Development Bank of
India(SIDBI), Export Promotion Councils, Non governmental Organisations.
Teaching-Learning Chalk and talk method, Power point presentation, Case studies
Process RBT Level:L2,L3,L4
Course outcome (Course Skill Set)
At the end of the course the student will be able to :
1. Understand the fundamental concepts of Management and its functions.
2. Understand the different functions to be performed by managers/Entrepreneur.
3. Understand the social responsibilities of a Business.
4. Understand the Concepts of Entrepreneurship and to identify Business opportunities.
5. Understand the components in developing a business plan and awareness about various sources of funding and
Institutions supporting Entrepreneur.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%. The
minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50). A student shall be deemed
to have satisfied the academic requirements and earned the credits allotted to each subject/ course if the student
secures not less than 35% ( 18 Marks out of 50)in the semester-end examination(SEE), and a minimum of 40% (40
marks out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester End Examination)
taken together

Continuous Internal Evaluation:

Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20 Marks (duration
01 hours)
6. At the end of the 13th week of the semester
The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks and will be
scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any of the methods of the
CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per the
outcome defined for the course.

Semester End Examination:

Theory SEE will be conducted by University as per the scheduled timetable, with common question papers for the
subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a maximum of
3 sub-questions), should have a mix of topics under that module.
3. The students have to answer 5 full questions, selecting one full question from each module. Marks scored
out of 100 shall be reduced proportionally to 50 marks.
Suggested Learning Resources:
Text Books:
1. Principles of Management – P.C Tripathi, P.N Reddy, McGraw Hill Education, 6 th Edition, 2017. ISBN-
13:978-93-5260-535-4.
2. Entrepreneurship Development Small Business Enterprises- Poornima M Charantimath,2nd Edition,
Pearson Education 2018, ISBN 978-81-317-6226-4.

Reference Book:
1. Essentials of Management: An International, Innovation and Leadership perspective by Harold Koontz,
Heinz Weihrich McGraw Hill Education, 10th Edition 2016. ISBN- 978-93-392-2286-4.

Web links and Video Lectures (e-Resources):

• https://nptel.ac.in/courses/110107094
• https://nptel.ac.in/courses/110106141
• https://nptel.ac.in/courses/122106031
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
• Industrial visit
• Group discussion
• Role play
• Think pair share activity
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VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication Engineering
NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
VI Semester

Microwave Theory and Antennas

Course Code 21EC62 CIE Marks 50
Teaching Hours/Week (L: T: P: S) (3:0:2:0) SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 12 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Course objectives: This course will enable students to :
1. Describe the microwave properties and its transmission media.
2. Describe the microwave devices for several applications.
3. Understand the basic concepts of antenna theory.
4. Identify antenna types for specific applications.

Teaching-Learning Process (General Instructions)

The sample strategies, which the teacher can use to accelerate the attainment of the various course
outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Ask at least three HOTS (Higher-order Thinking) questions in the class, which promotes critical
thinking
3. Adopt Problem Based Learning (PBL), which fosters students’ analytical skills, develop thinking
skills such as the ability to evaluate, generalize & analyze information rather than simply recall it.
4. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
5. Using videos for demonstration of the fundamental principles to students for better understanding
of concepts.
6. Demonstration of microwave devices and Antennas in the lab environment where students can
study them in real time.

Module-1
Microwave Sources: Introduction, Gunn Diode (Text 2: 7.1,7.1.1,7.1.2)
Microwave transmission lines: Microwave frequencies, Microwave devices, Microwave systems.
Transmission line equations and solutions, Reflection Coefficient and Transmission Coefficient.
Standing wave and standing wave ratio. Smith chart, Single stub matching.
Text 2: 0.1, 0.2, 0.3, 3.1, 3.2, 3.3, 3.5, 3.6 (except double stub matching)

Teaching-Learning Chalk and Talk would be helpful for the quantitative analysis. Videos of the Basic
Process principles of the devices would help students to grasp better.
RBT Level: L1, L2, L3
Module-2
A Closer Look at Methods and classes: Overloading methods, Using objects as parameters, Returning
Microwave Network Theory: Introduction, S matrix representation of multi-port networks (Text 1: 6.1,
6.3, 6.3.1, 6.3.2)
Microwave passive devices: Coaxial connectors and Adapters, Attenuators, Phase shifters, waveguide
Tees, Magic Tee, Circulator, Isolator. (Text 1: 6.4.2, 6.4.14, 6.4.15, 6.4.16, 6.4.17 A, B)
Teaching-Learning Chalk and Talk, PowerPoint Presentation

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Process RBT Level: L1, L2, L3

Module-3
Strip Lines: Introduction, Microstrip lines, Parallel Strip lines (Text 2: 11.1,11.2)
Antenna Basics: Introduction, Basic Antenna Parameters, Patterns, Beam Area, Radiation Intensity, Beam
efficiency, Directivity and Gain, Antenna Aperture Effective height, Bandwidth, Radio communication Link,
Antenna Field Zones (Text 3: 2.1-2.7, 2.9-2.11, 2.13).
Teaching-Learning Chalk and talk method, Power point presentation and videos.
Process RBT Level: L1, L2, L3
Module-4
Point sources and arrays: Introduction, Point Sources, Power patterns, Power theorem, Radiation
Intensity, Arrays of 2 isotropic point sources, Pattern multiplication, Linear arrays of n Isotropic sources
of equal amplitude and Spacing. (Text 3: 5.1-5.6, 5.9, 5.13)
Electric Dipole: Introduction, Short Electric dipole, Fields of a short dipole. Radiation resistance of a short
dipole. Thin linear antenna (field analysis). (Text 3: 6.1-6.5)
Teaching-Learning Chalk and Talk, PowerPoint Presentation
Process RBT Level: L1, L2, L3
Module-5
Loop and Horn antenna: Introduction: Small loop, Comparison of far fields of small loop and Short
dipole. Radiation resistance of small loop, Horn Antennas, Rectangular antennas. (Text 3: 7.1,7.2, 7.4, 7.6,
7.7, 7.8, 7.19, 7.20)
Antenna Types: The Helix geometry, Helix modes, Practical design consideration for mono-filar axial
mode Helical Antenna, Yagi Uda array, Parabolic Reflector (Text 3: 8.3, 8.4, 8.5, 8.8, 9.5)
Teaching-Learning Chalk and Talk, PowerPoint Presentation
Process RBT Level: L1, L2, L3

PRACTICAL COMPONENT OF IPCC

Sl.No Experiments
1 Study of characteristics of Magic Tee.
2 Coupling and Isolation characteristics of microstrip directional coupler.
3 Determination of power division of microstrip power divider.
4 Determination of resonance characteristics of microstrip ring resonator and computation of
dielectric constant of the substrate.
5 Measurement of frequency, guide wavelength, power and attenuation in a microwave Test bench.
6 Study of characteristics of E plane Tee / H plane Tee.
7 To measure unknown impedance using Smith chart through test bench setup.
8 Measurement of VSWR and reflection coefficient and attenuation in a microwave test bench
setup.
9 Obtain the radiation pattern of a Yagi-Uda Antenna array and calculate its directivity.
10 Calculate the aperture of a Dipole Antenna.
11 Obtain the near and far fields of a given antenna and compare the fields.
12 Obtain the bandwidth of a given Antenna.

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 30.08.2023

Course Outcomes
At the end of the course the student will be able to:
1. Describe the use and advantages of microwave transmission
2. Analyze various parameters related to transmission lines.
3. Identify microwave devices for several applications.
4. Analyze various antenna parameters and their significance in building the RF system.
5. Identify various antenna configurations for suitable applications.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures not less than 35% (18 Marks out of 50) in the semester-end examination
(SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together
CIE for the theory component of IPCC
Two Tests each of 20 Marks (duration 01 hour)
• First test at the end of 5th week of the semester
• Second test at the end of the 10th week of the semester
Two assignments each of 10 Marks
• First assignment at the end of 4th week of the semester
• Second assignment at the end of 9th week of the semester
Scaled-down marks of two tests and two assignments added will be CIE marks for the theory component
of IPCC for 30 marks.
CIE for the practical component of IPCC
• On completion of every experiment/program in the laboratory, the students shall be evaluated
and marks shall be awarded on the same day. The 15 marks are for conducting the experiment
and preparation of the laboratory record, the other 05 marks shall be for the test conducted at
the end of the semester.
• The CIE marks awarded in the case of the Practical component shall be based on the continuous
evaluation of the laboratory report. Each experiment report can be evaluated for 10 marks.

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Marks of all experiments’ write-ups are added and scaled down to 15 marks.
• The laboratory test (duration 03 hours) at the end of the 15th week of the semester /after
completion of all the experiments (whichever is early) shall be conducted for 50 marks and
scaled down to 05 marks.
Scaled-down marks of write-up evaluations and tests added will be CIE marks for the laboratory
component of IPCC for 20 marks.
SEE for IPCC
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the course (duration 03 hours)
• The question paper will have ten questions. Each question is set for 20 marks.
• There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
• The students have to answer 5 full questions, selecting one full question from each module.
The theory portion of the IPCC shall be for both CIE and SEE, whereas the practical portion will
have a CIE component only. Questions mentioned in the SEE paper shall include questions from
the practical component.
• The minimum marks to be secured in CIE to appear for SEE shall be the 12 (40% of maximum
marks-30) in the theory component and 08 (40% of maximum marks -20) in the practical
component. The laboratory component of the IPCC shall be for CIE only. However, in SEE, the
questions from the laboratory component shall be included. The maximum of 04/05 questions to
be set from the practical component of IPCC, the total marks of all questions should not be more
than the 20 marks.
SEE will be conducted for 100 marks and students shall secure 35% of the maximum marks to qualify in
the SEE. Marks secured will be scaled down to 50.
Suggested Learning Resources:
Text Books:
1. Microwave Engineering -Annapurna Das, Sisir K Das, TMH Publication, 2nd Edition, 2010.
2. Microwave Devices and Circuits – Samuel Y Liao, Pearson Education.
3. Antennas and Wave Propagation -John D Krauss, Ronald J Marhefka, Ahmad S Khan, 4th Edition,
McGraw Hill Education, 2013.
Reference Books:
1. Microwave Engineering -David M Pozar, John Wiley India Pvt Ltd., Pvt Ltd., 3rd edition, 2008.
2. Microwave Engineering-Sushrut Das, Oxford Higher Education, 2nd Edn, 2015.
3. Antennas and Wave Propagation- Harish and Sachidananda, Oxford University Press, 2007.

Web links and Video Lectures (e-Resources):

• https://www.tutorialspoint.com/antenna_theory/antenna_theory_horn.html
• http://www.antenna-theory.com/antennas/smallLoop.php

Activity Based Learning (Suggested Activities in Class)/ Practical Based learning

Quizzes, Seminars

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03.10.2022

VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication Engineering
NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
VI Semester

VLSI Design and Testing

Course Code 21EC63 CIE Marks 50
Teaching Hours/Week (L:T:P:S) 3:0:0:1 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 3 Exam Hours 3
Course objectives:
 Impart knowledge of MOS transistor theory and CMOS technology
 Learn the operation principles and analysis of inverter circuits.
 Infer the operation of Semiconductor memory circuits.
 Demonstrate the concept of CMOS testing.
Teaching-Learning Process (General Instructions)
The sample strategies, which the teacher can use to accelerate the attainment of the various course
outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Arrange visits to nearby PSUs and industries.
3. Show Video/animation films to explain the functioning of various fabrication & testing techniques.
4. Encourage collaborative (Group) Learning in the class
5. Topics will be introduced in multiple representations.
6. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
Module-1
Introduction: A Brief History, MOS Transistors, CMOS Logic (1.1 to 1.4 of TEXT1)
MOS Transistor Theory: Introduction, Long-channel I-V Characteristics, Non-ideal I-V Effects, DC
Transfer Characteristics (2.1, 2.2, 2.4 and 2.5 of TEXT1).
Teaching-Learning Chalk and talk method, PowerPoint Presentation, YouTube videos, Videos on
Process transistor working
Self-study topics: MOSFET Scaling and Small-Geometry Effects
RBT Level: L1, L2, L3
Module-2
Fabrication: CMOS Fabrication and Layout, Introduction, CMOS Technologies, Layout Design Rules, (1.5
and 3.1 to 3.3 of TEXT1).
Delay: Introduction, Transient Response, RC Delay Model, Linear Delay Model, Logical Efforts of Paths
(4.1 to 4.5 of TEXT1, except sub-sections 4.3.7, 4.4.5, 4.4.6, 4.5.5 and 4.5.6).
Teaching-Learning Chalk and talk method, Power point presentation, YouTube videos, Videos on
Process fabrication
Self-study topics: Layouts of complex design using Euler’s method
RBT Level: L1, L2, L3
Module-3
Semiconductor Memories: Introduction, Dynamic Random Access Memory (DRAM) and Static Random
Access Memory (SRAM), Nonvolatile Memory, Flash Memory, Ferroelectric Random Access Memory
(FRAM) (10.1 to 10.6 of TEXT2)
Teaching-Learning Chalk and talk method, PowerPoint Presentation, YouTube videos on Standard
03.10.2022

Process cell memory Design

Self-study topics: Memory array design
RBT Level: L1, L2, L3
Module-4
Faults in digital circuits: Failures and faults, Modelling of faults, Temporary faults
Test generation for combinational logic circuits: Fault diagnosis of digital circuits, test generation
techniques for combinational circuits, Detection of multiple faults in combinational logic circuits.
(1.1 to 1.3, 2.1 to 2.3 of TEXT3)
Teaching-Learning Chalk and talk method, PowerPoint Presentation, YouTube videos, videos on
Process testing algorithms for test generation
Self-study topics: Testable combinational logic circuits
RBT Level: L1, L2, L3
Module-5
Test generation for sequential circuits: Testing of sequential circuits as iterative combinational
circuits, state table verification, test generation based on circuits structure, functional fault models, test
generation based on functional fault models.
Design of testable sequential circuits: Controllability and Observability, Adhoc design rules, design of
diagnosable sequential circuits, The scan path technique, LSSD, Random Access scan technique, partial
scan.
(4.1 to 4.5, 5.1 to 5.7 of TEXT3)
Teaching-Learning Chalk and talk method/Power point presentation, YouTube videos
Process Self-study topics: Memory testing techniques
RBT Level: L1, L2, L3
Course outcomes (Course Skill Set)
At the end of the course the student will be able to:
1. Demonstrate understanding of MOS transistor theory, CMOS fabrication flow and technology
scaling.
2. Draw the basic gates using the stick and layout diagram with the knowledge of physical design
aspects.
3. Interpret memory elements along with timing considerations.
4. Interpret testing and testability issues in combinational logic design.
5. Interpret testing and testability issues in combinational logic design.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20
03.10.2022

Marks (duration 01 hours)

6. At the end of the 13th week of the semester
The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks
and will be scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any of the
methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module..Marks scored
out of 100 shall be reduced proportionally to 50 marks

Suggested Learning Resources:

Text Books:
1. “CMOS VLSI Design- A Circuits and Systems Perspective”, Neil H E Weste, and David Money Harris 4 th
Edition, Pearson Education.
2. “CMOS Digital Integrated Circuits: Analysis and Design”, Sung Mo Kang & Yosuf Leblebici, Third
Edition, Tata McGraw-Hill.
3. “Digital Circuit Testing and Testability”, Lala Parag K, New York, Academic Press, 1997.
Reference Books:
1. “Basic VLSI Design”, Douglas A Pucknell, Kamran Eshraghian, 3rd Edition, Prentice Hall of India
publication, 2005.
2. “Essential of Electronic Testing for Digital, Memory and Mixed Signal Circuits”, Vishwani D Agarwal,
Springer, 2002.
Web links and Video Lectures (e-Resources)
 https://www.youtube.com/watch?v=oL8SKNxEaHs&list=PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUmM
 https://www.youtube.com/watch?v=lRpt1fCHd8Y&list=PLCmoXVuSEVHlEJi3SwdyJ4EICffuyqpjk
 https://www.youtube.com/watch?v=yLqLD8Y4-Qc
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
 Model displayed for clear understanding of fabrication process of MOS transistor
 Practise session can be held to understand the significance of various layers in MOS process, with
the help of coloured layouts
03.10.2022

VI Semester
Cryptography
Course Code 21EC642 CIE Marks 50
Teaching Hours/Week (L:T:P:S) 2:2:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 3 Exam Hours 3
Course objectives:
This course will enable students to:
 Preparation: To prepare students with fundamental knowledge/ overview in the field of Information
Security with knowledge of mathematical concepts required for cryptography.
 Core Competence: To equip students with a basic foundation of Cryptography by delivering the
basics of symmetric key and public key cryptography and design of pseudo random sequence
generation technique
Teaching-Learning Process (General Instructions)
The sample strategies, which the teacher can use to accelerate the attainment of the various course
outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Show Video/animation films to explain the different Cryptographic Techniques / Algorithms
3. Encourage collaborative (Group) Learning in the class
4. Ask at least three HOTS (Higher order Thinking) questions in the class, which promotes critical
thinking
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop thinking
skills such as the ability to evaluate, generalize, and analyze information rather than simply recall
it.
6. Topics will be introduced in a multiple representation.
7. Show the different ways to solve the same problem and encourage the students to come up with
their own creative ways to solve them.
8. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
9. Adopt Flipped class technique by sharing the materials / Sample Videos prior to the class and have
discussions on the that topic in the succeeding classes
10. Give Programming Assignments
Module-1
Basic Concepts of Number Theory and Finite Fields: Divisibility and The Division Algorithm
Euclidean algorithm, Modular arithmetic, Groups, Rings and Fields, Finite fields of the form GF(p),
Polynomial Arithmetic, Finite Fields of the Form GF(2m) (Text 1: Chapter 3)
Teaching- Chalk and Talk, YouTube videos, Flipped Class Technique
Learning Programming on implementation of Euclidean algorithm, multiplicative inverse, Finite
Process fields of the form GF(p), construction of finite field over GF(2 m).
RBT Level: L1, L2, L3
Module-2
Introduction: Computer Security Concepts, A Model for Network Security (Text 1: Chapter 1)
Classical Encryption Techniques: Symmetric cipher model, Substitution techniques, Transposition
techniques (Text 1: Chapter 1)
Teaching- Chalk and Talk, YouTube videos, Flipped Class Technique and PPTs.
Learning Programming on Substitution and Transposition techniques.
Process Self-study topics: Security Mechanisms, Services and Attacks.
RBT Level: L1, L2, L3
Module-3
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Block Ciphers: Traditional Block Cipher structure, Data encryption standard (DES) (Text 1: Chapter 2:
Section1, 2) The AES Cipher. (Text 1: Chapter 4: Section 2, 3, 4)
More on Number Theory: Prime Numbers, Fermat’s and Euler’s theorem, discrete logarithm. (Text 1:
Chapter 7: Section 1, 2, 5)
Teaching- Chalk and Talk, YouTube videos, Flipped Class Technique and PPTs.
Learning Implementation of SDES using programming languages like C++/Python/Java/Scilab.
Process Self-study topics: DES S-Box- Linear and differential attacks
RBT Level: L1, L2, L3
Module-4
ASYMMETRIC CIPHERS: Principles of Public-Key Cryptosystems, The RSA algorithm, Diffie - Hellman
Key Exchange, Elliptic Curve Arithmetic, Elliptic Curve Cryptography (Text 1: Chapter 8, Chapter 9:
Section 1, 3, 4)
Teaching- Chalk and Talk, YouTube videos, Flipped Class Technique and PPTs.
Learning Implementation of Asymmetric key algorithms using programming languages like
Process C++/Python/Java/Scilab
Numerical examples on Elliptic Curve Cryptography
RBT Level: L1, L2, L3
Module-5
Pseudo-Random-Sequence Generators and Stream Ciphers:
Linear Congruential Generators, Linear Feedback Shift Registers, Design and analysis of stream
ciphers, Stream ciphers using LFSRs, A5, Hughes XPD/KPD, Nanoteq, Rambutan, Additive generators,
Gifford, Algorithm M, PKZIP (Text 2: Chapter 16)
Teaching- Chalk and Talk, YouTube videos, Flipped Class Technique and PPTs.
Learning Implementation of simple stream ciphers using programming languages like
Process C++/Python/Java/Scilab.
RBT Level: L1, L2, L3
Course outcomes (Course Skill Set)
At the end of the course the student will be able to:
1. Explain traditional cryptographic algorithms of encryption and decryption process.
2. Use symmetric and asymmetric cryptography algorithms to encrypt and decrypt the data.
3. Apply concepts of modern algebra in cryptography algorithms.
4. Design pseudo random sequence generation algorithms for stream cipher systems.

Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks out of 50). A student
shall be deemed to have satisfied the academic requirements and earned the credits allotted to each
subject/ course if the student secures not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous
Internal Evaluation) and SEE (Semester End Examination) taken together.

Continuous Internal Evaluation:

Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20
Marks (duration 01 hours)
6. At the end of the 13th week of the semester
03.10.2022

The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks
and will be scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any of the
methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper is designed to attain the different levels of Bloom’s taxonomy as per
the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module.. Marks scored
out of 100 shall be reduced proportionally to 50 marks

Suggested Learning Resources:

Text Books:
1. William Stallings , “Cryptography and Network Security Principles and Practice”, Pearson Education
Inc., 6th Edition, 2014, ISBN: 978-93-325-1877-3
2. Bruce Schneier, “Applied Cryptography Protocols, Algorithms, and Source code in C”, Wiley
Publications, 2nd Edition, ISBN: 9971-51-348-X.

Reference Books:
1. Cryptography and Network Security, Behrouz A Forouzan, TMH, 2007.
2. Cryptography and Network Security, Atul Kahate, TMH, 2003.
Web links and Video Lectures (e-Resources)
 https://nptel.ac.in/courses/106105031
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
 Programming Assignments / Mini Projects can be given to improve programming skills
VI Semester

INTRODUCTION TO DATA STRUCTURES

Course Code 21CS651 CIE Marks 50
Teaching Hours/Week (L:T:P: S) 3:0:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 03
Course Learning Objectives

CLO 1. Introduce elementary data structures.

CLO 2. Analyze Linear Data Structures: Stack, Queues, Lists
CLO 3. Analyze Non Linear Data Structures: Trees
CLO 4. Assess appropriate data structure during program development/Problem Solving.
Teaching-Learning Process (General Instructions)

These are sample Strategies, which teachers can use to accelerate the attainment of the various course
outcomes.
1. Lecturer method (L) need not to be only a traditional lecture method, but alternative
effective teaching methods could be adopted to attain the outcomes.
2. Use of Video/Animation to explain functioning of various concepts.
3. Encourage collaborative (Group Learning) Learning in the class.
4. Ask at least three HOT (Higher order Thinking) questions in the class, which promotes
critical thinking.
5. Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
design thinking skills such as the ability to design, evaluate, generalize, and analyze
information rather than simply recall it.
6. Introduce Topics in manifold representations.
7. Show the different ways to solve the same problem with different circuits/logic and
encourage the students to come up with their own creative ways to solve them.
Discuss how every concept can be applied to the real world - and when that's possible, it helps improve
the students' understanding.
Module-1
Introduction:
Introduction to arrays: one-dimensional arrays, two dimensional arrays, initializing two dimensional
arrays, Multidimensional arrays.
Introduction to Pointers: Pointer concepts, accessing variables through pointers, Dynamic memory
allocation, pointers applications.
Introduction to structures and unions: Declaring structures, Giving values to members, structure
initialization, arrays of structures, nested structure, unions, size of structures.

Textbook 1: Ch 8.3 to 8.15,Ch 12.3 to 12.19

Textbook 2:Ch 2.1 to2.13,2.51 ,2.80 to 2.98
Teaching-Learning Process Chalk and board, Active Learning
Module-2
Linear Data Structures-Stacks and queues:
Introduction, Stack representation in Memory, Stack Operations, Stack Implementation, Applications of
Stack. Introduction, Queues-Basic concept, Logical representation of Queues, Queue Operations and its
types, Queue Implementation, Applications of Queue.

Textbook 2: Ch 6.1 to 6.14 ,Ch 8.1,8.2

Teaching-Learning Process Chalk and board, Active Learning, Problem Based Learning
Module-3
Linear Data Structures-Linked List:
Introduction, Linked list Basic concept, Logical representation of Linked list, Self-Referential structure,
Singly-linked List Operations and Implementation, Circular Linked List, applications of Linked list.
Textbook 1: Ch 15.1 ,15.3,15.4,15.8
Textbook 2: Ch 9.2.9.5
Teaching-Learning Process Chalk and board, Active Learning, Problem based learning
Module-4
Non Linear Data Structures – Trees
Introduction, Basic concept, Binary Tree and its types, Binary Tree Representation, Binary Tree
Traversal, Binary Search tree, Expression Trees.

Textbook1: Ch 16.1,16.2
Textbook2:Ch 10.1,10.2,10.4,10.6.3
Teaching-Learning Process Chalk& board, Active Learning, Problem based learning
Module-5
Sorting and Searching
Sorting: Introduction, Bubble sort, Selection sort, Insertion sort
Searching: Introduction, Linear search, Binary search.

Textbook1: Ch 17.1,17.2.2, 17.2.4, 17.3.1,17.3.2

Textbook2: Ch 11.1.,11.2,11.3,11.7,11.10.1,11.10.2
Teaching-Learning Process Chalk and board, Active Learning, Problem based learning
Course Outcomes
At the end of the course the student will be able to:
CO 1. Express the fundamentals of static and dynamic data structure.
CO 2. Summarize the various types of data structure with their operations.
CO 3. Interpret various searching and sorting techniques.
CO 4. Choose appropriate data structure in problem solving.
CO 5. Develop all data structures in a high level language for problem solving.
Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is 50%.
The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall be
deemed to have satisfied the academic requirements and earned the credits allotted to each subject/
course if the student secures not less than 35% (18 Marks out of 50) in the semester-end examination
(SEE), and a minimum of 40% (40 marks out of 100) in the sum total of the CIE (Continuous Internal
Evaluation) and SEE (Semester End Examination) taken together
Continuous Internal Evaluation:
Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for 20
Marks (duration 01 hours)
6. At the end of the 13th week of the semester
The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100 marks
and will be scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any of the
methods of the CIE. Each method of CIE should have a different syllabus portion of the course).
CIE methods /question paper has to be designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common question
papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks. Marks scored
shall be proportionally reduced to 50 marks
2. There will be 2 questions from each module. Each of the two questions under a module (with a
maximum of 3 sub-questions), should have a mix of topics under that module.

The students have to answer 5 full questions, selecting one full question from each module.
Suggested Learning Resources:
Textbooks
1. C Programming and data structures, E Balaguruswamy 4 th Edition, 2007, McGraw Hill
2. Systematic approach to Data structures using C, A M Padma Reddy, 7thEdition 2007, Sri Nandi
Publications.
References
1. Ellis Horowitz and Sartaj Sahni, Fundamentals of Data Structures in C, 2 nd Ed, Universities
Press, 2014.
2. Seymour Lipschutz, Data Structures Schaum’s Outlines, Revised 1st Ed, McGraw Hill, 2014.
Weblinks and Video Lectures (e-Resources):
1. https://www.youtube.com/watch?v=DFpWCl_49i0
2. https://www.youtube.com/watch?v=x7t_-ULoAZM
3. https://www.youtube.com/watch?v=I37kGX-nZEI
4. https://www.youtube.com/watch?v=XuCbpw6Bj1U
5. https://www.youtube.com/watch?v=R9PTBwOzceo
6. https://www.youtube.com/watch?v=qH6yxkw0u78
Activity Based Learning (Suggested Activities in Class)/ Practical Based learning
Demonstration of projects developed using Linear/Non-linear data structures
03.10.2022

VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELAGAVI

B.E: Electronics & Communication Engineering / B.E: Electronics & Telecommunication Engineering
NEP, Outcome Based Education (OBE) and Choice Based Credit System (CBCS)
(Effective from the academic year 2021 – 22)
VI Semester

VLSI Laboratory
Course Code 21ECL66 CIE Marks 50
Teaching Hours/Week (L: T: P: S) 0:0:2:0 SEE Marks 50
Credits 1 Exam Hours 3
Course objectives:
This laboratory course enables students to
 Design, model, simulate and verify digital circuits.
 Design layouts and perform physical verification of CMOS digital circuits.
 Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level netlist.
 Perform RTL-GDSII flow and understand the stages in ASIC.
Sl.No. Experiments
ASIC Digital Design
1 4-Bit Adder
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required

2 4-Bit Booth Multiplier

• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required

3 32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for ALU
Behavioral Modeling
• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path

4 Latch and Flip-Flop

 Synthesize the design and compare the synthesis report (D, SR, JK)

ASIC Analog Design

5 a) Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
Inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology.
Carry out the following:
03.10.2022

i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns
and the time period of 20ns and plot the input voltage and output voltage of designed
inverter?
ii. From the simulation result compute tpHL, tpLH and td for all three geometrical
settings of width?
iii. Tabulate the results of delay and find the best geometry for minimum delay for CMOS
inverter?
b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC
and LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
6 a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NAND gate and also find
out the delay td for all four possible combinations of input vectors. Table the results. Increase
the drive strength to 2X and 4X and tabulate the results.
b) Draw the layout of NAND with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC
and LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
7 a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its
transient response and AC response? Measure the Unit Gain Bandwidth (UGB), amplification
factor by varying transistor geometries, study the impact of variation in width to UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC & LVS,
extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

8 a) Capture schematics of two-stage operational amplifier and measure the following:

i. UGB
ii. dB Bandwidth
iii. Gain Margin and phase margin with and without coupling capacitance
iv. Use the op-amp in the inverting and non-inverting configuration and verify its
functionality.
v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the
stage wise transistor geometries and record the observations.
b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained
in part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform
post layout simulations, compare the results with pre-layout simulations. Record the
observations.
Demonstration Experiments ( For CIE )
9 UART
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path
10 For synthesized netlist carry out the following:
• Floor planning
• Placement and Routing
• Record the parameters such as no. of metal layers used for routing, flip method for placement
of standard cells
• Physical Verification and record the DRC and LVS reports
• Generate GDSII
 03.10.2022

11 Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
• Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract parasitic
and perform post layout simulations, compare the results with pre-layout simulations. Record the
observations.
Course outcomes (Course Skill Set):
On the completion of this laboratory course, the students will be able to:
1. Design and simulate combinational and sequential digital circuits using Verilog HDL.
2. Understand the synthesis process of digital circuits using EDA tool.
3. Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level netlist.
4. Design and simulate basic CMOS circuits like inverter, common source amplifier, differential
amplifier, SRAM.
5. Perform RTL_GDSII flow and understand the stages in ASIC design.
Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE) is
50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A student shall
be deemed to have satisfied the academic requirements and earned the credits allotted to each course.
The student has to secure not less than 35% (18 Marks out of 50) in the semester-end examination
(SEE).
Continuous Internal Evaluation (CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment to be evaluated for conduction with observation sheet and record write-up. Rubrics
for the evaluation of the journal/write-up for hardware/software experiments designed by the
faculty who is handling the laboratory session and is made known to students at the beginning of the
practical session.
 Record should contain all the specified experiments in the syllabus and each experiment write-up will
be evaluated for 10 marks.
 Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8th week
of the semester and the second test shall be conducted after the 14 th week of the semester.
 In each test, test write-up, conduction of experiment, acceptable result, and procedural knowledge
will carry a weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and learning ability.
Rubrics suggested in Annexure-II of Regulation book
 The average of 02 tests is scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests is
the total CIE marks scored by the student.
Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed by
the University
 All laboratory experiments are to be included for practical examination.
 (Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR based on the course requirement evaluation rubrics shall be
 03.10.2022

decided jointly by examiners.

 Students can pick one question (experiment) from the questions lot prepared by the internal /external
examiners jointly.
 Evaluation of test write-up/ conduction procedure and result/viva will be conducted jointly by
examiners.
 General rubrics suggested for SEE are mentioned here, writeup-20%, Conduction procedure and result
in -60%, Viva-voce 20% of maximum marks. SEE for practical shall be evaluated for 100 marks and
scored marks shall be scaled down to 50 marks (however, based on course type, rubrics shall be
decided by the examiners).
Change of experiment is allowed only once and 15% Marks allotted to the procedure part to be made
zero.
The duration of SEE is 03 hours.
Rubrics suggested in Annexure-II of Regulation book