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Digital CMOS Project

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24 views

Digital CMOS Project

Uploaded by

ahmed1916713
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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College of Science and Engineering

Faculty of Electronics and Communication Engineering

CMOS Digital Circuits Design

It is required to implemnet either a NOR or NAND gate on Cadence.


The report should contain:
1. Schematic
2. Symbol
3. Testbench
4. Layout
5. Layout checks (DRC,LVS)
6. PEX
7. Post layout simulation
Requirements:
• Each Student should submit the Report that includes all your work on the
Moodle
• You are required to bring a Hardware copy of the report to the discussion
• Maximum 2 students can work in groups
• The discussion will be during your tutorials (28/12/2022 and 29/12/2022) or
you could discuss in the assembly on Monday 2/1/2023.
• Plagiarism of any form is subject to getting a grade F in the course.
NAND Gate Schematic NOR Gate Schematic

Gnd

Hints:
In the Schematic:
• The bulks of the PMOS transistors will be connected to the VDD
while the Bulks of the NMOS transistors will be connected to the
ground
In the test bench simulation:
• The NOR or the NAND gate has 2 inputs (A, B); one of the inputs
should be with double period of the second input. Ex. (period of
A=2*period of B)
In the Layout:
• The layout will include 4 MOSFETs, the 2 MOSFETs connected to
input A will be near to the output port
• The 4 MOSFETs should be aligned as the shown in the below
figure
• The figure is reference for the layout design.
• During adding the bulk to the MOSFET in the layout; choose either
integred or detached for the body-tie left
• Choose Integred if the bulk of the MOSFET is connected to its
source or choose detached if the bulk of the MOSFET is not
connected the source.

Layout

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