‫جامعة مصر الدولية‬

Misr International University

Faculty of Engineering Science and Arts

Electronics and Communication Department

CMOS Digital Circuits Design

CMOS Report – NAND Gate

Designed by:

Ahmed Fikry – 2019/16713

Moaz Tarek – 2019/16682

Supervised:

Dr. Hassan El-Ghitani

Eng. Esraa Nashaat

pg. 1
 ‫جامعة مصر الدولية‬
Misr International University

Table of Contents
Introduction ............................................................................................ 3
Transistor: ............................................................................................ 3
Metal-Oxide Semiconductor transistors (MOS): .................................. 3
Logic gates:............................................................................................. 4
NAND gate: ......................................................................................... 4
Implementation ....................................................................................... 5
Schematic Entry: .................................................................................. 5
Testbench: ............................................................................................ 7
Layout ................................................................................................... 10
Implementation: ................................................................................. 10
Validation:......................................................................................... 12
Parasitic Extraction & Post Layout Simulation: ................................. 14
Conclusion ............................................................................................ 15

pg. 2
 ‫جامعة مصر الدولية‬
Misr International University

Introduction
In the middle of 20th century, the new technique of transistor leads
to an “Industry revolution”. So, this report discusses what is the
transistor, types of MOS, Logic gates and gives an example which is
NAND gate.

Transistor:

A transistor is a miniature semiconductor that regulates or controls

current or voltage flow in addition amplifying and generating these
electrical signals and acting as a switch/gate for them. Typically,
transistors consist of three layers, or terminals, of a semiconductor
material, each of which can carry a current.

Metal-Oxide Semiconductor transistors (MOS):

The metal-oxide semiconductor field-effect transistor (MOSFET) is

the most common type of field-effect transistor (FET). They act as
electrical switches and amplifiers controlling the amount of electricity that
can flow between the source and drain terminals based on
the voltage applied to the gate
terminal. There are two
different type of CMOS, the
variation is depending on the
chosen channel to work with
such as PMOS and NMOS.

pg. 3
 ‫جامعة مصر الدولية‬
Misr International University

PMOS is one in which p-type dopants are used in the gate region.
NMOS is one in which n-type dopants are used in the gate region.

Logic gates:
The Logic gates are used to carry out logical operations using single
or multiple binary inputs and a single binary output. The input and output
of a logic gate are based on certain logic, which is explained using
Boolean algebra. Boolean algebra uses only two variables zero or one.
The most basic type of logic gates are OR gate, AND gate and NOT gate.
In addition to the basic logic gate, there are combination gates like NAND
gate, NOR gate, XOR gate, etc made by combining basic logic gates in
different ways.

NAND gate:
The NAND gate or “NotAND” gate is the combination of two basic
logic gates, the AND gate and the NOT gate connected in series. The
NAND gate and NOR gate can be called
the universal gates since the combination
of these gates can be used to accomplish
any of the basic operations. Hence,
NAND gate and NOR gate combination
can produce an inverter, an OR gate or an
AND gate.

pg. 4
 ‫جامعة مصر الدولية‬
Misr International University

The output of a NAND gate is high when either of the inputs is high or if
both the inputs are low. In other words, the output is always high and goes
low only when both the inputs are high. The logic NAND function is given
by the Boolean expression in the next figure (C):

Implementation
Schematic Entry:
This section is implementing the NAND gate using CMOS transistors.
The design is static which means it is consists of Pull Up network and Pull
Down_network.
The Pull Up network consists of two PMOS connected in parallel but he
Pull Down network is consists of two NMOS connected in series. To keep
the design working with its best performance. So, we set the size of the
PMOS with width = 600n, length = 60n and the size of the NMOS with
width = 400n, length = 60n for each transistor, respectively.

pg. 5
 ‫جامعة مصر الدولية‬
Misr International University

Setting the width and length for the Setting the width and length for the
PMOS transistor. NMOS transistor.
Figure (1) Figure (2)

pg. 6
 ‫جامعة مصر الدولية‬
Misr International University

The Schematic of NAND gate

Testbench:

In this section we need to test the design by adding two inputs (a, b)
then figure out the output DC & Transient response to check out that the
design is working correctly.

pg. 7
 ‫جامعة مصر الدولية‬
Misr International University

DC input
Setting the DC voltage with vc

DC Output

pg. 8
 ‫جامعة مصر الدولية‬
Misr International University

Setting the Transient Input

Side-Notes:
Voltage 1: the lower voltage level
Voltage 2: the higher voltage level
Period: the whole duration/
the complete cycle.
Rise time: the time needed change
from voltage.1 level to voltage.2
level, also controls the shape of
the pulse.
Fall time: the time needed change
from voltage.2 level to voltage.1
level, also controls the shape of
the pulse.
Pulse width: the time duration
when the volt is high.
Stop time: sets 1µs (200n * 5) to
see five completed cycles on graph

The Input values are the same in variable “a” and “b”
except the pule width. We put “a” with 100n sec and “b”
with 50n sec to make the output clear and demonstrate the
function of the NAND gate, clearly.
pg. 9
 ‫جامعة مصر الدولية‬
Misr International University

Transient Output

Layout

Implementation:

Layout is the stage to deal with the masks, in other words, the type of
materials that build the CMOS transistor itself and its connection with the
high tension (VDD), ground (GND) and the other transistors.

pg. 10
 ‫جامعة مصر الدولية‬
Misr International University

1st step

2nd step

pg. 11
 ‫جامعة مصر الدولية‬
Misr International University

Connection step

Validation:
After implementing the NAND gate transistors system, the time of
this stage has come. This stage is to check what we have done till now by
using two different methods which are [DRC – LVS].

Design Role Check (DRC):

By using this method, we check if there is any error happened during

layout implementation such as Errors with type (.A or .S) because we use
only “poly”.

Layout vs Schematic:

By using this method, we check that the functionality of the Layout on the
same page with the schematic function which is the NAND gate here.
pg. 12
 ‫جامعة مصر الدولية‬
Misr International University

DRC window

LVS window

pg. 13
 ‫جامعة مصر الدولية‬
Misr International University

Parasitic Extraction & Post Layout Simulation:

According to we implement by using the PMOS and NMOS transistors,

there are some parasitic capacitors comes out due to the “npn junction”.
Therefore, in this stage, we improve our design by removing these
parasitic from the design. Then, we post the layout simulation to check
that the design is still working correctly after removing the parasitic.
Indeed, we expect some delay between the outputs due to the parasitic.

Parasitic Extraction (PEX)

 Removing the yellow border on the small boxes her:

pg. 14
 ‫جامعة مصر الدولية‬
Misr International University
PEX layout result
 To check if there is an acceptable delay or not:

Conclusion

To sum up, transistor is the small unit of technology. Logic gate is an

example on what CMOS could do i.e. NAND gate. CMOS consists of
Metal-Oxide semiconductors connected using the poly dioxide silicon
and masks such as m1. To design any CMOS digital circuits, you need
to implemented through schematic stage and Layout stage to keep sure
that the target you want could be applicable to manufacture it.

pg. 15