EE 309

ANALOG ELECTRONICS and

DESIGN
Yasa Ekşioğlu Özok

E-mail: yasa.eksioglu@altinbas.edu.tr
 TEXT Book:

• Microelectronics Circuit Analysis and Design

Donald A. Neamen -McGrawHill, 4e,2009

Reference Book

• Microelectronic Circuits
Sedra Smith and Kenneth C. Smith-Oxford University
Press, 6/e, 2010.

Altınbaş Üniversitesi Yasa Ekşioğlu Özok yasa.eksioglu@altinbas.edu.tr EE 309 ANALOG ELECTRONICS and DESIGN
 COURSE CONTENTS:
❑ Semiconductors Materials and Diodes

❑ Diode Circuits

❑ The Field-Effect Transistor (FET)

❑ Basic FET Amplifiers

❑ The Bipolar junction Transistor

Altınbaş Üniversitesi Yasa Ekşioğlu Özok yasa.eksioglu@altinbas.edu.tr EE 309 ANALOG ELECTRONICS and DESIGN
 THE FIELD-EFFECT
TRANSISTOR
▪ Introduce the structure of MOSFETs.

▪ Operation, and characteristics of MOSFETs.

Chapter 3
▪ NMOS (n-channel MOSFET) and PMOS (p-channel

MOSFET)

▪ Non-ideal Current–Voltage Characteristics of

MOSFET

▪ DC analysis of MOSFET circuits

Altınbaş Üniversitesi Yasa Ekşioğlu Özok yasa.eksioglu@altinbas.edu.tr EE 309 ANALOG ELECTRONICS and DESIGN
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
▪ Basic concept of FET is known since 1930s
▪ The device was developed in 1960s.
▪ Since 1970s, a particular FET named as Metal Oxide Semiconductor Field
Effect Transistor (MOSFET) has become very popular.
▪ MOSFET’s is a three-terminal semiconductor devices.
▪ They can be used as signal amplifier, digital logic and switch.
▪ In the MOSFET, the current is controlled by an electric field applied
perpendicular to both the semiconductor surface and to the direction of
current. The phenomenon is called the field effect. It is used to modulate
the conductance of a semiconductor, or control the current in a
semiconductor.
▪ The basic principle is to use the voltage between two terminals to control
the current flowing in the third terminal.

5
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
The heart of the MOSFET is the metal-oxide-semiconductor (MOS)
capacitor shown in Figure.

The basic MOS capacitor structure

The metal may be aluminum or some other type of metal. In most cases,
the metal is replaced by a high-conductivity polycrystalline silicon layer
deposited on the oxide.
𝑡0𝑥 : is the thickness of the oxide and
𝜀0𝑥 : is the oxide permittivity.
6
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
The physics of the MOS structure can be explained with the aid of a
simple parallel-plate capacitor.

• Figure (a) shows a parallel-plate capacitor with the top plate at a

negative voltage with respect to the bottom plate. An insulator material
separates the two plates. With this bias, a negative charge exists on
the top plate, a positive charge exists on the bottom plate, and an
electric field is induced between the two plates
• A MOS capacitor with a p-type semiconductor substrate is shown in
Figure (b). The top metal terminal, also called the gate, is at a negative
voltage with respect to the semiconductor substrate. If the electric field
penetrates the semiconductor, the holes in the p-type semiconductor
will experience a force toward the oxide-semiconductor interface.
7
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

A parallel-plate capacitor, a corresponding MOS capacitor with the MOS capacitor with an
showing the electric field a negative gate bias, showing the accumulation layer of holes
and conductor charges, electric field and charge flow

• The equilibrium distribution of charge in the MOS capacitor with this

particular applied voltage is shown in Figure (c). An accumulation
layer of positively charged holes at the oxide-semiconductor
interface corresponds to the positive charge on the bottom “plate” of
the MOS capacitor.
8
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

• Figure (a) shows the same MOS capacitor, but with the polarity of the applied
voltage reversed. A positive charge now exists on the top metal plate and the
induced electric field is in the opposite direction. In this case, if the electric field
penetrates the semiconductor, holes in the p-type material will experience a
force away from the oxide-semiconductor interface. As the holes are pushed
away from the interface, a negative space-charge region is created, because of
the fixed acceptor impurity atoms. The negative charge in the induced
depletion region corresponds to the negative charge on the bottom “plate” of
the MOS capacitor.

effect of positive gate bias, the MOS capacitor with the MOS capacitor with an
showing the electric field and an induced space charge induced space-charge region
charge flow region due to a moderate and electron inversion layer due
positive gate bias to a larger positive gate bias

• Figure (b) shows the equilibrium distribution of charge in the MOS capacitor
with this applied voltage.
9
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

effect of positive gate bias, the MOS capacitor with the MOS capacitor with an
showing the electric field and an induced space charge induced space-charge region
charge flow region due to a moderate and electron inversion layer due
positive gate bias to a larger positive gate bias

• When a larger positive voltage is applied to the gate, the magnitude of the
induced electric field increases. Minority carrier electrons are attracted to the
oxide semiconductor interface, as shown in Figure (c). This region of minority
carrier electrons is called an electron inversion layer. The magnitude of the
charge in the inversion layer is a function of the applied gate voltage.

10
 METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
• The same basic charge distributions can be obtained in a MOS capacitor
with an n-type semiconductor substrate. Figure (a) shows this MOS
capacitor structure, with a positive voltage applied to the top gate terminal.
A positive charge is created on the top gate and an electric field is induced
in the direction shown. In this situation, an accumulation layer of electrons
is induced in the n-type semiconductor.

effect of positive gate bias, the MOS capacitor the MOS capacitor
showing the electric field and with an induced with an induced
charge flow space charge space-charge region
region due to a and hole inversion
moderate negative layer due to a larger
gate bias negative gate bias

11
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR
• Figure (b) shows the case when a negative voltage is applied to the gate
terminal. A positive space-charge region is induced in the n-type substrate by
the induced electric field.
• When a larger negative voltage is applied, a region of positive charge is
created at the oxide-semiconductor interface, as shown in Figure (c). Minority
carrier holes are attracted to the oxide semiconductor interface. This region of
minority carrier holes is called a hole inversion layer. The magnitude of the
positive charge in the inversion layer is a function of the applied gate voltage.

the MOS capacitor the MOS capacitor

with an induced with an induced
space charge space-charge region
region due to a and hole inversion
moderate negative layer due to a larger
gate bias negative gate bias

12
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR

The term enhancement mode means that a voltage must be applied to

the gate to create an inversion layer. For the MOS capacitor with a p-type
substrate, a positive gate voltage must be applied to create the electron
inversion layer; for the MOS capacitor with an n-type substrate, a negative
gate voltage must be applied to create the hole inversion layer.

13
n-channel enhancement-type MOSFET
Apply the concepts of an inversion layer charge in a MOS capacitor to create a
transistor.

Transistor Structure
Figure (a) shows a simplified cross section of a MOS field-effect transistor. The gate,
oxide, and p-type substrate regions are the same as those of a MOS capacitor.
In addition, we now have two n-regions, called the source terminal and drain
terminal. The current in a MOSFET is the result of the flow of charge in the
inversion layer, also called the channel region, adjacent to the oxide–
semiconductor interface.
MOS capacitor MOS field-effect transistor

14
 Schematic diagram of an n-channel
an n-channel MOSFET showing
enhancement mode MOSFET
the field oxide and polysilicon gate

• The channel length L is less than 1 μm (10−6 m) and channel width W

are defined on the figure. The oxide thickness 𝑡0𝑥 is typically on the
order of 400 angstroms, or less.
• Figure (b) shows a more detailed cross section of a MOSFET fabricated
into an integrated circuit configuration.
• A thick oxide, called the field oxide, is deposited outside the area in
which the metal interconnect lines are formed.
• The gate material is usually heavily doped polysilicon.
15
 Basic Transistor Operation
• With zero bias applied to the gate, the source and drain terminals are
separated by the p-region, as shown in Figure (a).
• This is equivalent to two back-to-back diodes, as shown in Figure (b).
The current in this case is essentially zero.
• If a large enough positive gate voltage is applied, an electron inversion
layer is created at the oxide–semiconductor interface and this layer
“connects” the n-source to the n-drain

(a) Cross section of the n

(b) equivalent back-to-back cross section after the
channel MOSFET prior to the
diodes between source and formation of an
formation of an electron
drain when the transistor is in electron inversion layer
inversion layer
cutoff
16
 Basic Transistor Operation
• A current can then be generated between the source and drain terminals.
Since a voltage must be applied to the gate to create the inversion
charge, this transistor is called an enhancement-mode MOSFET. Also,
since the carriers in the inversion layer are electrons, this device is also
called an n-channel MOSFET (NMOS).

(a) Cross section of the n

(b) equivalent back-to-back cross section after the
channel MOSFET prior to the
diodes between source and formation of an
formation of an electron
drain when the transistor is in electron inversion layer
inversion layer
cutoff

17
Basic Transistor Operation
• The source terminal supplies carriers that flow through the channel, and
the drain terminal allows the carriers to drain from the channel. For the
n-channel MOSFET, electrons flow from the source to the drain with an
applied drain-to-source voltage

(a) Cross section of the n

(b) equivalent back-to-back cross section after the
channel MOSFET prior to the
diodes between source and formation of an
formation of an electron
drain when the transistor is in electron inversion layer
inversion layer
cutoff

18
Basic Transistor Operation
• The magnitude of the current is a function of the amount of charge in the
inversion layer, which in turn is a function of the applied gate voltage.
Since the gate terminal is separated from the channel by an oxide or
insulator, there is no gate current.
• Similarly, since the channel and substrate are separated by a space-
charge region, there is essentially no current through the substrate.

(a) Cross section of the n

(b) equivalent back-to-back cross section after the
channel MOSFET prior to the
diodes between source and formation of an
formation of an electron
drain when the transistor is in electron inversion layer
inversion layer
cutoff

19
Ideal MOSFET Current–Voltage Characteristics NMOS Device

• The threshold voltage of the n-channel MOSFET, denoted as 𝑉𝑇𝑁 (the

threshold voltage of the n−channel device) defined as the applied gate
voltage needed to create an inversion charge in which the density is
equal to the concentration of majority carriers in the semiconductor
substrate. The threshold voltage is the gate voltage required to “turn
on” the transistor.
• For the n-channel enhancement-mode MOSFET, the threshold voltage
is positive because a positive gate voltage is required to create the
inversion charge.
• If the gate voltage is less than the threshold voltage, the current in the
device is essentially zero.
• If the gate voltage is greater than the threshold voltage, a drain-to-
source current is generated. The gate and drain voltages are measured
with respect to the source.

20
Ideal MOSFET Current–Voltage Characteristics NMOS Device
Figure (a) shows an n-channel enhancement-mode MOSFET with the
source and substrate terminals connected to ground. The gate-to-source
voltage is less than the threshold voltage, and there is a small drain-to-
source voltage. With this bias configuration, there is no electron inversion
layer, the drain-to-substrate pn junction is reverse biased, and the drain
current is zero.

The n-channel enhancement-mode

MOSFET (a) with an applied gate (b) with an applied gate voltage 𝑣𝐺𝑆 >
voltage 𝑣𝐺𝑆 < 𝑉𝑇𝑁 𝑉𝑇𝑁

21
Ideal MOSFET Current–Voltage Characteristics NMOS Device
Figure (b) shows the same MOSFET with an applied gate voltage greater
than the threshold voltage. In this situation, an electron inversion layer is
created and, when a small drain voltage is applied, electrons in the inversion
layer flow from the source to the positive drain terminal. The conventional
current enters the drain and leaves the source terminal. Note that a positive
drain voltage creates a reverse-biased drain-to-substrate pn junction, so
current flows through the channel region and not through a pn junction.

The n-channel enhancement-mode (b) with an applied gate voltage 𝑣𝐺𝑆 >
MOSFET (a) with an applied gate 𝑉𝑇𝑁
voltage 𝑣𝐺𝑆 < 𝑉𝑇𝑁

22
Ideal MOSFET Current–Voltage Characteristics NMOS Device
The 𝑖𝐷 versus 𝑣𝐷𝑆 characteristics for small values of 𝑣𝐷𝑆 are shown in
Figure below.

Plot of 𝑖𝐷 versus 𝑣𝐷𝑆 characteristic for small

values of 𝑣𝐷𝑆 at three 𝑣𝐺𝑆 voltages

When 𝑣𝐺𝑆 < 𝑉𝑇𝑁 , the drain current is zero. When 𝑣𝐺𝑆 is greater than 𝑉𝑇𝑁 ,
the channel inversion charge is formed and the drain current increases with
𝑣𝐷𝑆 .
Then, with a larger gate voltage, a larger inversion charge density is
created, and the drain current is greater for a given value of 𝑣𝐷𝑆 .

23
Ideal MOSFET Current–Voltage Characteristics NMOS Device
Figure (a) shows the basic MOS structure for 𝑣𝐺𝑆 > 𝑉𝑇𝑁 and a small applied
𝑣𝐷𝑆

In the figure, the thickness of the

inversion channel layer qualitatively
indicates the relative charge density,
which for this case is essentially
constant along the entire channel
length.
The 𝑖𝐷 versus 𝑣𝐷𝑆 also shown in the
figure.

24
Ideal MOSFET Current–Voltage Characteristics NMOS Device

Figure (b) shows the situation when 𝑣𝐷𝑆

increases. As the drain voltage increases,
the voltage drop across the oxide near the
drain terminal decreases, which means that
the induced inversion charge density near
the drain also decreases.
The incremental conductance of the
channel at the drain then decreases, which
causes the slope of the 𝑖𝐷 versus 𝑣𝐷𝑆 curve
to decrease. This effect is shown in the
𝑖𝐷 versus 𝑣𝐷𝑆 curve in the figure.

25
Ideal MOSFET Current–Voltage Characteristics NMOS Device

As 𝑣𝐷𝑆 increases to the point where

the potential difference, 𝑣𝐺𝑆 − 𝑣𝐷𝑆
across the oxide at the drain terminal
is equal to 𝑉𝑇𝑁 , the induced inversion
charge density at the drain terminal
is zero in Figure (c).
For this condition, the incremental
channel conductance at the drain is
zero, which means that the slope of
the 𝑖𝐷 versus 𝑣𝐷𝑆 curve is zero.
𝑣𝐺𝑆 − 𝑣𝐷𝑆 = 𝑉𝑇𝑁
𝑣𝐺𝑆 − 𝑣𝐷𝑆 sat = 𝑉𝑇𝑁
or
𝑣𝐷𝑆 sat = 𝑣𝐺𝑆 − 𝑉𝑇𝑁
where 𝑣𝐷𝑆 sat is the drain-to-source voltage that produces zero inversion
charge density at the drain terminal.
26
Ideal MOSFET Current–Voltage Characteristics NMOS Device

When 𝑣𝐷𝑆 becomes larger than 𝑣𝐷𝑆 sat , the

point in the channel at which the inversion
charge is just zero moves toward the source
terminal.
In this case, electrons enter the channel at
the source, travel through the channel
toward the drain, and then, at the point
where the charge goes to zero, are injected
into the space-charge region, where they
are swept by the E-field to the drain contact.
In the ideal MOSFET, the drain current is
constant for 𝑣𝐷𝑆 > 𝑣𝐷𝑆 sat .
This region of the 𝑖𝐷 versus
𝑣𝐷𝑆 characteristic is referred to as the
saturation region, which is shown in Figure
𝑣𝐺𝑆 − 𝑣𝐷𝑆 sat = 𝑉𝑇𝑁 (d).

27
Ideal MOSFET Current–Voltage Characteristics NMOS Device

As the applied gate-to-source voltage changes, the 𝑖𝐷 versus 𝑣𝐷𝑆 curve

changes.

we saw that the initial slope of 𝑖𝐷 versus 𝑣𝐷𝑆 increases as 𝑣𝐺𝑆 increases.
Also, Equation
𝑣𝐷𝑆 sat = 𝑣𝐺𝑆 − 𝑉𝑇𝑁

shows that 𝑣𝐷𝑆 sat is a function of 𝑣𝐺𝑆 . Therefore;

28
Ideal MOSFET Current–Voltage Characteristics NMOS Device

We can generate the family of curves for this n-channel

enhancement mode MOSFET as shown in Figure below

The 𝑣𝐷𝑆 sat voltage is a single point on each of the curves. This point
denotes the transition between the non-saturation region and the saturation
region

29
Ideal MOSFET Current–Voltage Characteristics NMOS Device

For nonsaturation or triode region 𝑣𝐷𝑆 < 𝑣𝐷𝑆 sat

The ideal current–voltage characteristics in this region are described by
the equation
𝑖𝐷 = 𝐾𝑛 2 𝑣𝐺𝑆 − 𝑉𝑇𝑁 𝑣𝐷𝑆 − 𝑣𝐷𝑆 2
For saturation region 𝑣𝐷𝑆 > 𝑣𝐷𝑆 (sat)
The ideal current–voltage characteristics in this region are described by
the equation
In the saturation region, the incremental or
𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁 2
small-signal resistance is infinite 𝑟0 = ∞

𝑲𝒏 conduction parameter for the n-channel device

𝑊𝜇𝑛 𝐶𝑜𝑥
𝐾𝑛 = 𝜇𝑛 : electron mobility, 𝑊: channel width, 𝐿: channel length
2𝐿

Oxide capacitance per unit area

𝜖𝑜𝑥
𝐶𝑜𝑥 = 𝜇𝑛 𝐶𝑜𝑥 : process conduction parameter (comes from process)
𝑡𝑜𝑥

30
3 modes of conduction

• Linear region : 𝑣𝐷𝑆 is too small

• Triode region (non-saturation) : 𝑣𝐷𝑆 is smaller than 𝑣𝐷𝑆 (sat)

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥
2 𝐿
2
2(𝑉𝐺𝑆 − 𝑉𝑇𝑁 )𝑉𝐷𝑆 − 𝑉𝐷𝑆 𝑖𝐷 = 𝐾𝑛 2 𝑣𝐺𝑆 − 𝑉𝑇𝑁 𝑣𝐷𝑆 − 𝑣𝐷𝑆 2

• Saturation region : 𝑣𝐷𝑆 is larger than 𝑣𝐷𝑆 (sat)

1 𝑊 2 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝐺𝑆 − 𝑉𝑇𝑁 𝑖𝐷 = 𝐾𝑛 𝑣𝐺𝑆 − 𝑉𝑇𝑁
2 𝐿

31
Ex 1: Consider an n-channel enhancement-mode MOSFET with the
following parameters: 𝑉𝑇𝑁 = 0.4𝑉, 𝑊 = 20𝜇𝑚, 𝐿 = 0.8𝜇𝑚, 𝜇𝑛 = 650𝑐𝑚2 /𝑉-s,
𝑡𝑜𝑥 = 200𝐴0 , and 𝜖𝑜𝑥 = (3.9)(8.85 × 10−14 )𝐹/𝑐𝑚.
Determine the current when the transistor is biased in the saturation region
for
(a) 𝑣𝐺𝑆 = 0.8 𝑉
(b) 𝑣𝐺𝑆 = 1.6 𝑉

32
Ex 1:

33
p-channel enhancement-type MOSFET

Figure shows a simplified cross section of the p-channel

enhancement mode transistor. The substrate is now n-type and the
source and drain areas are p-type.

34
Basic Transistor Operation
▪ The operation of PMOS is the same as that of the NMOS, except
the hole is the charge carrier rather than the electron.
▪ A negative gate bias is required to induce an inversion layer of
holes in the channel region directly under the oxide.
▪ The threshold voltage for the p-channel device is denoted as 𝑉𝑇𝑃
▪ Since the threshold voltage is defined as the gate voltage required
to induce the inversion layer, then 𝑉𝑇𝑃 < 0 for PMOS device.
▪ Once the inversion layer has been created, the p-type source
region is the source of the charge carrier so that holes flow from the
source to the drain.
▪ A negative drain voltage is therefore required to induce an electric
field in the channel forcing the holes to move from the source to the
drain.
▪ The conventional current direction, for the PMOS transistor is into
the source and out of the drain.
▪ The conventional current direction and voltage polarity for the
PMOS device are reversed compared to the NMOS device.

35
Ideal MOSFET Current–Voltage Characteristics PMOS Device
The ideal current–voltage characteristics of the p-channel enhancement
mode device are essentially the same as NMOS device

The saturation point is given by

𝑣𝑆𝐷 sat = 𝑣𝑆𝐺 + 𝑉𝑇𝑃

In the non-saturation region, the current is given by

𝑖𝐷 = 𝐾𝑝 2 𝑣𝑆𝐺 + 𝑉𝑇𝑃 𝑣𝑆𝐷 − 𝑣𝑆𝐷 2

In the saturation region, the current is given by

2
𝑖𝐷 = 𝐾𝑝 𝑣𝑆𝐺 + 𝑉𝑇𝑃

𝑲𝒑 conduction parameter for the p-channel device

𝑊𝜇𝑝 𝐶𝑜𝑥 𝜇𝑝 : hole mobility, 𝑊: channel width, 𝐿: channel length
𝐾𝑝 =
2𝐿
36
Ex 2: Determine the source-to-drain voltage required to bias a p-channel
enhancement mode MOSFET in the saturation region.
Consider an enhancement-mode p-channel MOSFET for which
𝑉𝑇𝑃 = −0.5𝑉, and 𝑖𝐷 = 0.5 𝑚𝐴 𝐾𝑝 = 0.2 𝑚𝐴/𝑉 2

37
Ex 2:

38
Ex 3: For a PMOS device with 𝑉𝑇𝑃 = −1.2𝑉 has a drain current
𝑖𝐷 = 0.5𝑚𝐴 when 𝑉𝑆𝐺 = 3𝑉 and 𝑉𝑆𝐷 = 5𝑉 calculate the drain current when

(a) 𝑉𝑆𝐺 = 2𝑉; 𝑉𝑆𝐷 = 3𝑉 ; and

(b) 𝑉𝑆𝐺 = 5𝑉;𝑉𝑆𝐷 = 2𝑉

39
Ex 3:

40
 Circuit Symbols and Conventions
The conventional circuit symbol for the n-channel enhancement-mode
MOSFET is shown in Figure (a).

• The vertical solid line denotes the gate

electrode, the vertical broken line denotes the
channel (the broken line indicates the device is
enhancement mode), and the separation
between the gate line and channel line denotes
the oxide that insulates the gate from the
channel.
• The polarity of the pn junction between the
substrate and the channel is indicated by the
arrowhead on the body or substrate terminal.
conventional circuit symbol
The direction of the arrowhead indicates the
type of transistor, which in this case is an n-
channel device.

41
Circuit Symbols and Conventions

• Instead of Figure (a), which is conventional circuit symbol, the circuit

symbol for the n channel MOSFET will be used in this textbook is
shown in Figure (b).
• In this symbol, the arrowhead is on the source terminal and it
indicates the direction of current, which for the n-channel device is
out of the source.

circuit symbol that will be used in this textbook

42
Circuit Symbols and Conventions
• In more advanced texts and journal articles, the circuit symbol of the n-
channel MOSFET shown in Figure (c) is generally used.
• The gate terminal is obvious and it is implicitly understood that the “top”
terminal is the drain and the “bottom” terminal is the source.
• The top terminal, in this case the drain, is usually at a more positive
voltage than the bottom terminal.

a simplified circuit symbol used in more advanced texts

43
Circuit Symbols and Conventions
• The conventional circuit symbol for the p-channel enhancement-mode
MOSFET appears in Figure (a).
• The arrowhead direction on the substrate terminal is reversed from that in
the n-channel enhancement-mode device.
• This circuit symbol again shows the four terminal structure of the MOSFET
device.

conventional circuit symbol

44
Circuit Symbols and Conventions

• The circuit symbol for the p-channel enhancement-mode device

shown in Figure (b) will be used in this text.
• The arrowhead is on the source terminal indicating the direction of
the current, which for the p-channel device is into the source
terminal.

circuit symbol that will be used in this text

45
Circuit Symbols and Conventions
• In more advanced texts and journal articles, the circuit symbol of the p-
channel MOSFET shown in Figure (c) is generally used.
• It is implicitly understood that the “top” terminal is the source and the
“bottom” terminal is the drain.
• The top terminal, in this case the source, is normally at a higher
potential than the bottom terminal.

a simplified circuit symbol used in more advanced texts

46
n-Channel Depletion-Mode MOSFET
Figure (a) shows the cross section of an n-channel depletion-mode MOSFET.

Even at zero voltage applied to the gate, the inversion layer exists under the oxide
related of impurities introduced during device fabrication.

Since an n-region connects the n-source and n-drain, a drain-to-source current may
be generated in the channel even with zero gate voltage. The term depletion mode
means that a channel exists even at zero gate voltage. In case of enhancement mode
𝑣𝐺𝑆 is required to enhance channel because it is not initially presented but for
depletion mode we already have the channel.

A negative gate voltage must be applied to the n-channel depletion-mode MOSFET to

turn the device off. 47
n-Channel Depletion-Mode MOSFET
Figure (b) shows the n-channel depletion mode MOSFET with a negative applied
gate-to-source voltage.

A negative gate voltage induces a space-charge (depletion) region under the oxide,
thereby reducing the thickness of the n-channel region.
The reduced thickness decreases the channel conductance, which in turn reduces the
drain current. In other words, negative potential at the gate will repel the electrons in
n-channel towards p-substrate and attract the holes from p-substrate. Electrons and
holes will recombine so available electrons for conduction will decrease.
When the gate voltage is equal to the threshold voltage, which is negative for this
device, the induced space-charge region extends completely through the n-channel
region, and the current goes to zero.
48
n-Channel Depletion-Mode MOSFET
A positive gate voltage creates an electron accumulation layer, as shown
in Figure (c) which increases the drain current. In other words, the
positive potential at gate will attract additional electrons from p-type
substrate, which are minority charge carriers, to a channel. The
conduction current will increase.

The general 𝑖𝐷 versus 𝑉𝐷𝑆 family of curves

for the n-channel depletion mode MOSFET
is shown in Figure

49
p-Channel Depletion-Mode MOSFET
• Figure shows the cross section of a p-channel depletion-mode MOSFET,
as well as the biasing configuration and current direction.

• In the depletion-mode device, a channel region of holes already exists

under the oxide, even with zero gate voltage.
• A positive gate voltage is required to turn the device off. Hence the
threshold voltage of a p-channel depletion-mode MOSFET is positive
(𝑉𝑇𝑃 > 0).

50
51
MOSFET DC CIRCUIT ANALYSIS
Common-Source Circuit

One of the basic MOSFET circuit configurations is called the common-

source circuit.

The source terminal is at ground

potential and is common to both the
input and output portions of the circuit.
The coupling capacitor 𝐶𝐶 acts as an
open circuit to dc but it allows the
signal voltage to be coupled to the
gate of the MOSFET.

An NMOS common source circuit

52
MOSFET DC CIRCUIT ANALYSIS
Common-Source Circuit

The dc equivalent circuit of the NMOS common-source circuit

53
MOSFET DC CIRCUIT ANALYSIS
Common-Source Circuit

The voltage at the gate is given by a voltage divider

Assuming that the gate-to-source voltage is

greater than 𝑉𝑇𝑁 , and that the transistor is biased
in the saturation region, the drain current is

The drain-to-source voltage is

54
Ex 4: Calculate the drain current and drain-to-source voltage of a common
source circuit with an n-channel enhancement-mode MOSFET. Find the power
dissipated in the transistor.
𝑅1 = 30kΩ, 𝑅2 = 20kΩ, 𝑅𝐷 = 20kΩ, 𝑉𝐷𝐷 = 5V, 𝑉𝑇𝑁 = 1V and 𝐾𝑛 = 0.1mA/𝑉 2

55
Ex 4:

𝑃𝑇 = 𝐼𝐷 𝑉𝐷𝑆
𝑃𝑇 = 0.1 3 = 0.3𝑚𝑤

56
Ex 5: The transistor in Figure has parameters 𝑉𝑇𝑁 = 0.35V and
𝐾𝑛 = 25µA/𝑉 2 . The circuit parameters are 𝑉𝐷𝐷 = 2.2V, 𝑅1 = 355kΩ, 𝑅2 =
245kΩ, 𝑅𝐷 = 100kΩ. Find 𝐼𝐷 , 𝑉𝐺𝑆 , 𝑉𝐷𝑆 .

57
Ex 5:

58
MOSFET DC CIRCUIT ANALYSIS
Common-Source Circuit

Figure (a) shows a common-source circuit with a p-channel enhancement

mode MOSFET. The source terminal is tied to +𝑉𝐷𝐷 , which becomes
signal ground in the ac equivalent circuit.

The gate voltage is

the source-to-gate voltage is

the device is biased in the saturation region, the drain

current is given by

source-to-drain voltage is

59
Ex 6: Calculate the drain current and source-to-drain voltage of a common
source circuit with a p-channel enhancement-mode MOSFET.
Consider the circuit shown in Figure. Assume that
𝑅1 = 𝑅2 = 50kΩ, 𝑅𝐷 = 7.5kΩ, 𝑉𝐷𝐷 = 5V, 𝑉𝑇𝑃 = −0.8V and 𝐾𝑝 = 0.2mA/𝑉 2

60
Ex 6:

61
Ex 7: The transistor in Figure has parameters 𝑉𝑇𝑃 = −0.6V,𝐾𝑝 = 0.2mA/𝑉 2 .
The circuit is biased at 𝑉𝐷𝐷 = 3.3V . Assume 𝑅1 //𝑅2 = 300kΩ. 𝐼𝐷𝑄 = 0.5𝑚𝐴 ,
𝑉𝑆𝐷𝑄 = 2.0V. Find 𝑅1 , 𝑅2 , 𝑅𝐷 .

62
Ex 7:

63
Ex 8: The transistor parameters for the transistor in Figure are 𝑉𝑇𝑁 =
𝑊
0.4V,𝑘′𝑛 = 120µA/𝑉 2 , = 50 .
𝐿
a) Determine 𝑉𝐺𝑆 such that 𝐼𝐷 = 0.35𝑚𝐴
b) Determine 𝑉𝐷𝑆 and 𝑉𝐷𝑆 (sat)

64
Ex 8: 𝑉𝑇𝑁 = 0.4V,
𝑘′𝑛 = 120µA/𝑉 2 ,
𝑊
= 50 .
𝐿

𝑉𝐺𝑆 =? , 𝐼𝐷 = 0.35𝑚𝐴
𝑉𝐷𝑆 =? 𝑉𝐷𝑆 𝑠𝑎𝑡 =?

65