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Aug 31 2019

Final Exam

45 24 21 0 53.33% 60:00 24
Questions Right Wrong Unattended Accuracy Time Taken Marks Scored

View rank list (https://elearn.maven-silicon.com/report/assessment/103)

Topics No.of Qns Right Wrong Unattended Accuracy Remarks

Design Flow 5 3 2 0 60% Needs Improvement

Digital Electronics 20 10 10 0 50% Needs Improvement

Of ine
OFFER

Verilog 20 11 9 0 55% Needs Improvement

Easy
Questions

Right Answers 24

Wrong Answers 21

Unattended 0

Medium
Questions

Right Answers 0

Wrong Answers 0

Unattended 0

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Hard
Questions

Right Answers 0

Wrong Answers 0

Unattended 0

All questions

Compare (https://elearn.maven-silicon.com/report/assessment/103)

Showing 45 of 45 questions
OFFER

1 Single choice

The design flow in VLSI Systems is in which order?

1. Architecture Design
2. Market requirement
3. Verification
4. HDL coding

a) 2–1–4–3 b) 4–1–3–2
c) 3–2–1–4 d) 1–2–3–4
e) 3–1–2–4

Your answer a Right Time Taken 30s Marks 1 Answer Explanation

2 Single choice

Gate level Simulation is to ensure that, _______________

a) Both RTL and Gate level netlist hav b) the synthesis tool has no bugs in it’s
e same no. of input & output lines implementation
c) Both RTL & Gate level netlist are e d) All of the above.
quivalent in terms of functionality

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e) None of the above.

Your answer c Right Time Taken 15s Marks 1 Answer Explanation

3 Single choice

The structures like H – tree and I- tree are used for ____________

a) Increasing the clock slew rate b) Increasing the speed of the circuit
c) Minimizing the clock skew effect d) All of the above.
e) None of the above.

Your answer b Wrong Right answer c Time Taken 17s Marks 0 Answer Explanation
OFFER

4 Single choice

The Layout Vs Schematic (LVS) is done to ensure that, __________

a) The functionality of schematic and b) Layout occupies lesser silicon area

Layout are equivalent
c) Layout is drawn by considering all t d) All of the above
he design rules.
e) None of the above

Your answer c Wrong Right answer a Time Taken 57s Marks 0 Answer Explanation

5 Single choice

While defining specification for designing ASIC’s, we need to include _______

a) Input & Output specification b) Power requirements

c) Speed requirements d) All of the above
e) None of the above

Your answer d Right Time Taken 14s Marks 1 Answer Explanation

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6 Single choice

Find the radix (512/41)r = (12) r

a) 0 b) 6
c) 8 d) 9
e) none of these

Your answer c Right Time Taken 115s Marks 1 Answer Explanation

7 Single choice

(10000)16 – (1001)16 is

a) EFFF b) 00111
OFFER

c) both a and b d) 01000

e) none of these

Your answer a Right Time Taken 129s Marks 1 Answer Explanation

8 Single choice

Which of the expression are equivalent to A^B^C^D?

i. F(A,B,C,D)=∑(1,2,4,7,8,11,13,14)
ii. F(A,B,C,D)=∑(3,5,7,10,11,12,13,14)
iii. F(A,B,C,D)=π(0,3,5,6,9,10,12,15)
iv. F(A,B,C,D)=π(0,1,2,4,6,8,9,15)

a) ii and iii b) iv and i

c) ii and iv d) i and iii
e) None of the above

Your answer d Right Time Taken 106s Marks 1 Answer Explanation

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9 Single choice

The Boolean expression for shaded area in Venn Diagram is _________

a) X’+Y’+Z b) XY’Z+X’YZ
c) X+Y+Z d) X’Y’Z+XY
e) None of the above
OFFER

Your answer b Wrong Right answer d Time Taken 239s Marks 0 Answer Explanation

10 Single choice

Design the circuit to get X output with the help of the following waveform. A and B are
Inputs of ____________?

a) OR Gate b) AND Gate

c) XOR Gate d) XNOR Gate
e) None of the above

Your answer a Right Time Taken 54s Marks 1 Answer Explanation

11 Single choice

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A 32 bit ripple carry adder is realized using 32 identical full adders (FA). The carry
propagation delay of each FA is 10 ns and the sum propagation delay of each FA is 15 ns.
Worst case delay of this 32 bit adder is ___________

a) 325ns b) 480ns
c) Both can be right d) 400ns
e) None of the above

Your answer b Wrong Right answer a Time Taken 76s Marks 0 Answer Explanation

12 Single choice

A priority encoder is an encoder circuit with priority. If 2 or more inputs are equal to 1,
the input with the highest priority will take precedence. The truth table of a 4-input
priority encoder is shown below. An output V is added which is set to1 when one or more
OFFER

inputs are equal to 1; otherwise V is 0. The two outputs x and y are not inspected when V
equals 0 and hence they are specified as don′t care outputs. Note that whereas x′s in
output columns represent don′t care outputs, the x′s in the input columns are useful for
representing a truth table in compact form. For example, input X100 represents the 2
input combinations: 0100 and 1100. The simplified SOP expressions for Y is_____.

a) D0+D2D1’ b) D1D2+D2D4’
c) D0+D4D3’ d) D1+D2D3’
e) None of the above

Your answer b Wrong Right answer a Time Taken 145s Marks 0 Answer Explanation

13 Single choice

How many 4 to 1 multiplexers are required to implement 100 to 1 multiplexer?

a) 33 b) 34
c) 32 d) 36
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e) None of the above

Your answer b Wrong Right answer a Time Taken 45s Marks 0 Answer Explanation

14 Single choice

How many minimum nor gates are required to implement function?

a) 6 b) 7
c) 8 d) 9
OFFER

e) None of the above

Your answer a Wrong Right answer b Time Taken 136s Marks 0 Answer Explanation

15 Single choice

Product-of-Sums expressions can be implemented using __________

a) 2-level OR-AND logic circuits b) 2-level NOR logic circuits

c) 2-level XOR logic circuits d) Both 2-level OR-AND and NOR log
ic circuits
e) None of the above

Your answer d Right Time Taken 122s Marks 1 Answer Explanation

16 Single choice

The circuit below forms a ÷2 counter. If the inverter has a propagation delay of 5 ns and
the propagation delay, setup time and hold time of the ip op are 8 ns, 4 ns and 2 ns
respectively, calculate the highest clock frequency for reliable operation.

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a) 58.8MHz b) 68.8MHz

c) 49.8MHz d) 53.8MHz

e) None of the above

Your answer a Right Time Taken 169s Marks 1 Answer Explanation

OFFER

17 Single choice

A latch can be constructed from an OR gate, an AND gate, and an inverter connected as
follows:

What restriction must be placed on R and H so that P will always equal Q′ (under steady-
state conditions)?

a) 00 b) 01
c) 10 d) 11
e) None of the above

Your answer c Right Time Taken 135s Marks 1 Answer Explanation

18 Single choice

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Consider the synchronous sequential circuit shown below. Which states are not reachable
from initial state S4 (Q0, Q1, Q2) = 100? What is the modulus of the counter?

a) 5 b) 6
c) 7 d) 4
e) None of the above

Your answer a Wrong Right answer c Time Taken 157s Marks 0 Answer Explanation
OFFER

19 Single choice

How many address bits are required for a 4096-bit memory organized as a 512 × 8, bit
addressable memory?

a) 12 address lines b) 2^9 address lines

c) 9 address lines d) 2^12 address lines
e) None of the above

Your answer a Right Time Taken 40s Marks 1 Answer Explanation

20 Single choice

Assume that a 4-bit serial in/serial out left shift register is initially clear. We wish to store
the nibble 1100. What will be the output pattern after the fourth clock pulse? (Left-most bit
rst)?

a) 0000 b) 0011

c) 1100 d) 1001

e) None of the above

Your answer a Wrong Right answer b Time Taken 52s Marks 0 Answer Explanation

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21 Single choice

Consider the synchronous sequential circuit shown below.

Which states are not reachable from initial state S5(Q0, Q1, Q2) = 101?

a) 000,011,100 and 111are not reachable b) 000,010,100 and 111are not reachable

c) 000,011,110 and 111are not reachable d) 000,011,101 and 111are not reachable
OFFER

e) None of the above

Your answer c Wrong Right answer e Time Taken 245s Marks 0 Answer Explanation

22 Single choice

How many address bits are required for a 4096 KB memory which has a data width
capacity of 16 bits?

a) 21 address lines b) 12 address lines

c) 10 address lines d) 18 address lines
e) None of the above

Your answer c Wrong Right answer a Time Taken 149s Marks 0 Answer Explanation

23 Single choice

What is the modulus of the 6-bit ring counter ?

a) 2 b) 4

c) 6 d) 12

e) None of the above

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Your answer c Right Time Taken 9s Marks 1 Answer Explanation

24 Single choice

Which of the following is right with respect to the given FSM?

a) to detect overlapping sequence “101 b) to detect non overlapping sequence

01” “10101”
c) to detect non overlapping sequence d) to detect non overlapping sequence
“1010” “1011”
none of the above
OFFER

e)

Your answer a Right Time Taken 152s Marks 1 Answer Explanation

25 Single choice

What is the minimum number of states required to design a Moore FSM with input as a
bit stream, and o/p which goes 1 whenever the number received so far is divisible by 3?

a) 5 b) 8
c) 3 d) 9
e) None of the above

Your answer a Wrong Right answer c Time Taken 148s Marks 0 Answer Explanation

26 Single choice

Which abstraction level is used by the most of the synthesizer tools?

a) Dataflow level b) Gate level

c) Behavioral level d) RTL level

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e) None of the above

Your answer d Right Time Taken 23s Marks 1 Answer Explanation

27 Single choice

What is an error in the following name based port mapping?

a) One extra comma is given b) There is no error

OFFER

c) Port mapping should be order base d) During port mapping none of the p
d orts should be kept floating
e) None of the above

Your answer a Wrong Right answer d Time Taken 32s Marks 0 Answer Explanation

28 Single choice

What value is stored in the variable “y” after 10ns?

a) -2 b) -6
c) 2’s complement of -6 d) 2147483642
e) None of the above

Your answer b Wrong Right answer d Time Taken 27s Marks 0 Answer Explanation

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29 Single choice

What is the value passed to the port “ain” from the below snippet?

a) 4.3 b) 4
c) 5 d) 0
e) None of the above

Your answer b Right Time Taken 54s Marks 1 Answer Explanation

OFFER

30 Single choice

What is the syntax to access the 4th bit from LSB of an array with size 10x8?

a) array[4] b) array[addr][3]
c) array[addr][4] d) array[addr][8]
e) None of the above

Your answer d Wrong Right answer b Time Taken 44s Marks 0 Answer Explanation

31 Single choice

Which is true from the following statements for Parameters?

a) Parameters are constants which can change anytime. b) Parameters are variables

c) Parameters are global constants. d) All of the above

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e) None of the above

Your answer a Wrong Right answer c Time Taken 18s Marks 0 Answer Explanation

32 Single choice

What is the output of the following snippet?

a) y=1 b) y=0
c) y=x d) y=z
OFFER

e) None of the above

Your answer c Right Time Taken 12s Marks 1 Answer Explanation

33 Single choice

What is the output of the following snippet?

a) y = 3’b001 b) y = 3’b000
c) y = 3’b100 d) y = 3’b111
e) None of the above

Your answer d Wrong Right answer a Time Taken 30s Marks 0 Answer Explanation

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34 Single choice

What is the value of a from the following snippet?

a) a = 4’b00x1 b) a = 4’b0xx1
c) a = 4’bxxx1 d) a = 4’bx0x1
e) None of the above

Your answer b Right Time Taken 71s Marks 1 Answer Explanation

OFFER

35 Single choice

What is the value of a from the following snippet?

a) a = 4’b1101 b) a = 4’b110x
c) a = 4’b1100 d) a = 4’b1111
e) None of the above

Your answer e Wrong Right answer b Time Taken 92s Marks 0 Answer Explanation

36 Single choice

Which is not true from the following statements?

a) Continuous assignments are concurrent b) Continuous assignments are made to Net type only

c) The RHS of a continuous assignments can be reg or wire. d) All of the above

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e) None of above

Your answer a Wrong Right answer e Time Taken 24s Marks 0 Answer Explanation

37 Single choice

Which is true from the following statements?

a) Procedural assignments are made t b) Initial block is non-synthesizable.

o Integers only.
c) Always block will run once. d) All of above
e) None of above

Your answer e Wrong Right answer b Time Taken 63s Marks 0 Answer Explanation
OFFER

38 Single choice

At what time value of a is updated to 6 from the below snippet?

a) 20ns b) 10ns
c) 0ns d) 30ns
e) None of above

Your answer b Right Time Taken 27s Marks 1 Answer Explanation

39 Single choice

At what time value of a is updated to 8 from the below snippet?

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a) 20ns b) 10ns
c) 30ns d) 50ns
e) None of above

Your answer c Right Time Taken 45s Marks 1 Answer Explanation

40 Single choice

At what time value of a is updated to 6 from the below snippet?

OFFER

a) 20ns b) 10ns
c) 30ns d) 50ns
e) None of above

Your answer a Right Time Taken 23s Marks 1 Answer Explanation

41 Single choice

At what time value of a is updated to 8 from the below snippet?

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a) 20ns b) 10ns
c) 0ns d) 30ns
e) None of the above

Your answer b Right Time Taken 69s Marks 1 Answer Explanation

42 Single choice

What type of case the below snippet belongs to?

OFFER

a) Full case b) Parallel case

c) Overlapping case d) Non overlapping case
e) None of the above

Your answer b Right Time Taken 41s Marks 1 Answer Explanation

43 Single choice

For inferring a priority encoder logic, which construct should be used?

a) if-else b) case
c) for loop d) while loop
e) None of the above

Your answer a Right Time Taken 53s Marks 1 Answer Explanation

44 Single choice

For inferring a single Mux logic, which construct should be used?

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a) if-else b) case
c) for loop d) while loop
e) None of the above

Your answer b Right Time Taken 44s Marks 1 Answer Explanation

45 Single choice

In a Moore based FSM, which of the following statement is true?

a) Outputs should be reg type. b) Outputs shouldn’t depend on clock

edge .
c) Glitches can occur in the output. d) All of the above
e) None of the above.
OFFER

Your answer a Wrong Right answer b Time Taken 64s Marks 0 Answer Explanation

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