SRM IST, RAMAPURAM CAMPUS AND plane, while the PAL only has a programmable AND plane

d) The PAL has more possible product terms than the PLA
DEPARTMENT OF ELECTRICAL AND ELECTRONICS
ENGINEERING 6. In an ECL the output is taken from
CYCLE TEST III a) Emitter b) Base c) Collector d) None of the Mentioned
7. Transistor–transistor logic (TTL) is a class of digital circuits built
Sub. Code :15EE206 Date :
from
Sub. Name: Digital System Design MaxMarks: 75 a) Transistors only b) Bipolar junction transistors (BJT)
Year/S II/III Duration : 2 hours c) Resistors d) Bipolar junction transistors (BJT) and resistors.

Answer All Questions 8. Standard TTL circuits operate with a __ volt power supply.
a) 2 b) 4 c) 5 d) 3
PART A – (15x1 = 15 Marks)
9. Which of the following logic families has the shortest
1. PAL refers to
propagation delay?
a) Programmable Array Loaded b) Programmable Logic Array a) CMOS b) BICMOS c)ECL d) TTL
10. The disadvantage of RTL is that
c) Programmable Array Logic d) None of the Mentioned
a) It uses a maximum number of resistors
b) It results in high power dissipation
2. The inputs in the PLD is given through c) High noise creation
d) None of the Mentioned
a) NAND gates b) OR gates c) NOR gates d) AND gates 11. What do VHDL stand for?
a) Verilog hardware description language
3. For programmable logic functions, which type of PLD should be b) VHSIC hardware description language
used? c) very hardware description language
a) PLA b) CPLD c) PAL d) SLD d) VMEbus description language
12. Each unit to be modelled in a VHDL design is known as
4. Which type of device FPGA are? a) behavioural model b) design architecture
a) SLD b) SROM c) EPROM d) PLD c) design entity d) structural model
5. The difference between a PAL & a PLA is 13. Which of the following describes the connections between the entity
a) PALs and PLAs are the same thing port and the local component?
b) The PAL has a programmable OR plane and a programmable a) port map b) one-to-one map
AND plane,while the PLA only has a programmable AND plane c) many-to-one map d) one-to-many maps
c) The PLA has a programmable OR plane and a programmable 14. Among the VHDL features, which language statements are
 executed at the same time in parallel flow? 24.b.i. Write the working of two input TTL NAND GATE (6)
a. Concurrent b. Sequential c. Net-list d. Test-bench
15. In VHDL, which object/s is/are used to connect entities ii. Write short notes on noise margin and propagation delay of logic
together for the model formation? families (6)
a. Constant b. Variable c. Signal d. All of the above
25.a. Discuss the various styles of modelling architecture in VHDL
program with an example
PART B (6*4=24 Marks) OR

Answer Any six Questions 25.b. Write the VHDL program for JK flip flop and for full adder.
26.a. i.Explain about test benches for VHDL programming with example.
16. Write down the comparison between PROM,PLA & PAl.
17. Explain the features of transfer logic ii. Write the VHDL program for 4 bit up counter
18. With a neat diagram, explain the working of CMOS NAND OR
Gate 26.b. Discuss about CMOS NAND and CMOS NOR gate with a suitable
19. Draw the circuit of two input NOR gate using CMOS. diagram
20. Define TTL.
21. Explain the relational operator in Verilog HDL.
22. Write the VHDL code for half adder circuit
23.Write short notes on test bench.

PART C – (3 X 12 = 36 Marks)
Answer ALL the Questions

24.a. Implement the following Boolean function using PLA

F1(A,B,C) = ∑m(0,1,2,4)
F2(A,B,C) = ∑m(0,5,6,7)
OR
 SRM UNIVERSITY, RAMAPURAM CAMPUS 7. TTL is a
a) Current sinking b) Current sourcing
DEPARTMENT OF ELECTRICAL AND ELECTRONICS
ENGINEERING c) Voltage sinking d) Voltage sourcing

CYCLE TEST III 8. Special handling precautions should be taken when working with MOS
devices. Which of the following statements is not one of these
Sub. Code :15EE206 Date : precautions?
a) All test equipment should be grounded.
Sub. Name: Digital System Design Max Marks : 75
b) MOS devices should have their leads shorted together for
Year/ Sem :II/III
shipment and storage.
Duration :2 hours c) Never remove or insert MOS devices with the power on.
d) Workers handling MOS devices should not have grounding
straps attached to their wrists.
Answer All Questions
9. What is the major advantage of ECL logic?
PART A – (15x1 = 15 Marks) a).very high speed b) wide range of operating voltage
c).very low cost d) very high power
1. Logic circuits can also be designed using
a) RAM b) ROM c) PLD d) PLA 10. The primary advantage of RTL technology was that
2. PLA refers to a) It results as low power dissipation
a) Programmable Loaded Array b) Programmable Logic Array b) It uses a minimum number of resistors
c) Programmable Array Logic d) None of the Mentioned c) It uses a minimum number of transistors
d) None of the Mentioned
3. The memory which is used for storing programs and data currently
being processed by the CPU is called 11. What do VHSIC stand for?
a) PROM b) Main Memory a) very high speed integrated chip
c) Non-volatile memory d) Mass memory b) very high sensor integrated chip
c) Verilog system integrated chip
4. PLA contains
d) Verilog speed integrated chip
a) AND and OR arrays b) NAND and OR arrays 12. Which type of simulation mode is used to check the
c) NOT and AND arrays d) NOR and OR arrays timing performance of a design?
5. In FPGA, vertical and horizontal directions are separated by a) Behavioural b) Switch-level
a) A line b) A channel c) A strobe d) A flip-flop c) Transistor-level d) Gate-level
6. Which logic is the fastest of all the lo gic families? 13. Which among the following is a process of transforming
a) TTL b) ECL c) HTL d) DTL design entry information of the circuit into a set of logic
equations?
 a) Simulation b) Optimization Expression (6)
c) Synthesis d) Verification
14. Which type of simulation mode is used to check the timing ii. Write a VHDL code for half adder (6)
performance of a design? OR
a) Behavioural b) Switch-level
c) Transistor-level d) Gate-level 25.b. Explain in detail the the structure of HDL behavioral
15. In VHDL, the mode of port does not define
a) An input b) An Output Descriptions
c) Both input and output d) the type of bit 26.a. Implement the following Boolean function using Pal
PART B – (6 X 4= 24 Marks) W(A,B,C,D) = ∑m(0,2,6,7,8,9,12,13)
Answer Any six Questions X(A,B,C,D) = ∑m(0,2,6,7,8,9,12,13,14)
Y(A,B,C,D) = ∑m(2,3,8,9,10,12,13)
16. Compare PROM, PLA and PAL.
17. Give the difference between TTL & RTL Z(A,B,C,D) = ∑m(1,34,6,9,12,14)
18. Draw and explain three input TTL NAND gate OR
19. Explain the working og CMOS NAND gate
20. Write the VHDL program for full adder 26.b. Write the VHDL code for
21. Write short notes on test bench i. 16:1 multiplexer
22. Explain any two VHDL operators with example
23.Explain process in VHDL with syntax. ii. JK flip flop

PART C – (3 X 12 = 36 Marks)
Answer ALL the Questions
24.a. i.Explain the operation of totem pole TTL logic (6)
ii. Draw and explain CMOS NAND gate (6)
OR
24.b. Design a BCD to Excess -3 code converter and implement
using PLA
25.a. i. Write a VHDL code for 4:1 multiplexer using logic