Semiconductor Memory

Lecture 11
•The memory of a computer system normally consists of one
or more PC boards that are connected to the system bus.

• On each board is a module that is addressed by the

high-order bits on the address bus.

•Most systems include both ROM and RAM modules.

•The memory consists primarily of an interface and an array of

memory IC devices, each of which contains an array of
memory cells with each cell being the circuitry needed to
store 1 bit.
•A memory device is said to be an M x N device if it contains M
groups with each group consisting of N cells.
▪ Similarly, a K x L module is one that consists of K words, each
having L bits.
The principal criteria involved in designing a memory are:

1. Cost.

2. Capacity.

3. Speed.

4. Power consumption.

5. Reliability.

6. Volatility and access capability.

•The cost of a memory module normally consists of two components,
one which is independent of the size of the module and is called
overhead, and one which is proportional to the size and is called the
incremental cost.
•The overhead cost is due primarily to the support and interface
electronics in the module, and the incremental cost is most-closely
related to the cost of the memory devices.
•Both overhead and incremental costs are dependent on the number
of pin connections and the complexity of the board design.
• Therefore, memory devices with large bit capacities and that require
few supporting chips ordinarily have a cost advantage.

•Because the overhead tends to be the same regardless of the

capacity of the module but must be included for each module, it is
generally better to fulfill the overall memory capacity requirement
using as few modules as possible.
• Another factor which enters into the overhead is the cost of the
power supply.
•The fewer the number of supply voltages that are required, the less
complicated-the power supply and board design.
•The speed of a memory is gauged by its access time, which is defined
as the time delay between the receipt of a stable address input and
the data output.
•This time depends on many factors and is even related to the bit
capacity of the memory devices.
•High-speed transistors tend to require more chip space so that fewer
cells can be included on each chip.
• Also, high-speed devices, which are normally made using a bipolar
technology, are more expensive and consume more power.
•Power consumption can be very important in systems that must
sometimes be powered by batteries or solar cells (e.g., space
vehicles).
• The technology used in constructing the IC determines the power
required for each cell.
• The technology most often used in low-power applications is the
complementary metal-oxide semi-conductor (CMOS) technology.
•The main disadvantage associated with CMOS is that fair
amount of chip space is needed for each cell; thus the
capacity of each device is reduced.
•Unfortunately, power consumption and speed tend to be
pro-portional and it is difficult and expensive to achieve
both low power and high speed.
•The technology that has been found to be a good
compromise of speed, power consumption, capacity per
device, and cost is the high-density MOS
(HMOS)technology.
•Because the reliability of an IC is high once it has been
thoroughly tested, the reliability of a module is strongly
related to the number of solder connections and board
complexity. Therefore, reliability increases as the total pin
count de-creases, thus supplying an additional incentive to
minimize the number of memory and supporting devices in
a module.
•Unless an application requires nonvolatility there is no reason to
provide it. If nonvolatile RAM is needed, then either core memory
must be used or backup power must be available so that the volatile
semiconductor memory can be maintained in a powered-up state.
•Nonvolatility and access capability are pretty much dictated by the
application.
•ROM is generally used whenever possible because it is less
expensive, nonvolatile, more reliable, and impervious to noise, and
its simple construction lends itself to high cell density.
 1. Static RAM (SRAM)

• Essentially uses flip-flops to store charge (transistor

circuit)
• As long as power is present, transistors do not lose charge
(no refresh)
• Very fast (no sense circuitry to drive nor charge depletion)
• Complex construction
• Large bit circuit
• Expensive
• Used for Cache RAM because of speed and no need for
large volume
 STATIC RAM DEVICES

❖For static memory devices, a cell is commonly implemented using six MOS
transistors.
❖Information is stored according to the states of transistors Q1 and Q2. This
cross-coupled transistor pair is such that when one transistor is on, the other
is off, and vice versa.
❖A 1 is assigned to the state that exists when Q2 is on and Q1 is off, and a 0 is
assigned to the opposite state.
❖The transistors Q3 and Q4 serve as resistors and Q5 and Q6 act as enable
gates.
❖During a write operation, first the cell is selected by raising the voltage level on the
select line. When this is done, transistors Q5 and Q6 act as short circuits, so that
the Read/Write 1 line is applied to the gate of Q2 and the Read/Write 0 line is
applied to the gate of Q1.
❖To write a 1 into the cell a 1 is placed on Read/Write 1 and a 0 is placed on
Read/Write 0 .
❖This causes Q2 to be turned on and Q1 to be turned off.
❖On the other hand, if a 0 is to be written into the cell, a 1 is placed on Read/Write 0
and a 0 is placed on Read/Write 1.
❖In either case, once they are set the states of Q1 and Q2 will remain
unchanged until the next write operation.
❖The cell can be read simply by applying a voltage to the select line. When this
is done, the state of Q1, is applied to Read/Write 0 and the state of Q2 is
applied to Read/Write 1.
❖A 4K x 8 memory device array which is constructed from 1K x 1 devices
is shown in the following figure.
❖If a chip is enabled, a read or write operation will proceed as specified by R/W
control input.
❖The read/write signal will not be recognized and the output is forced into a
high-impedance state.
❖This allows the data outputs of several memory chips to be directly tied
together so that 2K x 8, 4K x 8; and so on, memories can be constructed from
columns of 1K X 1 chips with each column contributing one bit of the data
byte.
❖When this is done, the bit being output not only depends on the signals on the
address lines, but also depends on receive the chip enable signal.
❖Each row in the array is connected to a row enable line and the row enable
lines are activated by higher-order address bits which for this example are
bits A11 and A10.
❖When a row is selected each device in the row will input or output a bit
according to the signals on the A9-A0 lines.
❖ Because each cell in a static RAM device must contain several transistors,
each device generally contains fewer cells than a dynamic RAM chip of
comparable design.
❖ Also, they tend to use more power since one of the two cross-coupled
transistors is always on, thus consuming power continuously.
❖The major advantage of static RAM is that it does not need to be refreshed.
❖The most important timing parameter to be considered in choosing a
memory device is the access time.
❖The maximum time delay from an address input to a data output is longer
than the delay between a chip enable and a data output, and consequently
the former timing figure is normally considered to be the access time.
❖The access time for commonly used MOS RAMs varies from 50 to 500 ns.
❖For a read operation, once the output data are valid, the address input
cannot be changed immediately to start another read operation.
❖ This is because the device needs a certain amount of time, called read
recovery time, to complete its internal ope€rations before the next memory
operation
❖The sum of the access time and read recovery time is the memory read
cycle time.
❖ This is the time needed between the start of a read operation and the start
of the next memory cycle.
❖The memory write cycle time can be similarly defined and may be different
from the read cycle time.
❖Figure 10-7(a) illustrates the timing of a-memory read cycle.
❖The address is applied at point A, which is the beginning of the read cycle,
and must be held stable during the entire cycle.
❖In order to reduce the aceess time, the chip enable Input should be applied
before point B .
❖ The data output becomes valid after point C and remains valid as long as
the address and chip enable inputs hold. The R/W control input is not shown
in the timing diagram for the read cycle, but should remain high throughout
the entire cycle.
 2. Dynamic RAM (DRAM)

• Bits stored as charge in capacitors

• Simpler construction
• Smaller per bit
• Less expensive
• Slower than SRAM
• Typical application is main memory
• Essentially analogue -- level of charge
determines value
 RAM Cells
Static RAM (SRAM): Dynamic RAM (DRAM):
• The basic element of a static RAM cell is • DRAM stores data in the form of
the D-Latch. electric charges in capacitors.
• Data remains stored in the cell until it is • Charges leak out, thus need to
intentionally modified. refresh data every few ms.
• SRAM is fast (Access time: 1ns). • DRAM is slow (Access time: 60ns).
• SRAM needs more space on the • DRAM needs less space on the
semiconductor chip than DRAM. semiconductor chip than SRAM.
– SRAM more expensive than DRAM – DRAM less expensive than SRAM
– SRAM needs more space than – DRAM needs less space than
DRAM SRAM
• SRAM consumes power only when • DRAM needs to be refreshed
accessed. • DRAM is used as the main memory
• SRAM is used as a Cache

ACOE255
 DYNAMIC RAM DEVICES

❖Just like static RAMs, the memory on a dynamic memory chip is

organized in a matrix formed by rows and columns of memory cells.
❖The simplest type of dynamic RAM cell contains only one transistor and
one capacitor, as shown in Fig. 10-10.
❖Whether a 1 or 0 is contained in a cell is determined by whether or not
there is a charge on the capacitor.
❖During a read operation, one of the row select lines is brought high by
decoding the row address (low-order address bits).
❖ The activated row select line turns on the switch transistors e for all cells
in the selected row.
❖This causes the refresh amplifier associated with each column to sense
the voltage level on the corresponding capacitor and interpret it as a 0 or
a 1.
❖The column address (high-order address bits) enables one cell in the
selected row for the output.
❖During this process, the capacitors in an entire row are disturbed.
❖In order to retain the stored information, the same row of cells is rewritten by the
refresh amplifiers.
❖A write operation is done similarly except that the data input is stored in the
selected cell while the other cells in the same row are simply refreshed.
❖As a result of the storage discharge through pn –junction leakage current,
dynamic memory cells must be repeatedly read and restored.
❖This process is called memory refresh.
❖The storage discharge rate increases as the operating temperature
rises, and the necessary time interval between refreshes ranges from 1 to 100
ms.
❖When operating at 70c, the typical refresh time interval is 2 ms.
❖Although a row of cells is refreshed during a read or write, the randomness of
memory references cannot guarantee that every word in a memory module is
refreshed within the 2-ms time limit.