AXI IP -V Plan

AIonSi
Author: Vyshnavi CH
Date:

AIONSI CONFIDENTIAL & PROPRIETARY-UNDER NDA

 Version Information
S. No Date Author Version Description Issue Change
Name
1. Vyshnavi V1.00 Rs232 system controller
Ch

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S.No Table of Content Page
No.
1 Interface 5
1.1 rs232_syscon_interface 5

2 Features 6
2.1 For WRITE Transaction 6
2.1.1 FIXED BURST TYPE
2.1.2 INCR BURST TYPE
2.1 3 WRAP BURST TYPE
2.2 For READ Transaction 7
2.2.1 FIXED BURST TYPE
2.2.2 INCR BURST TYPE
2.2.3 WRAP BURST TYPE
3 Stimulus 8
3.1 Direct Stimulus
3.2 Random Stimulus
3.3 Constraint Random Stimulus
4 TB Architecture 9
4.1 Block Diagram of axi vip 9
4.2 Architecture Components of axi 9
4.2.1 Top 10
4.2.2 Test 10
4.2.3 Environment 10
4.2.3.1 Scoreboard & Coverage
4.2.3.2 axi_agent
4.2.3.2.1 axi_driver
4.2.3.2.2 axi_monitor
4.2.3.2.3 axi_sequencer
4.2.4 axi_sequence 10

5 Checker 11
5.1 Direct Check 11
5.1.1 Direct check without delay
5.1.2 Direct check with delay
5.2 Reference Logic Check 11
5.2.1 Reference logic check without delay
5.2.1.1 1_x_4_demux_data_out_check
5.2.2 Reference logic check with delay

6 Functional Coverage 12
6.1 Covergroup 12
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 6.1.1 Covergroup write_cg 12
6.1.1.1 Coverpoint AWADDR_cp
6.1.1.2 Coverpoint AWLEN_cp
6.1.1.3 Coverpoint AWSIZE_cp
6.1.1.4 Coverpoint AWBURST_cp
6.1.1.5 Coverpoint AWVALID_cp
6.1.1.6 Coverpoint WLAST_cp
6.1.1.7 Coverpoint WVALID_cp
6.1.1.8 Coverpoint BRESP_cp
6.1.2 Covergroup read_cg 12
6.1.2.1 Coverpoint ARADDR_cp
6.1.2.2 Coverpoint ARLEN_cp
6.1.2.3 Coverpoint ARSIZE_cp
6.1.2.4 Coverpoint ARBURST_cp
6.1.2.5 Coverpoint ARVALID_cp
6.1.2.6 Coverpoint RRESP_cp

7 Assertion 13

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1. Introduction:

o A soft-core implemented in Verilog serving as a serial-port-to-bus interface.

o Primarily designed for debugging system components such as memory, registers,

and peripheral interfaces (e.g., PS/2 mouse/keyboard interfaces).

o Enables on-chip debugging within a “system on a chip” (SOC) design.

2. Interface:
 Interface is a bunch of signals for rs232 system controller
 Here only one interface is required which is rs232_syscon_if, which has all the DUT
signals in it.

2.1 rs232_syscon_if:
 Input to DUT / Output from test bench :

logic clk_i;
logic reset_i;
logic master_bg_i;
logic rs232_rxd_i
logic ack_i
bit [DAT_DIGITS_PP 1:0] dat_io; ///inout port

logic rst_o
logic stb_o
logic cyc_o
logic [ADR_DIGITS_PP -1:0] adr_o;
logic we_o;

 Output from DUT / Input to test bench :

logic master_br_o;
logic err_i
bit [DAT_DIGITS_PP 1:0] dat_io ///inout port

logic rs232_txd_o03

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3. Functionality:
Signal Description

clk_i Clock input (45MHz)

reset_i reset

master_bg_i Bus grant from master

master_br_o Bus request from rs232_syscon

ack_i Wishbone acknowledge signal

err_i Wishbone error signal

stb_o Wishbone strobe signal

cyc_o Wishbone cycle signal

adr_o Address bus {Width of address bus in nibbles (4 =>16bits, 8 => 32 bits)}

dat_io Data bus (tri-state) {Width of data bus in nibbles}

we_o Write enable signal

 Serial BAUD Rate Generation:

o Baud rate: the measure of the number of changes to the signal (per second) that
propagate through a transmission medium.

o Uses an internal signal, serial_clk_16x, which is a clock enable running at 16× the
desired BAUD rate.

o For 115,200 BAUD it is a high pulse which occurs for one single “clk_i” clock period,
at a rate of 16*115200 = 1.8432 MHz(==clk period of serial_clk_16x)

 Command Types:

Command type format function

Write(w) w aaaa dddd qq Writes a hexadecimal value
to a specified address, with
optional quantity (auto-
increments address for
multi-word writes).

Read(r) r aaaa qq Reads a specified quantity

of words starting at a given

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 address.

Initialize(i) i Resets the rs232_syscon

unit (does not reset
peripherals; an explicit i
command is needed).

 Fields in the command line

field default If left out/not specified Command description (considering

for 16bit addr and data width
data Zero assumes the previous If dddd =0005 aaaa=0017
field value. Command=w 17 5
address Zero assumes the previous
field value. If Command,
w 5434540017 66677560005
aaaa = 0017
dddd = 0005
quantity 1 it assumes the value “1,” qq=0 command will do nothing. No
field bus cycles will be generated.

qq>1 the aaaa is automatically

incremented during the subsequent
iterations of the command loop.
dddd remains the same.

 Initial Power-up Display:

o On startup, the module sends the characters “0123456789ABCDEF” to the terminal.

o This display helps verify that the terminal is set to the correct BAUD rate.

 Watchdog Timer:

o Ensures timely bus transactions by monitoring bus request and cycle completion.

o Generates an error message if bus acknowledgment is not received within a preset

number of clock cycles.

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4. Features:
In system controller, we need to verify the following features :

4.1 For WRITE Transaction :

4.1.1 FIXED BURST TYPE

Description: When awburst[1:0] is 2’b00, the address remains the same for every
transfer in the burst.

Steps to implement:
1. Apply random stimulus on wr addr channel with burst type and assert awvalid.
2. Apply random stimulus on wr data channel with random value of wdata and assert
wvalid.
3. When awready and wready has been asserted by the dut, it means dut is ready to accept
the addr and data signals.
4. Assert bready to get the response from dut to indicate the completion of success/failure
of write transaction.

4.1.2 INCR BURST TYPE

Description: When awburst[1:0] is 2’b01, the address for each transfer in the burst is an
increment of the previous transfer address. The increment value depends on the size of the
transfer.

Steps to implement:
1. Apply random stimulus on wr addr channel with burst type incr with control signal
awsize and awlen of any value and assert awvalid.
2. Apply random stimulus on wr data channel with random value of wdata and assert
wvalid.
3. When awready and wready has been asserted by the dut, it means dut is ready to accept
the addr and data signals.

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4. Assert bready to get the response from dut to indicate the completion of success/failure
of write transaction

4.1.3 WRAP BURST TYPE

Description: When awburst[1:0] is 2’b10, the address increments in similar way in incr
burst type but it wraps around to a lower address when a wrap boundary is reached.

Steps to implement:
1. Apply random stimulus on wr addr channel with burst type wrap with the start address
aligned to the size of the transfer & control signal awsize of any value & awlen of
2,4,8,16 only and assert awvalid.
2. Apply random stimulus on wr data channel with random value of wdata and assert
wvalid.
3. When awready and wready has been asserted by the dut, it means dut is ready to accept
the addr and data signals.
4. Assert bready to get the response from dut to indicate the completion of success/failure
of write transaction.

4.2 For READ Transaction :

4.2.1 FIXED BURST TYPE

Description: When arburst[1:0] is 2’b00, the address remains the same for every
transfer in the burst.

Steps to implement:
1. Apply random stimulus on rd addr channel with burst type fixed and assert arvalid.
2. Assert rready signal on rd data channel to indicate that master is ready to accept the
data from dut.
3. Dut retrieves data and places it on rdata signal, at the same time it uses rresp signal to
indicate success or failure of read transaction.

4.2.2 INCR BURST TYPE

Description: When arburst[1:0] is 2’b01, the address for each transfer in the burst is an
increment of the previous transfer address. The increment value depends on the size of the
transfer.

Steps to implement:
1. Apply random stimulus on rd addr channel with burst type incr and assert arvalid.
2. Assert rready signal on rd data channel to indicate that master is ready to accept the
data from dut.

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 3. Dut retrieves data and places it on rdata signal, at the same time it uses rresp signal to
indicate success or failure of read transaction.

4.2.3 WRAP BURST TYPE

Description: When arburst[1:0] is 2’b10, the address increments in similar way in incr
burst type but it wraps around to a lower address when a wrap boundary is reached.

Steps to implement:
1. Apply random stimulus on rd addr channel with burst type fixed and assert arvalid.
2. Assert rready signal on rd data channel to indicate that master is ready to accept the
data from dut.
3. Dut retrieves data and places it on rdata signal, at the same time it uses rresp signal to
indicate success or failure of read transaction

5. Stimulus:

 Stimulus are the input data which is given to the design.

 Stimulus can be passed directly as direct values or as random values depending on
requirement.
 There are classified into three types of stimulus and they are,

5.1 Direct Stimulus:[Yes Required]

 In Direct Stimulus we give the values directly to the stimulus without giving
random values for inputs.
o bit awvalid
o bit wvalid
o bit wlast
o bit bready
o bit arvalid
o bit rready

5.2 Random Stimulus: [Yes Required]

 In random Stimulus we will give random data for input signals.
 Signal to be randomized:
o rand bit [3:0] awid
o rand bit [31:0] awaddr
o rand bit [3:0] wid
o rand bit [31:0] wdata
o rand bit [3:0] arid
o rand bit [31:0] araddr

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 5.3 Constraint Random Stimulus: [Yes Required]
 Constraint Random Stimulus will generate meaningful stimulus for constraints
which we give in the stimulus.

o rand bit [3:0] awlen
o rand bit [2:0] awsize
o rand bit [1:0] awburst
o rand bit [3:0] arlen
o rand bit [2:0] arsize
o rand bit [1:0] airburst

4. TB Architecture:

4.1 Block Diagram of axi vip:

tb_top

axi_if Test axi_DUT

5.
Test
6.

ENV
axi_sequence
axi_scoreboard axi_coverage
Reference logic

axi_agent

axi_sequencer

axi_driver axi_monitor

11

axi_dut
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4.2 Architecture Components of axi:
The following components are needed in architecture to verify the axi IP.
 Top
 Test
 Environment
 Scoreboard
 Coverage
 axi_agent
 axi_driver
 axi_monitor
 axi_sequencer
 axi_sequence
4.2.1 Top :
Top module contains:
 axi_test
 axi_if

4.2.2 Test :
 In Test all the test cases are declared.
 Then, we need to create an environment.

4.2.3 Environment:
 In Environment configuration class we have agent configuration class and
agent.
 We need to create scoreboard, coverage and all agents

4.2.3.1 Scoreboard & Coverage:

 In scoreboard we compare the data from axi_agent’s monitor to verify
whether comparison is successful or not.
 We add Covergroup in coverage to generate 100% functional coverage.

4.2.3.2 axi_agent:
 Create Driver class to drive the input signals.
 Create Monitor class to monitor the input that driver is driving.
 Create Sequencer to transfer data between sequence class and driver.
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 4.2.3.2.1 axi_driver:
 In Driver we drive the data that is generated by sequence, and send
it to DUT by the interface axi_interface.
4.2.3.2.2 axi_monitor:
 Monitor collect the data from DUT using axi_interface and send it
to scoreboard.
4.2.3.2.3 axi_sequencer:
 In sequencer we get the data from sequence and send it to driver to
drive it to DUT.
4.2.4 axi_sequence:
 In Sequence we will generate the data and send it to driver.

5. Checkers:
In checker we compare actual output from design with expected output from monitor
and verify the same.

Checkers are of two types:

 Direct Check
 Reference Logic Check

5.1 Direct Check: [Not Required]

 In direct check, get the data in scoreboard directly from monitors and compare
both monitor data.

In Direct Check there are two types:

5.1.1 Direct check without delay : [Not Required]
 In processing there is no delay so, we go for asynchronous direct check.

5.1.2 Direct check with delay: [Not Required]

 In processing there is a delay so, we go for synchronous direct check.

5.2 Reference Logic Check: [Yes Required]

 In Reference Logic check we compare the actual output from reference logic with
expected output in scoreboard.
 Reference Logic check is used in this 1_x_4_demux IP.

In Reference Logic there are two types:

5.2.1 Reference logic check without delay: [Yes Required]
 By Comparing the data from reference logic which gives the actual output
and data from agent_out monitor which gives the expected output.
 In this about mentioned way checking is verified.
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  In processing there is no delay so, we go for asynchronous check

5.2.1.1 1_x_4_demux_data_out_Check:
 When select line is s0=0,s1=0 then, output y0=data_in
 When select line is s0=0, s1=1 then, output y1=data_in
 When select line is s0=1, s1=0 then, output y2=data_in
 When select line is s0=1, s1=1 then, output y3=data_in

5.2.2 Reference logic check with delay: [Not Required]

 In processing there is a delay so, we go for synchronous check.

6. Functional Coverage: [Yes Required]

For this Ip we need two covergroup for covering the functional coverage part.

6.1Covergroup: [Yes Required]

Covergroup will generate a specification of the coverage model.

6.1.1 Covegroup write_cg:

6.1.1.1 Coverpoint AWADDR_cp:

 When all the required bins are tracked. It will generate 100%
coverage for awaddr.
 Coverpoint AWADDR_cp : awaddr
6.1.1.2 Coverpoint AWLEN_cp:
 When all the required bins are tracked. It will generate 100%
coverage for awlen.
 Coverpoint AWLEN_cp : awlen
6.1.1.3 Coverpoint AWSIZE_cp:
 When all the required bins are tracked. It will generate 100%
coverage for awsize.
 Coverpoint AWSIZE_cp : awsize
6.1.1.4 Coverpoint AWBURST_cp:
 When all the required bins are tracked. It will generate 100%
coverage for awburst.
 Coverpoint AWBURST_cp : awburst
6.1.1.5 Coverpoint AWVALID_cp:
 When all the required bins are tracked. It will generate 100%
coverage for awvalid.
 Coverpoint AWVALID_cp : awvalid
6.1.1.6 Coverpoint WLAST_cp:

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  When all the required bins are tracked. It will generate 100%
coverage for wlast.
 Coverpoint WLAST_cp : wlast
6.1.1.7 Coverpoint WVALID_cp:
 When all the required bins are tracked. It will generate 100%
coverage for wvalid.
 Coverpoint WVALID_cp : wvalid
6.1.1.8 Coverpoint BRESP_cp:
 When all the required bins are tracked. It will generate 100%
coverage for bresp.
 Coverpoint BRESP_cp : bresp
6.1.2 Covergroup read_cg:

6.1.2.1 Coverpoint ARADDR_cp:

 When all the required bins are tracked. It will generate 100%
coverage for data_input_data_in.
 Coverpoint ARADDR_cp : araddr
6.1.2.2 Coverpoint ARLEN_cp:
 When all the required bins are tracked. It will generate 100%
coverage for arlen.
 Coverpoint ARLEN_cp : arlen
6.1.2.3 Coverpoint ARSIZE_cp:
 When all the required bins are tracked. It will generate 100%
coverage for arsizr.
 Coverpoint ARSIZE_cp : arsize
6.1.2.4 Coverpoint ARBURST_cp:
 When all the required bins are tracked. It will generate 100%
coverage for arburst.
 Coverpoint ARBURST_cp : arburst
6.1.2.5 Coverpoint ARVALID_cp:
 When all the required bins are tracked. It will generate 100%
coverage for arvalid.
 Coverpoint ARVALID_cp : arvalid
6.1.2.6 Coverpoint RRESP_cp:
 When all the required bins are tracked. It will generate 100%
coverage for rresp.
 Coverpoint RRESP_cp : rresp

7. Assertion:[ Not Required]

 Assertions are used to validate the behaviour of the design.

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