Unit-IV

Peripheral Interfacing
S.Sayeekumar , AP/RMDEEE
 8251
• The 8251A is a programmable serial
communication interface chip designed for
synchronous and asynchronous serial
data communication.
• It supports the serial transmission of data.
• It is packed in a 28 pin DIP.
Pin details
Architecture
 Arch - details
• The functional block diagram of 825 1A
consists five sections.
They are:
• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.
 Read/Write control logic
• The Read/Write Control logic interfaces the
8251A with CPU, determines the functions of the
8251A according to the control word written into
its control register.
• It monitors the data flow.
• This section has three registers and they are
control register, status register and data buffer.
• The active low signals RD, WR, CS and
C/D(Low) are used for read/write operations with
these three registers.
 Read/Write control logic
• When C/D(low) is high, the control register is
selected for writing control word or reading
status word.
• When C/D(low) is low, the data buffer is selected
for read/write operation.
• When the reset is high, it forces 8251A into the
idle mode.
• The clock input is necessary for 8251A for
communication with CPU and this clock does not
control either the serial transmission or the
reception rate.
 Transmitter
• The transmitter section accepts parallel data
from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it
has a buffer register to hold an 8-bit parallel data
and another register called output register to
convert the parallel data into serial bits.
• When output register is empty, the data is
transferred from buffer to output register. Now
the processor can again load another data in
buffer register.
 Transmitter
• If buffer register is empty, then TxRDY is goes to
high.
• If output register is empty then TxEMPTY goes to
high.
• The clock signal, TxC (low) controls the rate at
which the bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the
baud rate.
 Receiver
• The receiver section accepts serial data and
convert them into parallel data
• The receiver section is double buffered, i.e., it
has an input register to receive serial data and
convert to parallel, and a buffer register to hold
the parallel data.
• When the RxD line goes low, the control logic
assumes it as a START bit, waits for half a bit
time and samples the line again.
• If the line is still low, then the input register
accepts the following bits, forms a character and
loads it into the buffer register.
 Receiver
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits
are received by the USART.
• During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
 Modem control
• The MODEM control unit allows to interface a MODEM to 8251A
and to establish data communication through MODEM over
telephone lines.
• This unit takes care of handshake signals for MODEM interface.
• The 825 1A can be either memory mapped or I/O mapped in the
system.
• 8251A in I/O mapped in the system is shown in the figure.
• Using a 3-to-8 decoder generates the chip select signals for I/O
mapped devices.
• The address lines A4, A5 and A6 are decoded to generate eight chip
select signals (IOCS-0 to IOCS-7) and in this, the chip select signal
IOCS-2 is used to select 8251A.
• The address line A7 and the control signal IO / M(low) are used as
enable for decoder.
• The address line A0 of 8085 is connected to C/D(low) of 8251A to
provide the internal addresses.
 Modem control
• The data lines D0 - D7 are connected to D0 - D7 of the
processor to achieve parallel data transfer.
• The RESET and clock signals are supplied by the
processor. Here the processor clock is directly
connected to 8251A. This clock controls the parallel data
transfer between the processor and 8251A.
• The output clock signal of 8085 is divided by suitable
clock dividers like programmable timer 8254 and then
used as clock for serial transmission and reception.
 Modem control
• The TTL logic levels of the serial data lines and the
control signals necessary for serial transmission and
reception are converted to RS232 logic levels using
MAX232 and then terminated on a standard 9-pin D-
.type connector.
• In 8251A the transmission and reception baud rates can
be different or same.
• The device which requires serial communication with
processor can be connected to this 9-pin D-type
connector using 9-core cable
• The signals TxEMPTY, TxRDY and RxRDY can be used
as interrupt signals to initiate interrupt driven data
transfer scheme between processor and 8251
 Modem control
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits
are received by the USART.
• During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
8251 command register

EH IR RTS ER SBRK RxE DTR TxE

TxE: transmit enable

DTR: data terminal ready
RxE: receiver enable
SBPRK: send break character
ER: error reset
RTS: request to send
IR: internal reset
EH: enter hunt mode
 8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
8251 interfaced with 8085
 8255 PPI

• PPI
Programmable Peripheral
Interface

20
 Intel 8255 PPI
PPI – Programmable Peripheral Interface
It is an I/O port chip used for interfacing I/O
devices with microprocessor
Very commonly used peripheral chip
Knowledge of 8255 essential for students in the
Microprocessors lab for Interfacing experiments

21
 About 82C55
• The 82C55 is a popular interfacing component, that
can interface any TTL-compatible I/O device to a
microprocessor.
• It is used to interface to the keyboard and a parallel
printer port in PCs (usually as part of an integrated
chipset).
• Requires insertion of wait states if used with a
microprocessor using higher that an 8 MHz clock.
• PPI has 24 pins for I/O that are programmable in
groups of 12 pins and has three distinct modes of
operation.
82C55 : Pin Layout
8255 Control Word
Basic Mode Definitions and Bus
Int

• Mode 0
– Basic I/O
• Mode 1
– Strobe I/O
• Mode 2
– Bi-Dir Bus
 Programming 8255
 8255 has three operation modes: mode 0, mode 1, and mode 2

11-26
27
8255 PPI contd.
3 ports in 8255 from user’s point of view
- Port A, Port B and Port C.
Port C composed of two independent 4-bit ports
- PC7-4 (PC Upper) and PC3-0 (PC Lower)
A1 A0 Selected port
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control port
28
 8255 40 pin DIP

Intel 8255 PPI Vcc (+5V)

PA7-0
GND Port A
Chip Select Circuit RD
U2A
WR PC7-4
1 2 1 U1
2
3 CS Port C PC3-0
7404 4
A7 8
5 D7-0 Control Port
U3A 6 PB7-0
11
1 2 12
7430 A1 Port B

7404 A0
M/IO*
Reset

A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, & M/IO*= 0

29
8255 PPI Contd.
There is also a Control port from the Processor point
of view. Its contents decides the working of 8255.
When CS (Chip select) is 0, 8255 is selected for
communication by the processor. The chip select
circuit connected to the CS pin assigns addresses to
the ports of 8255.
For the chip select circuit shown, the chip is selected
when A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, & M/IO*= 0
Port A, Port B, Port C and Control port will have the
addresses as 7CH, 7DH, 7EH, and 7FH respectively.
30
 8255 PPI Contd.
Mode 0: Simple Input or Output

In this mode, ports A, B are used as two simple 8-bit I/O ports
port C as two 4-bit ports.
Each port can be programmed to function as simply an input port or
an output port. The input/output features in Mode 0 are as follows.

1. Outputs are latched.

2. Inputs are not latched.

3. Ports don’t have handshake or interrupt capability.

31
 8255 PPI Contd.
Mode 1: Input or Output with Handshake

In this mode, handshake signals are exchanged between

the MPU and peripherals prior to data transfer.
The features of the mode include the following:

1. Two ports (A and B) function as 8-bit I/O ports.

They can be configured as either as input or output ports.

2. Each port uses three lines from ort C as handshake signals.

The remaining two lines of Port C can be used for simple I/O operations.

3. Input and Output data are latched.

4. Interrupt logic is supported.

32
 8255 PPI Contd.
Mode 2: Bidirectional Data Transfer

This mode is used primarily in applications such as data transfer

between two computers.

In this mode, Port A can be configured as the bidirectional port

Port B either in Mode 0 or Mode 1.

Port A uses five signals from Port C

as handshake signals for data transfer.

The remaining three signals from port C can be used either

as simple I/O or as handshake for port B.

33
 8255 Handshake signals

Where are the Handshake signals?

Port C pins act as handshake signals, when Port A
and Port B are configured for other than Mode 0.
Port A in Mode 2 and Port B in Mode 1 is possible,
as it needs only 5+3 = 8 handshake signals
After Reset of 8255, Port A , Port B , and Port C are
configured for Mode 0 operation as input ports.

34
8255 Handshake signals Contd.

PC2-0 are used as handshake signals by Port B

when configured in Mode 1. This is immaterial
whether Port B is configured as i/p or o/p port.
PC5-3 are used as handshake signals by Port A
when configured as i/p port in Mode 1.
PC7,6,3 are used as handshake signals by Port A
when configured as o/p port in Mode 1.
PC7-3 are used as handshake signals by Port A
when configured in Mode 2.
35
8255 PPI Contd.
Port A can work in Mode 0, Mode 1, or Mode 2
Port B can work in Mode 0, or Mode 1
Port C can work in Mode 0 only, if at all

Port A, Port B and Port C can work in Mode 0

Port A and Port B can work in Mode 1
Only Port A can work in Mode 2

36
8255 MD Control word
Control port having Mode Definition (MD) control word
1 M2A M1A I/P A I/P CU M1B I/P B I/P CL
Means Mode
1 - PCU as input 1 -PCL as input
Definition
control word 0 - PCU as output 0 -PCL as output
1 - PA as input 1 - PB as input
M2A M1A 0 - PA as output 0 - PB as output
0 0 Port A in Mode 0 1 – Port B in Mode 1
0 1 Port A in Mode 1 0 – Port B in Mode 0
1 0/1 Port A in Mode 2
37
8255 MD Control word Contd.
Ex. 1: Configure Port A as i/p in Mode 0, Port B as o/p in
mode 0, Port C (Lower) as o/p and Port C (Upper) as i/p
ports.
Required MD control word:
1 0 0 1 1 0 0 0 = 98H
MD control PC Lower as o/p
PA in Mode 0 PB as o/p Reqd. instrns.
PA as i/p PB in Mode 0 MOV AL, 98H
PC Upper as i/p OUT 7FH, AL
38
8255 MD Control word Contd.
Ex. 2: Configure Port A as i/p in Mode 1, Port B as o/p in
mode 1, Port C7-8 as i/p ports. (PC5-0 are handshake lines,
some i/p lines and others o/p. So they are shown as X)
Required MD control word:
1 0 1 1 1 1 0 X = BCH or BDH
MD control PC3-0 as don’t care
PA in Mode 1 PB as o/p Reqd. Instrns.
PA as i/p PB in Mode 1 MOV AL,BCH
PC Upper(C7-8) as i/p OUT 7FH, AL
39
8255 Contd.
There are 2 control words in 8255
Mode Definition (MD) Control word and
Port C Bit Set / Reset (PCBSR) Control Word

MD control word configures the ports of 8255

- as i/p or o/p in Mode 0, 1, or 2

PCBSR control word is used to set to 1 or reset to 0

any one selected bit of Port C

40
8255 MD Control word Contd.
Ex. 3:Configure Port A in Mode 2, Port B as o/p in mode 1.
(PC5-0 are handshake lines for Port A and PC2-0 are
handshake signals for port B)
Required MD control word:
1 1 0 X X 1 0 X = C4H / C5H..
MD control PC3-0 as handshake
PA in Mode 2 PB as o/p Reqd. instrns.
PA bidirectional PB in Mode 1 MOV AL, C4H
PC7-0 as handshake OUT 7FH, AL
41
8255 PCBSR Control word
Control port having Port C Bit Set / Reset control word
0 X X X SB2 SB1 SB0 S/R*
Select bit of PC 1 - Set to 1
PC bit set
Don’t to be set / reset 0 - Reset to 0
/ reset
cares 0 0 0 Bit 0 of Port C
control
word 0 0 1 Bit 1 of Port C
:
:
1 1 1 Bit 7 of Port C
42
 8253 / 8254 Timer
• To program a given counter to divide the
CLK input frequency, one must send the
divisor to that specific counter’s register.
• Although all three counters share the same
control register, the divisor registers are
separate for each counter
• Example: given the port addresses for
8253/54: Counter 0: 94H Counter 1:
95H
Counter 2: 96H Engr 4862 Microprocessors
Control Reg: 97H
 8253 / 8254 Timer
• Task1: program counter 0 for binary counter
for mode 3 to divide CLK0 by number 4282
(BCD)
MOV AL, 0011 0111B
OUT 97H, AL
MOV AX, 4282H (BCD needs H)
OUT 94H, AL (Low Byte)
MOV AL, AH
OUT 94H, AL (High Byte)
• OUT0 = CLK0 /Engr
42824862 Microprocessors
 Shape of the 8253/54 Output
• Given CLK = 1.193 MHz, the clock period of
input frequency is 838 ns
• If the number N loaded into the counter is
even, both high and low pulse are the same
length, which is N/2 * 838 ns
• If the number N loaded into the counter is
odd, the high pulse is (N+1)/2 * 838 ns and
the low pulse is (N–1)/2 * 838 ns
•  If N is odd, the high portion of the output
square wave is slightly wider than the low
portion Engr 4862 Microprocessors
 8253/54 Operation Modes
• Mode 0: Interrupt on terminal count
– The output is initially low, and remain low for the
duration of the count if GATE=1. When the
terminal count is reached, the output will go
high and remain high until a new control word
or new count number is loaded
• Width of low pulse = N * T, where T is clock period
– Example: GATE=1 and CLK = 1 MHz
Clock count N = 1000

Engr 4862 Microprocessors

 8253/54 Operation Modes
• Mode 0: Interrupt on terminal count
– If GATE becomes low at the middle of the count,
the count will stop and the output will be low. The
count resumes when the GATE becomes high
again  This in effect adds to the total time the
output is low.
• Mode 1: HW triggered / programmable one
shot
– The triggering must be done through the GATE
input by sending a 0-to-1 pulse to it.
– Steps: 1) Load the count register
2) A 0-to-1 pulse
Engr 4862 must be sent to the
Microprocessors

GATE input to trigger the count

 8253/54 Operation Modes
• Mode 1: HW triggered / programmable one
shot
– In Mode 1, after sending the 0-to-1 pulse to
GATE, OUT becomes low and stays low for a
duration of N*T, then becomes high and stays
high until the GATE is triggered again
– If during the activation, a retriggered happened,
then restart the down counting
• Mode 2: Rate Generator (Divide-by-N
counter)
– In Mode2, if GATE=1, OUT will be high for N*T,
goes low only for one clock pulse,
Engr 4862 Microprocessors
then counter is
reloaded automatically, and the process
 8253/54 Operation Modes
• Mode 3: Square wave rate generator
– Most commonly used
• Mode 4: Software triggered strobe
– Similar to Mode2, except that the counter is not
reloaded automatically
– In Mode4, if GATE=1, the output will go high
when loading the count, it will stay high for
duration N*T. After the count reaches zero, it
becomes low for one clock pulse, then goes high
again and stays high until a new command word
or new count is loaded
– To repeat the strobe, the count must be reloaded
Engr 4862 Microprocessors
 8253/54 Operation Modes
• Mode 5: Hardware triggered strobe
– Similar to Mode4, except that the triggering must
be done with the GATE input
– The count starts only when a 0-to-1 pulse is sent
to the GATE input
– If GATE retriggered during the counting, it will
restart the down counting

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

 8259
• 8259 is Programmable Interrupt Controller (PIC)
• It is a tool for managing the interrupt requests.
• 8259 is a very flexible peripheral controller
chip:PIC can deal with up to 64 interrupt
inputs
– interrupts can be masked
– various priority schemes can also programmed.
• originally (in PC XT) it is available as a
separate IC
• Later the functionality of (two PICs) is in the
motherboards chipset.
 Pin description
• 8-bit bi-directional data bus, one address line is
needed,the direction of data flow is controlled by RD
and WR.
• CS is as usual connected to the output of the address
decoder.
• Interrupt requests are output on INT which is
connected to the INTR of the processor. Int.
acknowledgment is received by INTA.
• IR0-IR7 allow 8 separate interrupt requests to be
inputted to the PIC.
• sp/en=1 for master , sp/en=0 for slave.
• CAS0-3 inputs/outputs are used when more than one
PIC to cascaded.
FIGURE 9-4 Block diagram and pin definitions for the 8259A Programmable Interrupt Controller (PIC). (Courtesy of Intel
Corporation.)
FIGURE 9-5 Interfacing the PIC to the 386 and 486 processors. Two I/O ports are required.
FIGURE 9-7 All interrupt requests must pass through the PIC’s interrupt request register (IRR) and interrupt mask register
(IMR). If put in service, the appropriate bit of the in-service (IS) register is set.
Example of two cascaded
PICs
 OPERATION
• PIC is to be initialized and programmed to
control its operation.
• The operation in simple words:
When an interrupt occurs , the PIC determines the highest
priority, activates the processor via its INTR input, and
sends the type number onto the data bus when the
processor acknowledges the interrupt.
• Priority:
What is used in PC is fully nested mode. That is the
lowest numbered IRQ input has highest priority.
Lower priority interrupts will not be forwarded to the
processor until the higher priority interrupts have
been serviced.
FIGURE 9-8 (a) Simultaneous interrupt requests arrive on IR4 and IR6. IR4 has highest priority and its IS bit is set as the IR4
service routine is put in service. (b) The IR4 service routine issues a rotate-on-nonspecific-EOI command, resetting IS4 and
assigning it lowest priority. IR6 is now placed in service. (c) The IR6 service routine issues a rotate-on-nonspecific-EOI
command, resetting IS6 and assigning it lowest priority.

John Uffenbeck
The 80x86 Family: Design, Copyright ©2002 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Programming, and Interfacing, 3e All rights reserved.
FIGURE 9-9 Example illustrating the difference between the rotate-on-nonspecific-EOI command and the rotate-on-specific-
EOI command.
 Modes
• Fully Nested mode
• Special Fully Nested mode
• Nonspecific Rotating
• Specific Rotating
• Special Mask
• Polling
FIGURE 9-11 8259A initialization control word format. (Courtesy of Intel Corporation.)

John Uffenbeck
The 80x86 Family: Design, Copyright ©2002 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Programming, and Interfacing, 3e All rights reserved.
 Features of 8279
The important features of 8279 are,
• Simultaneous keyboard and display operations.
• Scanned keyboard mode.
• Scanned sensor mode.
• 8-character keyboard FIFO.
• 1 6-character display.
• Right or left entry 1 6-byte display RAM.
• Programmable scan timing.
 Pin details

• A0: Selects data (0) or control/status (1) for

reads and writes between micro and 8279.

Output that blanks the displays.

• CLK: Used internally for timing. Max is 3 MHz.

• CN/ST: Control/strobe, connected to the control

key on the keyboard.

• Chip select that enables programming,

reading the keyboard, etc.

• DB7-DB0: Consists of bi-directional pins that

connect to data bus on micro.
 Pin details
• IRQ: Interrupt request, becomes 1 when a key
is pressed, data is available.
• OUT A3-A0/B3-B0: Outputs that sends data to
the most significant/least significant nibble of
display.

• : Connects to micro's IORC or RD

signal, reads data/status registers.
• RESET: Connects to system RESET.
• RL7-RL0: Return lines are inputs used to sense
key depression in the keyboard matrix.
•Shift: Shift connects to Shift key on keyboard.
• SL3-SL0: Scan line outputs scan both the
keyboard and displays.
Block diagram of 8279
 Sections
• Keyboard
• Display
• Scan
• CPU interface
 Keyboard section
• The keyboard section consists of eight return lines RL0 - RL7
that can be used to form the columns of a keyboard matrix.
• It has two additional input : shift and control/strobe. The keys
are automatically debounced.
• The two operating modes of keyboard section are 2-key
lockout and N-key rollover.
• In the 2-key lockout mode, if two keys are pressed
simultaneously, only the first key is recognized.
• In the N-key rollover mode simultaneous keys are recognized
and their codes are stored in FIFO.
• The keyboard section also have an 8 x 8 FIFO (First In First
Out) RAM.
• The FIFO can store eight key codes in the scan keyboard
mode. The status of the shift key and control key are also
stored along with key code.
• The 8279 generate an interrupt signal when there is an entry
in FIFO.
 Display section
• The display section has eight output lines divided into
two groups A0-A3 and B0-B3.
• The output lines can be used either as a single group of
eight lines or as two groups of four lines, in conjunction
with the scan lines for a multiplexed display.
• The output lines are connected to the anodes through
driver transistor in case of common cathode 7-segment
LEDs.
• The cathodes are connected to scan lines through driver
transistors.
• The display can be blanked by BD (low) line.
• The display section consists of 16 x 8 display RAM. The
CPU can read from or write into any location of the
display RAM.
 Scan section
• The scan section has a scan counter and four
scan lines, SL0 to SL3.
• In decoded scan mode, the output of scan lines
will be similar to a 2-to-4 decoder.
• In encoded scan mode, the output of scan lines
will be binary count, and so an external decoder
should be used to convert the binary count to
decoded output.
• The scan lines are common for keyboard and
display.
• The scan lines are used to form the rows of a
matrix keyboard and also connected to digit
drivers of a multiplexed display, to turn ON/OFF.
 CPU interface section
• The CPU interface section takes care of data transfer
between 8279 and the processor.
• This section has eight bidirectional data lines DB0 to
DB7 for data transfer between 8279 and CPU.
• It requires two internal address A =0 for selecting data
buffer and A = 1 for selecting control register of8279.
• The control signals WR (low), RD (low), CS (low) and A0
are used for read/write to 8279.
• It has an interrupt request line IRQ, for interrupt driven
data transfer with processor.
• The 8279 require an internal clock frequency of 100 kHz.
This can be obtained by dividing the input clock by an
internal prescaler.
• The RESET signal sets the 8279 in 16-character display
with two -key lockout keyboard modes.
Control Word Description:

First three bits given below select one of 8 control registers

(opcode).

 000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode.

DD field selects either:

• 8- or 16-digit display
• Whether new data are entered
to the rightmost or leftmost
display position.
Control Word Description:
MMM field:

MMM

• Encoded Mode: SL outputs are active-high, follow binary

bit pattern 0-7 or 0-15 depending on 8 or 16 digit display.
• Decoded Mode: SL outputs are active-low (only one of
the four outputs will be low at any time).Pattern output:
1110, 1101, 1011, 0111.
 I/O Interface
Control Word Description:

• Strobe : An active high pulse on the CN/ST input pin strobes

data from the RL pins into an internal FIFO for reading by micro
later.
• 2-key lockout/N-key rollover: Prevents 2 keys from being
recognized if pressed simultaneously/Accepts all keys pressed
from 1st to last.
 Write display format

 100ZAAAA

write display Selects address – to write address of one of the

Display. Z selects auto-increment so subsequent writes go to
subsequent display positions.
 Clear Display format
• 1100CCFA
• The clear control word clears the
display, FIFO or both
• Bit F clears FIFO and the display RAM
status, and sets address pointer to 000.
• If CC are 00 or 01, all display RAM
locations become 00000000.
• If CC is 10, --> 00100000,
• if CC is 11, --> 11111111.
 Basic DMA concept
Direct memory access (DMA) is a feature of
modern computer systems that allows certain
hardware subsystems to read/write data to/from
memory without microprocessor intervention,
allowing the processor to do other work.
Used in disk controllers, video/sound cards etc,
or between memory locations.
Typically, the CPU initiates DMA transfer, does
other operations while the transfer is in progress,
and receives an interrupt from the DMA controller
once the operation is complete.
Can create cache coherency problems (the data
in the cache may be different from the data in the
external memory after DMA)
86
 The 8237 DMA controller
 Supplies memory and I/O with control signals and addresses
during DMA transfer
 4-channels (expandable)
 0: DRAM refresh
 1: Free
 2: Floppy disk controller
 3: Free
 1.6MByte/sec transfer rate
 64 KByte section of memory address capability with single
programming
 “fly-by” controller (data does not pass through the DMA-only
memory to I/O transfer capability)
 Initialization involves writing into each channel:
i) The address of the first byte of the block of data that must be
transferred (called the base address).
ii) The number of bytes to be transferred (called the word count).

87
 8237 pins
 CLK: System clock
 CS΄: Chip select (decoder output)
 RESET: Clears registers, sets mask register
 READY: 0 for inserting wait states
 HLDA: Signals that the μp has relinquished buses
 DREQ3 – DREQ0: DMA request input for each channel
 DB7-DB0: Data bus pins
 IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
 IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
 EOP΄: End of process is a bidirectional signal used as input to terminate
a
DMA process or as output to signal the end of the DMA transfer
 A3-A0: Address pins for selecting internal registers
 A7-A4: Outputs that provide part of the DMA transfer address
 HRQ: DMA request output
 DACK3-DACK0: DMA acknowledge for each channel.
 AEN: Address enable signal
 ADSTB: Address strobe
 MEMR΄: Memory read output used in DMA read cycle
 MEMW΄: Memory write output used in DMA write cycle

88
8237 pin
Diagram

89
A 8237 DMA application

DMA ARCHITECTURE
90
 8237 registers
• CAR (Current Address Register): holds the 16-bit
memory address used for the DMA transfer (one
for each channel), either incremented or
decremented during the operation
• CWCR (Current Word Count Register): Programs a
channel for the number of bytes (up to 64K)
transferred during a DMA operation
• BA (Base Address) and WC (Word Count): Used
when auto-initialization is selected for a channel, to
reload the CAR and CWCR when DMA is
complete.
• CR (Command Register): Programs the operation
of the controller 91
• MR (Mode Register):

• Programs the mode of

operation for a channel (one
for each channel).

92
• MR (Mask
Register):

• SR (Status
Register): Shows
the status of each
DMA channel
93
8237 Software commands

94
 8237 Software commands
 Clear First/Last Flip-Flop - This command is executed prior to writing or reading
new address or word count information to the 82C37. This command initializes the
flipflop to a known state (low byte first) so that subsequent accesses to register
contents by the microprocessor will address upper and lower bytes in the correct
sequence.
 Set First/Last Flip-Flop - This command will set the flip-flop to select the high byte
first on read and write operations to address and word count registers.
 Master Clear - This software instruction has the same effect as the hardware
Reset. The Command, Status, Request, and Temporary registers, and Internal
First/Last Flip-Flop and mode register counter are cleared and the Mask register is
set. The 82C37A will enter the idle cycle.
 Clear Mask Register - This command clears the mask bits of all four channels,
enabling them to accept DMA requests.
 Clear Mode Register Counter - Since only one address location is available for
reading the Mode registers, an internal two-bit counter has been included to select
Mode registers during read operation. To read the Mode registers, first execute the
Clear Mode Register Counter command, then do consecutive reads until the
desired channel is read. Read order is channel 0 first, channel 3 last. The lower
two bits on all Mode registers will read as ones.

95
8237 block diagram

96
 Initiating a DMA transaction
 Save the current interrupt status and disable
interrupts by executing the CLI instruction
 Disable the channel that will be used for the
transaction
 Reset the flip-flop by writing a value of 0X to the
register
 Set the Mode Register
 Set the Page Register
 Set the Offset Register
 Set the Block Size Register
 Enable the channel that will be used for the
transaction
 Restore the interrupt status
97
 A/D Interfacing

• After the conversion is over, the ADC sends end

of conversion EOC signal to inform the
microprocessor that the conversion is over and
the result is ready at the output buffer of the
ADC.

• These tasks of issuing an SOC pulse to ADC,

reading EOC signal from the ADC and reading
the digital output of the ADC are carried out by
the CPU using 8255 I/O ports.
 A/D Interfacing
• The time taken by the ADC from the active
edge of SOC pulse till the active edge of
EOC signal is called as the conversion
delay of the ADC.
• Successive approximation techniques and
dual slope integration techniques are the
most popular techniques used in the
integrated ADC chip.
• The analog to digital converter chips 0808
and 0809 are 8-bit CMOS, successive
approximation converters.
ADC 0804
 ADC Interfacing
• CS :Active low input used to activate the ADC0804
chip.

RD (data enable) : Active low input used to get

converted data out of the ADC0804 chip. When CS = 0,
if a high-to-low pulse is applied to the RD pin, the 8-bit
digital output shows up at the D0-D7 data pins.
WR (start conversion): Active low input used to inform
the ADC0804 to start the conversion process. If CS = 0
when WR makes a low-to-high transition, the
ADC0804 starts converting the analog input value of
Vin to an 8-bit digital number. When the data
conversion is complete, the INTR pin is forced low by
the ADC0804.
 ADC Interfacing
• CLK IN and CLK R : Connect to external capacitor and
resistor for self-clocking, f = 1/(1.1RC). The clock affect
the conversion time and this time cannot be faster than
110 micros.

INTR (end of conversion) This is an active low output

pin. When the conversion is finished, it goes low to
signal the CPU that the converted data is ready to be
picked up. After INTR goes low, we make CS = 0 and
send a high-to-low pulse to the RD pin to get the data
out of the ADC0804 chip.
 ADC Interfacing
• Vin (+) and Vin (-) :These are the
differential analog inputs where Vin =
Vin (+) - Vin (-). Often the Vin (-) pin is
connected to ground and the Vin (+)
pin is used as the analog input to be
converted to digital.
• VCC : This is the +5V power supply. It
is also used as a reference voltage
when the Vref/2 (pin 9) input is open.
 ADC Interfacing
• Vref/2 :- Input voltage pin used for the
reference voltage. If this pin is open, the
analog input voltage for the the ADC is
ranged from 0 to 5 volts.This is optional
input pin. It is used only when the input
signal range is small. When pin 9 is at
2V, the range is 0-4V, i.e. Twice the
voltage at pin 9. Pin 6 (V+), Pin 7(V-):
The actual input is the difference in
voltages applied to these pins. The
analogue input can range from 0 to 5V.
ADC Interfacing
ADC Interfacing
A/D Interfacing [0808 ]
 A/D Interfacing
• The ADC 0808 is 8-channel 8-bit ADC chip.
It has 8 analog inputs i.e. IN0-IN7.
A/D Interfacing
A/D Interfacing
A/D Interfacing
 3/9/14

D/A INTERFACING

DEEPAK.P
 D/A Interfacing
• The digital to analog converters convert
binary number into their equivalent
voltages.
• The DAC find applications in areas like
digitally controlled gains, motors speed
controls, programmable gain amplifiers etc.
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
 D/A Interfacing
• AD 7523 8-bit Multiplying DAC : This is a 16 pin
DIP, multiplying digital to analog converter,
containing R-2R ladder for D-A conversion along
with single pole double thrown NMOS switches to
connect the digital inputs to the ladder.

• supply range is from +5V to +15V, while

• Vref may be any where between -10V to +10V.
• The maximum analog output voltage will be any where between -
10V to +10V, when all the digital inputs are at logic high state.
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing