RTL8380M-VB-CG

MULTI-LAYER MANAGED 10*10/100/1000M-PORT SWITCH CONTROLLER

RTL8382M-VB-CG
MULTI-LAYER MANAGED 28*10/100/1000M-PORT SWITCH CONTROLLER

DATASHEET
(CONFIDENTIAL: Development Partners Only)

Rev. 1.2
30 January 2016
Track ID:

Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
 RTL8380M-VB/RTL8382M-VB
Datasheet

COPYRIGHT
©2016 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.

TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.

USING THIS DOCUMENT

This document provides detailed user guidelines to achieve the best performance when implementing the
Realtek Ethernet Switch Controllers.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.

REVISION HISTORY
Revision Release Date Summary
1.0 2014/01/20 First release.
1.1 2016/1/8 Remove the support for 10M-EEE and I2C master for EEPROM.
1.2 2016/6/30 Separate unmanaged series RTL8382L.

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Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2. FEATURES ......................................................................................................................................................................... 3
3. SYSTEM APPLICATIONS ............................................................................................................................................... 4
3.1. RTL8380M-VB: MANAGED 8*1000M UTP+2*1000BASE-X SWITCH ....................................................................... 4
3.2. RTL8382M-VB: MANAGED 28*1000M SWITCH VIA RTL8218B PHY ...................................................................... 5
3.3. RTL8382M-VB: MANAGED 20*1000M UTP+4*1000M COMBO SWITCH ................................................................. 6
3.4. RTL8382M-VB: MANAGED 24*1000M UTP+2*1000BASE-X SWITCH ..................................................................... 7
4. BLOCK DIAGRAMS ......................................................................................................................................................... 8
4.1. RTL8380M-VB BLOCK DIAGRAM .............................................................................................................................. 8
4.2. RTL8382M-VB BLOCK DIAGRAM .............................................................................................................................. 9
5. PIN ASSIGNMENTS AND DESCRIPTION (RTL8380M-VB) ................................................................................... 10
5.1. PIN ASSIGNMENTS FIGURE (RTL8380M-VB) ........................................................................................................... 10
5.2. PACKAGE IDENTIFICATION ......................................................................................................................................... 10
5.3. PIN ASSIGNMENTS TABLE CODES (RTL8380M-VB) ................................................................................................. 11
5.4. PIN ASSIGNMENTS TABLE (RTL8380M-VB) ............................................................................................................. 11
5.5. PIN DESCRIPTIONS (RTL8380M-VB) ........................................................................................................................ 16
5.5.1. 1000M Ethernet PHY MDI Interface Pins ............................................................................................................ 16
5.5.2. SGMII Interface Pins............................................................................................................................................ 18
5.5.3. 1000Base-X/100Base-FX Interface Pins .............................................................................................................. 18
5.5.4. DDR1/2 SDRAM Interface Pins ........................................................................................................................... 19
5.5.5. DDR3 SDRAM Interface Pins .............................................................................................................................. 20
5.5.6. Master Mode SPI Flash Interface Pins ................................................................................................................ 20
5.5.7. UART Interface Pins............................................................................................................................................. 21
5.5.8. LED Interface Pins ............................................................................................................................................... 21
5.5.9. GPIO Interface Pins ............................................................................................................................................. 21
5.5.10. EJTAG Interface Pins ...................................................................................................................................... 21
5.5.11. Configuration Strapping Pins .......................................................................................................................... 22
5.5.12. Miscellaneous Interface Pins ........................................................................................................................... 23
5.5.13. Power and Ground Pins .................................................................................................................................. 24
6. PIN ASSIGNMENTS AND DESCRIPTION (RTL8382M-VB) ................................................................................... 25
6.1. PIN ASSIGNMENTS FIGURE (RTL8382M-VB) ........................................................................................................... 25
6.2. PACKAGE IDENTIFICATION ......................................................................................................................................... 25
6.3. PIN ASSIGNMENTS TABLE CODES (RTL8382M-VB) ................................................................................................. 26
6.4. PIN ASSIGNMENTS TABLE (RTL8382M-VB) ............................................................................................................. 26
6.5. PIN DESCRIPTIONS (RTL8382M-VB) ........................................................................................................................ 44
6.5.1. 1000M Ethernet PHY MDI Interface Pins ............................................................................................................ 44
6.5.2. SGMII Interface Pins ............................................................................................................................................ 46
6.5.3. QSGMII Interface Pins ......................................................................................................................................... 46
6.5.4. 1000Base-X/100Base-FX Interface Pins .............................................................................................................. 47
6.5.5. DDR1/2 SDRAM Interface Pins ........................................................................................................................... 47
6.5.6. DDR3 SDRAM Interface Pins .............................................................................................................................. 48
6.5.7. Master Mode SPI Flash Interface Pins ................................................................................................................ 48
6.5.8. UART Interface Pins............................................................................................................................................. 49
6.5.9. LED Interface Pins ............................................................................................................................................... 49
6.5.10. GPIO Interface Pins ........................................................................................................................................ 49
6.5.11. EJTAG Interface Pins ...................................................................................................................................... 49
6.5.12. Configuration Strapping Pins .......................................................................................................................... 50
6.5.13. Miscellaneous Interface Pins ........................................................................................................................... 51
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6.5.14. Power and Ground Pins .................................................................................................................................. 52
7. SWITCH FUNCTION DESCRIPTION ......................................................................................................................... 52
7.1. HARDWARE RESET AND SOFTWARE RESET................................................................................................................ 52
7.1.1. Hardware Reset .................................................................................................................................................... 52
7.1.2. Software Reset ...................................................................................................................................................... 52
7.2. CRYSTAL.................................................................................................................................................................... 53
7.3. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) ................................................................................................ 53
7.4. LAYER 2 LEARNING AND FORWARDING ..................................................................................................................... 53
7.4.1. Forwarding ........................................................................................................................................................... 53
7.4.2. Learning ............................................................................................................................................................... 53
7.4.3. DA/SA Block ......................................................................................................................................................... 54
7.5. PORT ISOLATION ........................................................................................................................................................ 54
7.6. IEEE 802.3X FLOW CONTROL ................................................................................................................................... 56
7.7. HALF DUPLEX BACKPRESSURE .................................................................................................................................. 57
7.7.1. Collision-Based Backpressure (Jam Mode) ......................................................................................................... 57
7.7.2. Carrier-Based Backpressure (I.e., Defer Mode) .................................................................................................. 57
7.8. LAYER 2 MULTICAST AND IP MULTICAST ................................................................................................................. 57
7.9. IEEE 802.1D/1W/1S (STP/RSTP/MSTP) ................................................................................................................... 58
7.10. IEEE 802.1P AND IEEE 802.1Q (VLAN) .................................................................................................................. 59
7.11. IEEE 802.1X (NETWORK ACCESS CONTROL) ............................................................................................................ 60
7.12. RESERVED MULTICAST ADDRESS HANDLING ............................................................................................................ 61
7.13. LAYER 2 TRAFFIC SUPPRESSION (STORM CONTROL) ................................................................................................. 62
7.14. PIE (PACKET INSPECTION ENGINE) ............................................................................................................................ 62
7.14.1. Ingress ACL ..................................................................................................................................................... 62
7.15. INPUT BANDWIDTH CONTROL AND ACL TRAFFIC METER ......................................................................................... 63
7.15.1. Input Bandwidth Control ................................................................................................................................. 63
7.15.2. ACL Traffic Meter............................................................................................................................................ 63
7.16. IEEE 802.3AD LINK AGGREGATION PROTOCOL ........................................................................................................ 63
7.17. IEEE 802.1AD VLAN STACKING............................................................................................................................... 64
7.18. QUALITY OF SERVICE (QOS) ...................................................................................................................................... 65
7.19. PACKET SCHEDULING (WRR AND WFQ) .................................................................................................................. 66
7.20. PACKET DROP ALGORITHM (TD) ............................................................................................................................... 67
7.21. EGRESS PACKET REMARKING .................................................................................................................................... 67
7.22. INGRESS AND EGRESS PORT MIRROR ......................................................................................................................... 67
7.22.1. Remote Mirror (RSPAN) .................................................................................................................................. 68
7.23. MANAGEMENT INFORMATION BASE (MIB) ............................................................................................................... 69
7.24. NIC AND CPU TAG FORWARDING ............................................................................................................................. 69
7.25. INDIRECT TABLE ACCESS........................................................................................................................................... 70
7.26. EXTERNAL PHY REGISTER ACCESS ........................................................................................................................... 70
7.27. SWITCH INTERRUPT INDICATION ................................................................................................................................ 70
8. CPU FUNCTION DESCRIPTION ................................................................................................................................. 71
8.1. MIPS-4KEC............................................................................................................................................................... 71
8.2. SPI FLASH.................................................................................................................................................................. 71
8.3. SDRAM INTERFACE CONFIGURATION....................................................................................................................... 71
9. INTERFACE DESCRIPTIONS ...................................................................................................................................... 72
9.1. QSGMII .................................................................................................................................................................... 72
9.2. SGMII ....................................................................................................................................................................... 72
9.3. DDR1 SDRAM ......................................................................................................................................................... 73
9.4. DDR2 SDRAM ......................................................................................................................................................... 74
9.5. DDR3 SDRAM ......................................................................................................................................................... 75
9.6. SPI FLASH INTERFACE ............................................................................................................................................... 75
9.7. UART ........................................................................................................................................................................ 76

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9.8. EJTAG ...................................................................................................................................................................... 76
9.9. I2C SLAVE INTERFACE ............................................................................................................................................... 77
9.10. SPI SLAVE INTERFACE ............................................................................................................................................... 78
9.11. SERIAL LED............................................................................................................................................................... 79
10. ELECTRICAL AC/DC CHARACTERISTICS ............................................................................................................. 81
10.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 81
10.2. OPERATING RANGE .................................................................................................................................................... 81
10.3. DC CHARACTERISTICS ............................................................................................................................................... 81
10.4. AC CHARACTERISTICS ............................................................................................................................................... 82
10.4.1. QSGMII Differential Transmitter Characteristics ........................................................................................... 82
10.4.2. QSGMII Differential Receiver Characteristics................................................................................................ 82
10.4.3. SGMII Differential Transmitter Characteristics.............................................................................................. 84
10.4.4. SGMII Differential Receiver Characteristics .................................................................................................. 85
10.4.5. 1000Base-X/100Base-FX Differential Transmitter Characteristics ................................................................ 86
10.4.6. 1000Base-X/100Base-FX Differential Receiver Characteristics ..................................................................... 87
10.4.7. DDR2 Characteristics ..................................................................................................................................... 88
10.4.8. DDR3 Characteristics ..................................................................................................................................... 89
10.4.9. SPI Interface Characteristics........................................................................................................................... 90
10.4.10. SMI (MDC/MDIO) Interface Characteristics .................................................................................................. 91
10.4.11. Serial Mode LED ............................................................................................................................................. 91
11. PACKAGE INFORMATION .......................................................................................................................................... 92
11.1. LQFP216-E-PAD (24*24MM) ................................................................................................................................... 92
12. ORDERING INFORMATION ........................................................................................................................................ 94

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List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE (RTL8380M-VB) ............................................................................................................... 11
TABLE 2. 1000M ETHERNET PHY MDI INTERFACE PINS ............................................................................................................ 16
TABLE 3. SGMII INTERFACE PINS ............................................................................................................................................... 18
TABLE 4. 1000BASE-X/100BASE-FX INTERFACE PINS ............................................................................................................... 18
TABLE 5. DDR1/2 SDRAM INTERFACE PINS .............................................................................................................................. 19
TABLE 6. DDR3 SDRAM INTERFACE PINS ................................................................................................................................. 20
TABLE 7. MASTER MODE SPI FLASH INTERFACE PINS ................................................................................................................ 20
TABLE 8. UART INTERFACE PINS ............................................................................................................................................... 21
TABLE 9. LED INTERFACE PINS .................................................................................................................................................. 21
TABLE 10. GPIO INTERFACE PINS ................................................................................................................................................ 21
TABLE 11. EJTAG INTERFACE PINS.............................................................................................................................................. 21
TABLE 12. CONFIGURATION STRAPPING PINS ............................................................................................................................... 22
TABLE 13. MISCELLANEOUS INTERFACE PINS............................................................................................................................... 23
TABLE 14. POWER AND GROUND PINS .......................................................................................................................................... 24
TABLE 15. PIN ASSIGNMENTS TABLE (RTL8382M-VB) .............................................................................................................. 26
TABLE 16. 1000M ETHERNET PHY MDI INTERFACE PINS ........................................................................................................... 44
TABLE 17. SGMII INTERFACE PINS .............................................................................................................................................. 46
TABLE 18. QSGMII INTERFACE PINS ............................................................................................................................................ 46
TABLE 19. 1000BASE-X/100BASE-FX INTERFACE PINS ............................................................................................................... 47
TABLE 20. DDR1/2 SDRAM INTERFACE PINS ............................................................................................................................. 47
TABLE 21. DDR3 SDRAM INTERFACE PINS ................................................................................................................................ 48
TABLE 22. MASTER MODE SPI FLASH INTERFACE PINS ............................................................................................................... 48
TABLE 23. UART INTERFACE PINS ............................................................................................................................................... 49
TABLE 24. LED INTERFACE PINS .................................................................................................................................................. 49
TABLE 25. GPIO INTERFACE PINS ................................................................................................................................................ 49
TABLE 26. EJTAG INTERFACE PINS.............................................................................................................................................. 49
TABLE 27. CONFIGURATION STRAPPING PINS ............................................................................................................................... 50
TABLE 28. MISCELLANEOUS INTERFACE PINS............................................................................................................................... 51
TABLE 29. POWER AND GROUND PINS .......................................................................................................................................... 52
TABLE 30. SPANNING TREE AND RAPID SPANNING TREE ACTION ................................................................................................ 59
TABLE 31. FORWARDING OF HOST N ............................................................................................................................................. 61
TABLE 32. RESERVED MULTICAST ADDRESS DEFAULT ACTIONS ................................................................................................. 61
TABLE 33. UART CONTROL INTERFACE PINS ............................................................................................................................... 76
TABLE 34. EJTAG INTERFACE PINS.............................................................................................................................................. 76
TABLE 35. SPI SLAVE INTERFACE ................................................................................................................................................. 78
TABLE 36. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 81
TABLE 37. RECOMMENDED OPERATING RANGE ........................................................................................................................... 81
TABLE 38. DC CHARACTERISTICS (IO POWER =3.3V) .................................................................................................................. 81
TABLE 39. QSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS ......................................................................................... 82
TABLE 40. QSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ............................................................................................... 82
TABLE 41. SGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS............................................................................................ 84
TABLE 42. SGMII DIFFERENTIAL RECEIVER CHARACTERISTICS .................................................................................................. 85
TABLE 43. 1000BASE-X/100BASE-FX DIFFERENTIAL TRANSMITTER CHARACTERISTICS ............................................................ 86
TABLE 44. 1000BASE-X/100BASE-FX DIFFERENTIAL RECEIVER CHARACTERISTICS ................................................................... 87
TABLE 45. DDR2 SDRAM TIMING CHARACTERISTICS ................................................................................................................ 88
TABLE 46. DDR3 SDRAM TIMING CHARACTERISTICS ................................................................................................................ 89
TABLE 47. SPI INTERFACE TIMING CHARACTERISTICS ................................................................................................................. 90
TABLE 48. SMI (MDC/MDIO) TIMING CHARACTERISTICS .......................................................................................................... 91
TABLE 49. SERIAL MODE LED AC TIMING .................................................................................................................................. 91
TABLE 50. ORDERING INFORMATION ............................................................................................................................................ 94

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List of Figures
FIGURE 1. MANAGED 8*1000M UTP+2*1000BASE-X SWITCH .................................................................................................... 4
FIGURE 2. MANAGED 28*1000M SWITCH VIA RTL8218B PHY ................................................................................................... 5
FIGURE 3. MANAGED 20*1000M UTP+4*1000M COMBO SWITCH .............................................................................................. 6
FIGURE 4. MANAGED 24*1000M UTP+2*1000BASE-X SWITCH .................................................................................................. 7
FIGURE 5. RTL8380M-VB BLOCK DIAGRAM ............................................................................................................................... 8
FIGURE 6. RTL8382M-VB BLOCK DIAGRAM ............................................................................................................................... 9
FIGURE 7. PIN ASSIGNMENTS (RTL8380M-VB) ......................................................................................................................... 10
FIGURE 8. PIN ASSIGNMENTS (RTL8382M-VB) ......................................................................................................................... 25
FIGURE 9. DA/SA BLOCK ............................................................................................................................................................. 54
FIGURE 10. PORT ISOLATION EXAMPLE ........................................................................................................................................ 55
FIGURE 11. TX PAUSE FRAME FORMAT ........................................................................................................................................ 56
FIGURE 12. FLOW CONTROL STATE MACHINE .............................................................................................................................. 56
FIGURE 13. SIGNAL TIMING FOR COLLISION-BASED BACKPRESSURE ........................................................................................... 57
FIGURE 14. SPANNING TREE AND RAPID SPANNING TREE PORT STATES ...................................................................................... 58
FIGURE 15. IEEE 802.1AD FRAME FORMAT.................................................................................................................................. 64
FIGURE 16. PRIORITY SELECTION TABLE WEIGHT RULES EXAMPLE ............................................................................................ 65
FIGURE 17. PER-PORT QUEUE MANAGEMENT .............................................................................................................................. 66
FIGURE 18. RSPAN ENCAPSULATION ........................................................................................................................................... 68
FIGURE 19. RSPAN ILLUSTRATION .............................................................................................................................................. 68
FIGURE 20. NIC ARCHITECTURE ................................................................................................................................................... 69
FIGURE 21. QSGMII INTERCONNECTION ...................................................................................................................................... 72
FIGURE 22. SGMII SIGNAL ........................................................................................................................................................... 72
FIGURE 23. DDR1 SDRAM CONFIGURATION .............................................................................................................................. 73
FIGURE 24. DDR2 SDRAM CONFIGURATION .............................................................................................................................. 74
FIGURE 25. DDR3 SDRAM CONFIGURATION .............................................................................................................................. 75
FIGURE 26. SPI FLASH CONFIGURATION ....................................................................................................................................... 75
FIGURE 27. EJTAG USING A 5-PIN JTAG INTERFACE TO ACCESS DATA BLOCK.......................................................................... 76
FIGURE 28. I2C SLAVE INTERFACE ACCESS DATA SEQUENCE ...................................................................................................... 77
FIGURE 29. SERIAL LED CONNECTION ......................................................................................................................................... 79
FIGURE 30. QSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM .............................................................................................. 82
FIGURE 31. QSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM .................................................................................................... 83
FIGURE 32. SGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM ................................................................................................. 84
FIGURE 33. SGMII DIFFERENTIAL RECEIVER EYE DIAGRAM ....................................................................................................... 85
FIGURE 34. 1000BASE-X/100BASE-FX DIFFERENTIAL TRANSMITTER EYE DIAGRAM ................................................................. 86
FIGURE 35. 1000BASE-X/100BASE-FX DIFFERENTIAL RECEIVER EYE DIAGRAM ........................................................................ 87
FIGURE 36. DDR2 TIMING CHARACTERISTICS .............................................................................................................................. 88
FIGURE 37. DDR3 TIMING CHARACTERISTICS .............................................................................................................................. 89
FIGURE 38. SPI INTERFACE TIMING .............................................................................................................................................. 90
FIGURE 39. SMI (MDC/MDIO) TIMING ....................................................................................................................................... 91
FIGURE 40. SERIAL MODE LED AC TIMING PARAMETERS ........................................................................................................... 91

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1. General Description
The RTL8380M-VB-CG and RTL8382M-VB-CG are new generation Gigabit switches supporting
Energy Efficient Ethernet (EEE). The RTL8380M-VB is an 10-port 10/100/1000M switch controller, and
the RTL8382M-VB is a 28-port 10/100/1000M switch controller. Both of them have an 8-port
10/100/1000M Ethernet PHY embedded.
The RTL8380M-VB/RTL8382M-VB are provided via a 55nm CMOS process in an LQFP-216 E-PAD
package. The Memory interface of the RTL8380M-VB/RTL8382M-VB supports DDR1/DDR2/DDR3
and SPI Flash. The following table lists the main differences between the RTL8380M-VB/RTL8382M-
VB:
Features RTL8380M-VB RTL8382M-VB
Port Capacity 8G*UTP + 2*1000Base-X 24G*UTP + 4GCombo
Management Mode Managed Mode Only Managed Mode Only
DDR1/2/3 Yes Yes
SPI Flash Yes Yes
EEPROM Config. Yes Yes
Internal CPU Yes Yes

The RTL8380M-VB supports two-pairs of SGMII/1000Base-X.

The RTL8382M-VB support four pairs of serially connected QSGMII interface ports to connect to two
Octal Gigabit PHYs (RTL8218B). The RTL8382M-VB also supports one serially connected QSGMII
interface port to connect to 1 Quad Gigabit PHY (RTL8214FC).
The RTL8380M-VB/RTL8382M-VB have an embedded 500MHz MIPS-4KEc CPU that supports a
32MByte (max.) SPI flash and DDR1/DDR2/DDR3 memory interface. Two 16C550 compatible UARTs
are integrated for low speed serial data, and one E-JTAG is supported for on-chip debugging.
There are 8K entries in the 4-way hash L2 table for MAC address learning and searching. The
RTL8380M-VB/RTL8382M-VB supports two hash algorithms. An independent 512-entry Multicast table
supports Layer 2 and IP multicast functions.
The RTL8380M-VB/RTL8382M-VB has a 4K-entry VLAN table for 802.1Q port-based, protocol-and-
port-based, 802.1Q-based, IP-subnet-based, and ACL Rules-based VLAN operation to separate logical
connectivity from physical connectivity. Support is provided for IVL (Independent VLAN Learning),
SVL (Shared VLAN Learning), and IVL/SVL (both Independent and Shared VLAN Learning) for
flexible network topology architecture. The RTL8380M-VB/RTL8382M-VB supports a 1.5K-entry
Access Control List (ACL) that parses various protocol packet types and performs configurable actions,
e.g., Permit/Drop, redirect, and traffic policing.
The RTL8380M-VB/RTL8382M-VB supports per-port ingress/egress bandwidth control and per-queue
egress bandwidth control. It has 8 physical queues in each port. The RTL8380M-VB/RTL8382M-VB
provides three types of packet scheduling; SP (Strict Priority), WFQ (Weighted Fair Queuing), and WRR
(Weighted Round Robin). Each queue provides a leaky-bucket to shape the incoming traffic into the
average rate behavior.

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Port-based 802.1X and MAC-based 802.1X authentication prevent unauthorized users from accessing
internal servers. The RTL8380M-VB/RTL8382M-VB supports port isolation to enhance port security.
The RTL8380M-VB/RTL8382M-VB also supports a 4-set port mirror configuration to mirror ingress and
egress traffic. For network management purposes, complete MIB counter support reflects the switch
status in real time. Support is provided for link aggregation to increase link redundancy, and increase
linear bandwidth.
The RTL8380M-VB/RTL8382M-VB adopts advanced technologies such as Realtek Cable Test (RTCT),
Automatic loop detection and prevention (RLPP/RLDP), Attack Prevention, and MAC Address Learning
Constraints.

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2. Features
 I2C and slave SPI interface for external
 Hardware Interface
master interface to access internal
 RTL8380M-VB registers
 10-port Gigabit wire speed
forwarding capability  L2 VLAN Function
 Supports 8-port 10/100/1000M  Supports IVL, SVL, and IVL/SVL
Ethernet PHY
 Supports two pairs of  Supports IEEE 802.1Q VLAN
SGMII/1000Base-X  4K-entry VLAN Table
 Port-based VLAN
 RTL8382M-VB  Port-and-protocol-based VLAN
 RTL8382M-VB provides 28-port  ACL-based VLAN
Gigabit wire speed forwarding
 Supports up to 64 spanning tree
capability instances for MSTP (IEEE 802.1s),
 Supports 8-port 10/100/1000M RSTP, and STP
Ethernet PHY
 Support 4-pairs of QSGMII to  Supports flexible Q-in-Q and VLAN Tag
connect to external 8-port function
10/100/1000M Ethernet PHYs
 RTL8382M-VB supports an extra 1  L2 MAC Function
pair of QSGMII or 2 pairs of  4.1 Mbit SRAM Packet Buffer
SGMII/1000Base-X
 Packet length of 10000Bytes
 DRAM and Flash Interface
 8K-entry L2 MAC table with 4-way
 Support one 8-bit 128MByte
DDR1/DDR2 or one 8-bit 256MByte hashing algorithm
DDR3 for internal CPU  Independent 512-entry L2/IP Multicast
 Support one 32MByte SPI flash table for multicast function
interface
 2-hash algorithm selection for L2 table
 Embedded MIPS-4KEc with MMU searching/learning
 MIPS32 instruction set and 5-stage
 Aging timer range from 0.2s to
pipeline
1600000s
 500MHz CPU clock rate
 16KByte I-Cache and 16KByte D-  Supports IGMPv1/2/3 and MLDv1/2
Cache snooping
 Built-in 128KByte SRAM  Supports Reserved Multicast Addresses
 32 Translation Look-aside Buffer processing
(TLB) entries
 Two UART interfaces to control the  Limited learned L2 MAC entry on each
internal CPU via a Command Line port and each VLAN
Interface (CLI)
 Supports EJTAG interface

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 L2 Miscellaneous Functions  Supports multiple actions
 Supports broadcast, multicast, unknown-  Supports L3 Unicast Routing, 512 next
multicast, and unknown-unicast packet hop MAC Support
suppression control
 QoS Functions
 Software supports IEEE 802.1x,
 8 physical queues per port
 Supports Port Mirroring
 Supports 4-sets of port mirrors  Strict Priority (SP) and Weighted Fair
 Flow-based mirror function Queue (WFQ), Weighted Round Robin
 RSPAN function for remote mirroring (WRR) packet scheduling
 Supports Link Aggregation (IEEE  QoS remarking for 802.1p and DSCP
802.3ad) for 8 groups of link aggregators (includes IPv4/IPv6)
with up to 8 ports per-group  Supports average packet rate control
 Port isolation function to enhance port leaky-bucket per queue, in 16Kbps steps
security up to 1Gbps maximum
 Attack Prevention  Ingress port bandwidth control, in
 Land attack 16Kbps steps up to 1Gbps maximum
 Blat attack  Egress port bandwidth control, in
 TCP control flag attack 16Kbps steps up to 1Gbps maximum
 Ping attack
 Packet length attack  EAV, 1588v2
 Supports Automatic loop detection and
isolation (RLPP/RLDP)  Cable Diagnostics (RTCT)

 Access Control List (ACL) Function  IEEE 802.3az Energy Efficient Ethernet
(EEE)
 1.5K-entry ACL table
 L2/L3/L4 format (e.g., DMAC, SMAC,  MIB Functions
and Ether-Type)  Ethernet-like MIB (RFC 3635)
 IPv6 Parsing  Interface Group MIB (RFC 2863)
 Per-flow traffic policing  RMON (RFC 2819)
 16-entry VID range checking  Bridge MIB (RFC 1493)
 8-entry IPv4 or 2-entry IPv6 range  Bridge MIB Extension (RFC 2674)
checking
 Others
 256 leaky-buckets for flow traffic
policing; in 16Kbps steps up to 1Gbps  55nm CMOS process
maximum  3.3V/1.1V dual power input
 256 log counters to enhance MIB count  LQFP216 E-PAD package
functionality

10/100/1000M Switch Controllers 3 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

3. System Applications
3.1. RTL8380M-VB: Managed 8*1000M UTP+2*1000Base-X
Switch

DDR1/DDR2/DDR3 Flash 8*1000M+2*1000Base-X

Switch with Embedded CPU

RTL8380M (8*1000M+2*1000Base-X Switch)

LQFP216-EPAD
8*1000Base-T

1000Base-X

1000Base-X
LED
Interface

Figure 1. Managed 8*1000M UTP+2*1000Base-X Switch

10/100/1000M Switch Controllers 4 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

3.2. RTL8382M-VB: Managed 28*1000M Switch via

RTL8218B PHY

DDR1/DDR2/DDR3* Flash Managed

28*1000M port Switch

RTL8382M (28*1000M Switch)

LQFP216-EPAD
QSGMII

QSGMII

QSGMII

QSGMII

QSGMII
8*1000Base-T

RTL8218B RTL8218B RTL8214FC

8*1000Base-T

8*1000Base-T

4*1000Base-T

4*1000Base-x
Copper
LED /fiber
Interface auto-det

Figure 2. Managed 28*1000M Switch via RTL8218B PHY

10/100/1000M Switch Controllers 5 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

3.3. RTL8382M-VB: Managed 20*1000M UTP+4*1000M

Combo Switch

DDR1/DDR2/DDR3* Flash Managed

24*1000M port Switch

RTL8382M (24*1000M Switch)

LQFP216-EPAD
QSGMII

QSGMII

QSGMII

QSGMII
8*1000Base-T

RTL8218B RTL8218FB
8*1000Base-T

4*1000Base-T

4*1000Base-T

4*1000Base-x
Copper
LED /fiber
Interface auto-det

Figure 3. Managed 20*1000M UTP+4*1000M Combo Switch

10/100/1000M Switch Controllers 6 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

3.4. RTL8382M-VB: Managed 24*1000M UTP+2*1000Base-X

Switch

DDR1/DDR2/DDR3* Flash Managed

24*1000M+2*1000Base-X Switch

RTL8382M (24*1000M+2*1000Base-X Switch)

LQFP216-EPAD
QSGMII

QSGMII

QSGMII

QSGMII
8*1000Base-T

1000Base-X

1000Base-X
RTL8218B RTL8218B
8*1000Base-T

8*1000Base-T

LED Interface

Figure 4. Managed 24*1000M UTP+2*1000Base-X Switch

10/100/1000M Switch Controllers 7 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

4. Block Diagrams
4.1. RTL8380M-VB Block Diagram

SGMII/ SGMII/
Scan or UART0 UART1 EJTAG DDR1/DDR2/ SPI Flash/ 1000Base-X/ 1000Base-X/
GPIO
Serial LED DDR3 I2C EEPROM 100Base-FX 100Base-FX

MIPS-4KEc Serdes0 Serdes1

32bits@500M
Hz Memory
LED GPIO 2*UART Controller
Controller Controller Controller
128KB
SRAM
EEPROM
/I2C/SPI
Register GMAC8 GMAC9

Controller Interrupt GMAC10

Controller and NIC
Packet Buffer (4.1 Mbit SRAM)

Flow Control Traffic Classification L2 and Forwarding Table 802.3ad

Qos Manager Storm Control VLAN Table Scheduler(SP/WRR/WFQ)
EEE 802.1x and STP ACL Table VLAN Tag/Untag
Attack Prevention Input Bandwidth Control Q-in-Q Table Output Bandwidth Control

MAC 0 MAC 2 MAC 4 MAC 6

MAC 1 MAC 3 MAC 5 MAC 7

PHY0~7 (Gigabit)

8*GE

Figure 5. RTL8380M-VB Block Diagram

10/100/1000M Switch Controllers 8 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

4.2. RTL8382M-VB Block Diagram

QSGMII/ SGMII/
Scan or DDR1/DDR2/ SPI Flash/ SGMII/1000Base-X 1000Base-X/
GPIO UART0 UART1 EJTAG
Serial LED DDR3 I2C EEPROM /100Base-FX 100Base-FX

MIPS-4KEc Serdes4 Serdes5

32bits@500M
Hz Memory
LED GPIO 2*UART Controller
Controller Controller Controller
128KB
SRAM MUX MUX

EEPROM
/I2C/SPI
GMAC24 GMAC26
Register GMAC25 GMAC27
Controller Interrupt GMAC28
Controller and NIC
Packet Buffer (4.1 Mbit SRAM)

Flow Control Traffic Classification L2 and Forwarding Table 802.3ad

Qos Manager Storm Control VLAN Table Scheduler(SP/WRR/WFQ)
EEE 802.1x and STP ACL Table VLAN Tag/Untag
Attack Prevetion Input Bandwidth Control Q-in-Q Table Output Bandwidth Control

MAC 8 MAC 10 MAC 12 MAC 14

MAC 0-3 MAC 4-7 MAC 9 MAC 11 MAC 13 MAC 15 MAC 16-19 MAC 20-23

Serdes 0 Serdes 1 Serdes 2 Serdes 3

PHY8~15 (Gigabit)

2*QSGMII 8*GE 2*QSGMII

Figure 6. RTL8382M-VB Block Diagram

10/100/1000M Switch Controllers 9 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

5. Pin Assignments and Description (RTL8380M-VB)

5.1. Pin Assignments Figure (RTL8380M-VB)

DDR12_A8/DDR3_A1/SDS_PDOWN_EN
DDR12_A6/DDR3_A8/SEL_XTAL_CLK
DDR12_A11/DDR3_A10/LED_MODE[0]
DDR12_A13/DDR3_A11/LED_MODE[1]

DDR12_A4/DDR3_A6/PWRBLINK[1]
DDR12_A2/DDR3_A4/PWRBLINK[0]
DDR12_A0/DDR3_A12/DIS_EEE

SSPI_SO/DIS_PHYAUTO_UP
DDR3_A14/SPI_ADDR_SEL

DDR12_CLK#/DDR3_CLK#
DDR12_RAS#/DDR3_CAS#
DDR12_CAS#/DDR3_RAS#

UART0_TX/REG_IF_SEL
DDR12_WE#/DDR3_WE#

DDR12_ODT/DDR3_CKE

DDR12_CLK/DDR3_CLK
DDR12_DQS/DDR3_DM

DDR12_DM/DDR3_DQS
DDR12_CS#/DDR3_BA1

DDR12_D5/DDR3_D5
DDR12_D2/DDR3_D7
DDR12_D0/DDR3_D1
DDR12_D7/DDR3_D3

DDR12_D6/DDR3_D0
DDR12_D1/DDR3_D4
DDR12_D3/DDR3_D2
DDR12_D4/DDR3_D6

SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
SPI_SO/SIO1
DDR3_DQS#

SPI_SI/SIO0

UART0_RX

LED_CLK
LED_DAT

SSPI_CS#
SPI_CS#0
SPI_CLK
MVDDH

MVDDH

RESET#
DVDDH

DVDDH
DVDDL

DVDDL

DVDDL

DVDDL
GPIO0
GPIO1
GPIO2
GPIO3
MDIO
VREF

MDC
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MVDDH 163 108 DVDDL
DDR3_BA2/DDR12_CKE 164 107 AVDDL_PLL
DDR3_A9/DDR12_BA1 165 106 XI
DDR3_A13/DDR12_A1/CPU_SLEEP 166 105 XO
DDR3_A2/DDR12_A12/DRAM_INI_EN 167 104 AVDDH_PLL
DDR3_RST# 168 103 SVDDL
DDR3_A7/DDR12_A9/MEM_TYPE[1] 169 102 S1RXP
DDRR3_A5/DDR12_A7/MEM_TYPE[0] 170 101 S1RXN
DDR3_A0/DDR12_A5/CLK_M_EE[1] 171 100 S1TXP
DDR3_A3/DDR12_A3/CLK_M_EE[0] 172 99 S1TXN
DDR3_BA0/DDR12_A10/EN_DECRYPT 173 98 SVDDL
DDR3_CS#/DDR2_BA2 174 97 S0RXN
DDR3_ODT/DDR12_BA0 175 96 S0RXP
DDR3_ZQ# 176 95 S0TXN
MVDDH 177 94 S0TXP
DVDDL 178 93 SVDDL
VX 179 92 CKOUT0

RTL8380M
RESERVED 180 91 SVDDH
SVDDL 181 90 TEST3
RESERVED 182 89 TEST2
RESERVED 183 88 RESERVED
TEST4 184 87 RESERVED
TEST5 185 86 SVDDL

LLLLLLL
SVDDH 186 85 TEST1
RESERVED 187 84 TEST0
RESERVED 188 83 RESERVED
TEST6 189 82 RESERVED
TEST7 190 81 SVDDL
SVDDL 191 80 RESERVED

GXXXV TAIWAN
DVDDL 192 79 DVDDL
AVDDH 193 78 AVDDH
P0MDIAP 194 77 P7MDIDN
P0MDIAN 195 76 P7MDIDP
P0MDIBP 196 75 P7MDICN
P0MDIBN 197 74 P7MDICP
AVDDL 198 73 AVDDL
P0MDICP 199 72 P7MDIBN
P0MDICN 200 71 P7MDIBP
P0MDIDP 201 70 P7MDIAN
P0MDIDN 202 69 P7MDIAP
AVDDH 203 68 AVDDH
P1MDIAP 204 67 P6MDIDN
P1MDIAN 205 66 P6MDIDP
P1MDIBP 206 65 P6MDICN
P1MDIBN 207 64 P6MDICP
AVDDL 208 63 AVDDL
P1MDICP 209 62 P6MDIBN
P1MDICN 210 61 P6MDIBP
P1MDIDP 211 60 P6MDIAN
P1MDIDN 212 59 P6MDIAP
PLLVDDL 213 58 ATESTCK1
ATESTCK0 214 57 PLLVDDL
P2MDIAP 215 56 P5MDIDN
P2MDIAN 216 55 P5MDIDP
54
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
1
2
3
4
5
6
7
8
9
P2MDIBP
P2MDIBN
AVDDL
P2MDICP
P2MDICN
P2MDIDP
P2MDIDN
AVDDH
P3MDIAP
P3MDIAN
P3MDIBP
P3MDIBN
AVDDL
AVDDH
P3MDICP
P3MDICN
P3MDIDP
P3MDIDN
AVDDH
AGND
MDIREF
AVDDL
RTT1
RTT2
AVDDH
DVDDL
DVDDH
JTAG_TCK
JTAG_TMS
JTAG_TDO/EEPROMTYPE
JTAG_TDI
JTAG_TRST#
DVDDL
DVDDL
DVDDH
AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN
AVDDH
AVDDL
P4MDICP
P4MDICN
P4MDIDP
P4MDIDN
AVDDH
P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
AVDDL
P5MDICP
P5MDICN

Figure 7. Pin Assignments (RTL8380M-VB)

5.2. Package Identification

Green package is indicated by a ‘G’ in ‘GXXXX’ (Figure 7). The version number is shown in the location
marked ‘V’.

10/100/1000M Switch Controllers 10 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

5.3. Pin Assignments Table Codes (RTL8380M-VB)

Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.

I: Input Pin AI: Analog Input Pin

O: Output Pin AO: Analog Output Pin

I/O: Bi-Directional Input/Output Pin AI/O: Analog Bi-Directional Input/Output Pin

P: Digital Power Pin AP: Analog Power Pin

G: Digital Ground Pin AG: Analog Ground Pin

IPU: Input Pin With Pull-Up Resistor; OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75KΩ) (Typical Value = 75KΩ)

IPD: Input Pin With Pull-Down Resistor; OPD: Output Pin With Pull-Down Resistor;
(Typical Value = 75KΩ) (Typical Value = 75KΩ)

5.4. Pin Assignments Table (RTL8380M-VB)

Table 1. Pin Assignments Table (RTL8380M-VB)
Name Pin No. Type Name Pin No. Type
P2MDIBP 1 AI/O AVDDH 19 AP
P2MDIBN 2 AI/O AGND 20 AG
AVDDL 3 AP MDIREF 21 AO
P2MDICP 4 AI/O AVDDL 22 AP
P2MDICN 5 AI/O RTT1 23 AI/O
P2MDIDP 6 AI/O RTT2 24 AI/O
P2MDIDN 7 AI/O AVDDH 25 AP
AVDDH 8 AP DVDDL 26 DP
P3MDIAP 9 AI/O DVDDH 27 DP
P3MDIAN 10 AI/O JTAG_TCK 28 I/OPU
P3MDIBP 11 AI/O JTAG_TMS 29 I/OPU
P3MDIBN 12 AI/O JTAG_TDO/EEPROMTYPE 30 I/OPD
AVDDL 13 AP JTAG_TDI 31 I/OPD
AVDDH 14 AP JTAG_TRST# 32 I/OPU
P3MDICP 15 AI/O DVDDL 33 DP
P3MDICN 16 AI/O DVDDL 34 DP
P3MDIDP 17 AI/O DVDDH 35 DP
P3MDIDN 18 AI/O AVDDH 36 AP

10/100/1000M Switch Controllers 11 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet
Name Pin No. Type Name Pin No. Type
P4MDIAP 37 AI/O AVDDH 78 AP
P4MDIAN 38 AI/O DVDDL 79 DP
P4MDIBP 39 AI/O RESERVED 80 -
P4MDIBN 40 AI/O SVDDL 81 AP
AVDDH 41 AP RESERVED 82 -
AVDDL 42 AP RESERVED 83 -
P4MDICP 43 AI/O TEST0 84 -
P4MDICN 44 AI/O TEST1 85 -
P4MDIDP 45 AI/O SVDDL 86 AP
P4MDIDN 46 AI/O RESERVED 87 -
AVDDH 47 AP RESERVED 88 -
P5MDIAP 48 AI/O TEST2 89 -
P5MDIAN 49 AI/O TEST3 90 -
P5MDIBP 50 AI/O SVDDH 91 AP
P5MDIBN 51 AI/O CKOUT0 92 AO
AVDDL 52 AP SVDDL 93 AP
P5MDICP 53 AI/O S0TXP 94 AO
P5MDICN 54 AI/O S0TXN 95 AO
P5MDIDP 55 AI/O S0RXP 96 AI
P5MDIDN 56 AI/O S0RXN 97 AI
PLLVDDL 57 AP SVDDL 98 AP
ATESTCK1 58 AO S1TXN 99 AO
P6MDIAP 59 AI/O S1TXP 100 AO
P6MDIAN 60 AI/O S1RXN 101 AI
P6MDIBP 61 AI/O S1RXP 102 AI
P6MDIBN 62 AI/O SVDDL 103 AP
AVDDL 63 AP AVDDH_PLL 104 AP
P6MDICP 64 AI/O XO 105 AO
P6MDICN 65 AI/O XI 106 AI
P6MDIDP 66 AI/O AVDDL_PLL 107 AP
P6MDIDN 67 AI/O DVDDL 108 P
AVDDH 68 AP DVDDL 109 P
P7MDIAP 69 AI/O GPIO3 110 I/OPD
P7MDIAN 70 AI/O GPIO2 111 I/OPD
P7MDIBP 71 AI/O GPIO1 112 I/OPD
P7MDIBN 72 AI/O GPIO0 113 I/OPD
AVDDL 73 AP RESET# 114 AI
P7MDICP 74 AI/O DVDDH 115 P
P7MDICN 75 AI/O SSPI_CS# 116 IPU
P7MDIDP 76 AI/O SSPI_SO/ 117 I/OPD
P7MDIDN 77 AI/O DIS_PHYAUTO_UP
SSPI_SI/I2C_DAT 118 I/OPU

10/100/1000M Switch Controllers 13 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet
Name Pin No. Type Name Pin No. Type
SSPI_CLK/I2C_CLK 119 I/OPU DDR12_A13/DDR3_A11/ 156 I/O
MDC 120 OPU LED/MODE[1]
MDIO 121 I/OPU DDR12_A11/DDR3_A10/ 157 I/O
LED/MODE[0]
LED_CLK 122 OPU
DDR12_CAS#/DDR3_RAS# 158 O
LED_DAT 123 I/OPU
DDR12_RAS#/DDR3_CAS# 159 O
UART0_TX/REG_IF_SEL 124 I/OPD
DVDDL 160 P
UART0_RX 125 IPD
DDR12_WE#/DDR3_WE# 161 O
DVDDL 126 P
MVDDH 162 P
SPI_CS#0 127 IPU
MVDDH 163 P
SPI_SI/SIO0 128 I/OPD
DDR12_CKE/DDR3_BA2 164 O
SPI_SO/SIO1 129 I/OPD
DDR12_BA1/DDR3_A9 165 O
SPI_CLK 130 OPD
DDR12_A1/DDR3_A13/ 166 I/O
DVDDH 131 P CPU_SLEEP
MVDDH 132 P DDR12_A12/DDR3_A2/ 167 I/O
DDR12_D4/DDR3_D6 133 I/O DRAM_INI_EN
DDR12_D3/DDR3_D2 134 I/O DDR3_RST# 168 O
DDR12_D1/DDR3_D4 135 I/O DDR12_A9/DDR3_A7/ 169 I/O
MEM_TYPE[1]
DDR12_D6/DDR3_D0 136 I/O
DDR12_A7/DDR3_A5/ 170 I/O
DDR12_DM/DDR3_DQS 137 I/O MEM_TYPE[0]
DDR3_DQS# 138 I/O DDR12_A5/DDR3_A0/ 171 I/O
DVDDL 139 P CLK_M_EE[1]
DDR12_CLK#/DDR3_CLK# 140 O DDR12_A3/DDR3_A3/ 172 I/O
DDR12_CLK/DDR3_CLK 141 O CLK_M_EE[0]
DDR12_A10/DDR3_BA0/ 173 I/O
DDR12_DQS/DDR3_DM 142 I/O
EN_DECRYPT
VREF 143 P
DDR2_BA2/DDR3_CS# 174 O
DDR12_D7/DDR3_D3 144 I/O
DDR12_BA0/DDR3_ODT 175 O
DDR12_D0/DDR3_D1 145 I/O
DDR3_ZQ# 176 O
DDR12_D2/DDR3_D7 146 I/O
MVDDH 177 P
DDR12_D5/DDR3_D5 147 I/O
DVDDL 178 P
DDR2_ODT/DDR3_CKE 148 O
VX 179 A
DDR12_CS#/DDR3_BA1 149 O
RESERVED 180 AO
DDR12_A0/DDR3_A12/ 150 I/O
SVDDL 181 AP
DIS_EEE
RESERVED 182 AO
DDR12_A2/DDR3_A4/ 151 I/O
PWRBLINK[0] RESERVED 183 AO
DDR12_A4/DDR3_A6/ 152 I/O TEST4 184 -
PWRBLINK[1] TEST5 185 -
DDR12_A6/DDR3_A8/ 153 I/O SVDDH 186 AP
SEL_XTAL_CLK
RESERVED 187 AO
DDR12_A8/DDR3_A1/ 154 I/O
SDS_PDOWN_EN RESERVED 188 AO
DDR3_A14/SPI_ADDR_SEL 155 I/O TEST6 189 -
TEST7 190 -

10/100/1000M Switch Controllers 14 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet
Name Pin No. Type Name Pin No. Type
SVDDL 191 AP P1MDIAN 205 AI/O
DVDDL 192 P P1MDIBP 206 AI/O
AVDDH 193 AP P1MDIBN 207 AI/O
P0MDIAP 194 AI/O AVDDL 208 AP
P0MDIAN 195 AI/O P1MDICP 209 AI/O
P0MDIBP 196 AI/O P1MDICN 210 AI/O
P0MDIBN 197 AI/O P1MDIDP 211 AI/O
AVDDL 198 AP P1MDIDN 212 AI/O
P0MDICP 199 AI/O PLLVDDL 213 AP
P0MDICN 200 AI/O ATESTCK0 214 AO
P0MDIDP 201 AI/O P2MDIAP 215 AI/O
P0MDIDN 202 AI/O P2MDIAN 216 AI/O
AVDDH 203 AP DGND EPAD G
P1MDIAP 204 AI/O

10/100/1000M Switch Controllers 15 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

5.5. Pin Descriptions (RTL8380M-VB)

5.5.1. 1000M Ethernet PHY MDI Interface Pins
Table 2. 1000M Ethernet PHY MDI Interface Pins
Pin Name Pin No. Type Description
P0MDIAP 194 AI/O Port 0 Media Dependent Interface A~D.
P0MDIAN 195 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P0MDIBP 196 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P0MDIBN 197 AI/O MDIAP/N and MDIBP/N.
P0MDICP 199 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P0MDICN 200 AI/O
P0MDIDP 201 AI/O
P0MDIDN 202 AI/O
P1MDIAP 204 AI/O Port 1 Media Dependent Interface A~D.
P1MDIAN 205 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P1MDIBP 206 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P1MDIBN 207 AI/O MDIAP/N and MDIBP/N.
P1MDICP 209 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P1MDICN 210 AI/O
P1MDIDP 211 AI/O
P1MDIDN 212 AI/O
P2MDIAP 215 AI/O Port 2 Media Dependent Interface A~D.
P2MDIAN 216 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P2MDIBP 1 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P2MDIBN 2 AI/O MDIAP/N and MDIBP/N.
P2MDICP 4 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P2MDICN 5 AI/O
P2MDIDP 6 AI/O
P2MDIDN 7 AI/O
P3MDIAP 9 AI/O Port 3 Media Dependent Interface A~D.
P3MDIAN 10 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P3MDIBP 11 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P3MDIBN 12 AI/O MDIAP/N and MDIBP/N.
P3MDICP 15 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P3MDICN 16 AI/O
P3MDIDP 17 AI/O
P3MDIDN 18 AI/O

10/100/1000M Switch Controllers 16 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet
Pin Name Pin No. Type Description
P4MDIAP 37 AI/O Port 4 Media Dependent Interface A~D.
P4MDIAN 38 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P4MDIBP 39 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P4MDIBN 40 AI/O MDIAP/N and MDIBP/N.
P4MDICP 43 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P4MDICN 44 AI/O
P4MDIDP 45 AI/O
P4MDIDN 46 AI/O
P5MDIAP 48 AI/O Port 5 Media Dependent Interface A~D.
P5MDIAN 49 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P5MDIBP 50 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P5MDIBN 51 AI/O MDIAP/N and MDIBP/N.
P5MDICP 53 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P5MDICN 54 AI/O
P5MDIDP 55 AI/O
P5MDIDN 56 AI/O
P6MDIAP 59 AI/O Port 6 Media Dependent Interface A~D.
P6MDIAN 60 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P6MDIBP 61 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P6MDIBN 62 AI/O MDIAP/N and MDIBP/N.
P6MDICP 64 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P6MDICN 65 AI/O
P6MDIDP 66 AI/O
P6MDIDN 67 AI/O
P7MDIAP 69 AI/O Port 7 Media Dependent Interface A~D.
P7MDIAN 70 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P7MDIBP 71 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P7MDIBN 72 AI/O MDIAP/N and MDIBP/N.
P7MDICP 74 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P7MDICN 75 AI/O
P7MDIDP 76 AI/O
P7MDIDN 77 AI/O

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 RTL8380M-VB/RTL8382M-VB
Datasheet

5.5.2. SGMII Interface Pins

Table 3. SGMII Interface Pins
Pin Name Pin No. Type Description
S0RXP 96 AI SGMII Interface Receive Data Differential Input Pair.
S0RXN 97 AI
S0TXP 94 AO SGMII Interface Transmit Data Differential Output Pair.
S0TXN 95 AO
S1RXP 102 AI SGMII Interface Receive Data Differential Input Pair.
S1RXN 101 AI
S1TXP 100 AO SGMII Interface Transmit Data Differential Output Pair.
S1TXN 99 AO

5.5.3. 1000Base-X/100Base-FX Interface Pins

Table 4. 1000Base-X/100Base-FX Interface Pins
Pin Name Pin No. Type Description
S0RXP 96 AI 1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
S0RXN 97 AI
S0TXP 94 AO 1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
S0TXN 95 AO
S1RXP 102 AI 1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
S1RXN 101 AI
S1TXP 100 AO 1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
S1TXN 99 AO

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 RTL8380M-VB/RTL8382M-VB
Datasheet

5.5.4. DDR1/2 SDRAM Interface Pins

Table 5. DDR1/2 SDRAM Interface Pins
Pin Name Pin No. Type Drive (mA) Description
DDR12_D[7:0] 144, 136, 147, 133, I/O 8 DDR SDRAM Data Bus.
134, 146, 135, 145
DDR12_A[13:0] 156, 167, 157, 173, I/O 8 DDR SDRAM Address Select.
169, 154, 170, 153,
171, 152, 172, 151,
166, 150
DDR2_BA[2] 174 O 8 DDR SDRAM Bank Address Select.
DDR12_BA[1:0] 165, 175 O 8 DDR SDRAM Bank Address Select.
DDR12_WE# 161 O 8 DDR SDRAM Write Enable.
DDR12_CKE 164 O 8 DDR SDRAM Clock Enable.
DDR12_RAS# 159 O 8 DDR SDRAM Row Address Strobe.
DDR12_CAS# 158 O 8 DDR SDRAM Column Address Strobe.
DDR12_CS#0 149 O 8 DDR SDRAM Chip Select 0.
DDR2_ODT 148 O 8 DDR SDRAM On-Die Termination.
DDR12_DQS 142 I/O 8 DDR SDRAM Data Strobe.
DDR12_CLK 141 O 8 DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.
DDR12_CLK# 140 O 8 DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.

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 RTL8380M-VB/RTL8382M-VB
Datasheet

5.5.5. DDR3 SDRAM Interface Pins

Table 6. DDR3 SDRAM Interface Pins
Pin Name Pin No. Type Drive (mA) Description
DDR3_D[7:0] 146, 133, 147, 135, I/O 8 DDR SDRAM Data Bus.
144, 134, 145, 136
DDR3_A[14] 155 O 8 DDR SDRAM Address Select.
DDR3_A[13:10] 166, 150,156, 157 I/O 8 DDR SDRAM Address Select.
DDR3_A[9] 165 O 8 DDR SDRAM Address Select.
DDR3_A[8:0] 153, 169, 152, 170, I/O 8 DDR SDRAM Address Select.
151, 172, 167, 154,
171
DDR3_DQS# 138 I/O 8 DDR SDRAM Data Strobe.
DDR3_DQS 137 I/O 8 DDR SDRAM Data Strobe.
DDR3_CLK# 140 O 8 DDR SDRAM Clock.
DDR3_CLK 141 O 8 DDR SDRAM Clock.
DDR3_DM 142 I/O 8 DDR SDRAM Data Mask.
DDR3_CKE 148 O 8 DDR SDRAM Clock Enable.
DDR3_BA[2:1] 164, 149 O 8 DDR SDRAM Bank Address Select.
DDR3_BA[0] 173 I/O 8 DDR SDRAM Bank Address Select.
DDR3_RAS# 158 O 8 DDR SDRAM Row Address Strobe.
DDR3_CAS# 159 O 8 DDR SDRAM Column Address Strobe.
DDR3_WE# 161 O 8 DDR SDRAM Write Enable.
DDR3_RST# 168 O 8 DDR SDRAM Reset.
DDR3_CS# 174 O 8 DDR SDRAM Chip Select.
DDR3_ODT 175 O 8 DDR SDRAM On-Die Termination.
DDR3_ZQ# 176 O 8 DDR SDRAM External Reference Ball for Output
Drive Calibration.
This ball is tied to an external 240 Ohm resistor, which
is tied to GND.

5.5.6. Master Mode SPI Flash Interface Pins

Table 7. Master Mode SPI Flash Interface Pins
Pin Name Pin No. Type Drive (mA) Description
SPI_CLK 130 OPD 12 Serial Clock Output Pin.
SPI_SO/SIO1 129 I/OPD 12 In Serial Mode: This is a flash chip output pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is MSB first.
SPI_SI/SIO0 128 I/OPD 12 In Serial Mode: This is a flash chip input pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is LSB first.
SPI_CS#0 127 O 12 Chip Select Output Pin.
Slave Transmit Enable and active low.

10/100/1000M Switch Controllers 20 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

5.5.7. UART Interface Pins

Table 8. UART Interface Pins
Pin Name Pin No. Type Drive (mA) Description
UART0_RX 125 IPD 4 UART0 Interface Receive Data.
UART0_TX 124 I/OPD 4 UART0 Interface Transmit Data.
UART1_RX 116 IPU 4 UART1 Interface Receive Data.
UART1_TX 117 I/OPD 4 UART1 Interface Transmit Data.

5.5.8. LED Interface Pins

Table 9. LED Interface Pins
Pin Name Pin No. Type Drive (mA) Description
LED_CLK 122 OPU 12 (1) In Serial LED Mode
Reference output clock for serial LED interface and Data is
latched on the rising of LEDCK.
(2) In SMI-like LED Mode
Reference output clock for I2C-like interface.
LED_DAT 123 I/OPU 12 (1) In Serial LED Mode
Serial bit stream of link status information.
(2) In I2C-like LED Mode
The data written to the LED IC.

5.5.9. GPIO Interface Pins

Table 10. GPIO Interface Pins
Pin Name Pin No. Type Drive (mA) Description
This pin default set as system LED.
GPIO0 113 I/OPD 4 Can be configured as General Purpose
Input/Output Pin.
GPIO[3:1] 110, 111, 112 I/OPD 4 General Purpose Input/Output Pins.
GPO10 30 I/OPD 4 General Purpose Output Pins.
GPIO11 31 I/OPD 4 General Purpose Input/Output Pins.
GPIO[14:12] 32,28,29 I/OPU 4 General Purpose Input/Output Pins.

5.5.10. EJTAG Interface Pins

Table 11. EJTAG Interface Pins
Pin Name Pin No. Type Drive (mA) Description
JTAG_TMS 29 I/OPU 4 JTAG Test Mode Select.
JTAG_TCK 28 I/OPU 4 JTAG Test Clock Input.
JTAG_TRST# 32 I/OPU 4 JTAG Test Reset.
JTAG_TDI 31 I/OPD 4 JTAG Test Data Input.
JTAG_TDO 30 I/OPD 4 JTAG Test Data Output.

10/100/1000M Switch Controllers 21 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

5.5.11. Configuration Strapping Pins

Table 12. Configuration Strapping Pins
Pin Name Pin No. Default Description
EEPROMTYPE 30 0b0 Select EEPROM Address Byte Size.
0b0: 1-byte 0b1: 2-byte
DIS_PHYAUTO_UP 117 0b0 Disable ASIC Auto Power Up PHY.
0b0: Enable ASIC auto power up PHY
0b1: Disable ASIC auto power up PHY
REG_IF_SEL 124 0b0 Select Switch Core Register Access Interface.
0b0: I2C 0b1: SPI slave
DIS_EEE 150 0b0 Disable 1000M EEE and 100M EEE Function.
0b0: Enable 0b1: Disable
PWRBLINK[1:0] 152, 151 0b00 Select LED Power On Blinking Timer.
0b00: Disable 0b01: 800ms
0b10: 1.6s 0b11:3.2s
SEL_XTAL_CLK 153 0b0 Select XTAL Input is 25M or 125M.
0b0: 25M 0b1:125M
Note: This option is only for sync Ethernet.
SDS_PDOWN_EN 154 0b0 Enable SerDes Power Down Mode.
0b0: SerDes 0/1 operate in normal mode
0b1: SerDes0/1 operate in power down mode
SPI_ADDR_SEL 155 0b0 Select Address Mode for SPI Flash.
0b0: 3-byte address 0b1: 4-byte address
LED_MODE[1:0] 156, 157 0b0 Select LED Mode.
0b00: Serial LED mode 0b01: Scan Single mode
0b10: Scan Bicolor mode 0b11: Disable LED
CPU_SLEEP 166 0b0 Enable CPU Function.
0b0: CPU is always under reset state
0b1: CPU is enabled
DRAM_INI_EN 167 0b0 Enable DRAM Initialization Procedure.
0b0: Enable DRAM Initialization procedure
0b1: Bypass DRAM Initialization procedure
MEM_TYPE[1:0] 169, 170 0b00 Select Memory Type for SOC.
0b00: Select SPI flash + DDR-3 0b01: Select SPI flash + DDR-2
0b10: Select SPI flash + DDR-1 0b11: Select EEPROM

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 RTL8380M-VB/RTL8382M-VB
Datasheet
Pin Name Pin No. Default Description
CLK_M_EE[1:0] 171, 172 0b00 When MEM_TYPE Select is SPI Flash:
This Strapping Pin Selects the Initial Clock for The Memory Controller.
For DDR2:
0b00: Reserved for test; 0b01: Reserved for test;
0b10: 100MHz 0b11: Reserved for test;
For DDR3:
0b00: Reserved for test; 0b01: Reserved for test;
0b10: 125MHz 0b11: Reserved for test;
Note: The initial value for this strapping pin must be set as recommended
in the reference design guide.

When MEM_TYPE Select is EEPROM:

CLK_M_EE[0] is used to select SOC EEPROM address byte size.
0b0: 1-byte address 0b1: 2-byte address
EN_DECRYPT 173 0b0 Enable or Disable Decrypt for Flash.
0b0: Disable decrypt 0b1: Enable decrypt

5.5.12. Miscellaneous Interface Pins

Table 13. Miscellaneous Interface Pins
Pin Name Pin No. Type Drive (mA) Description
MDC 120 OPU 12 MII Management Interface Clock Pin.
MDIO 121 I/OPU 12 MII Management Interface Data Pin.
SSPI_CLK/I2C_CLK 119 I/OPU 4 SPI Serial Clock Input (Slave Mode).
I2C Interface Clock Input (Slave Mode).
I2C Interface Clock Output (Master Mode).
SSPI_SI/I2C_DAT 118 I/OPU 4 SPI Serial Data Input (Slave Mode).
I2C Interface Bi-Directional data (Slave Mode).
SSPI_SO 117 I/OPD 4 SPI Serial Data Output (Slave Mode).
SSPI_CS# 116 IUP 4 SPI Serial Chip Select (Slave Mode).
RESET# 114 AI - System Pin Reset Input (Low Active).
To complete the reset function, this pin must be asserted
for at least 10ms. It must be pulled up for normal
operation.
XI 106 AI - 25MHz Crystal Clock Input and Feedback Pin.
XO 105 AO - 25MHz Crystal Clock Output Pin.
MDIREF 21 AO - MDI Bias Resistor.
Adjust the reference current for all PHYs. This pin must
connect to AGND via a 2.49k ohm resistor.
RTT1 23 AI/O - Reserved for Internal Use (Must be Left Floating).
RTT2 24 AI/O - Reserved for Internal Use (Must be Left Floating).
VX 179 A - Low Voltage Power Control Resistor.
CKOUT0 92 AO 8 25MHz Clock Output.
ATESTCK[1:0] 58, 214 AO - Reserved for Internal Use (Must be Left Floating).
RESERVED 82, 83, 87, 88, - - Reserved pins (Must be Left Floating).
180, 182, 183,
187, 188

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 RTL8380M-VB/RTL8382M-VB
Datasheet
Pin Name Pin No. Type Drive (mA) Description
TEST[7:0] 84, 85, 89, 90, - - Reserved for Testing.
184, 185, 189,
190

5.5.13. Power and Ground Pins

Table 14. Power and Ground Pins
Pin Name Pin No. Type Description
AVDDL 3, 13, 22, 42, 52, 63, AP Analog Low Voltage Power.
73, 198, 208
PLLVDDL 57, 213 AP Analog PLL Low Voltage Power.
AVDDH 8, 14, 19, 25, 36, 41, AP Analog High Voltage Power.
47, 68, 78, 193, 203
DVDDL 26, 33, 34, 79, 108, P Digital Low Voltage Power.
109, 126, 139, 160,
178, 192
DVDDH 27, 35, 115, 131 P Digital High Voltage Power.
SVDDL 81, 86, 93, 98, 103, AP SerDes Low Voltage Power.
181, 191
AVDDL_PLL 107 AP PLL Low Voltage Power.
SVDDH 91, 186 AP SerDes High Voltage Power.
AVDDH_PLL 104 AP PLL High Voltage Power.
MVDDH 132, 162, 163,177 P SDRAM High Voltage Power.
VREF 143 P SSTL Reference Voltage (MVDDH/2).
AGND 20 AG Analog Ground.
DGND E-PAD G Digital Ground.

10/100/1000M Switch Controllers 24 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

6. Pin Assignments and Description (RTL8382M-VB)

6.1. Pin Assignments Figure (RTL8382M-VB)

DDR12_A8/DDR3_A1/SDS_PDOWN_EN
DDR12_A6/DDR3_A8/SEL_XTAL_CLK
DDR12_A11/DDR3_A10/LED_MODE[0]
DDR12_A13/DDR3_A11/LED_MODE[1]

DDR12_A2/DDR3_A4/PWRBLINK[0]
DDR12_A4/DDR3_A6/PWRBLINK[1]

DDR12_A0/DDR3_A12/DIS_EEE

SSPI_SO/DIS_PHYAUTO_UP
DDR3_A14/SPI_ADDR_SEL

DDR12_CLK#/DDR3_CLK#
DDR12_RAS#/DDR3_CAS#
DDR12_CAS#/DDR3_RAS#
DDR12_WE#/DDR3_WE#

DDR12_CLK/DDR3_CLK

UART0_TX/REG_IF_SEL
DDR2_ODT/DDR3_CKE
DDR12_CS#/DDR3_BA1

DDR12_DM/DDR3_DQS
DDR12_DQS/DDR3_DM
DDR12_D5/DDR3_D5
DDR12_D2/DDR3_D7
DDR12_D0/DDR3_D1
DDR12_D7/DDR3_D3

DDR12_D6/DDR3_D0
DDR12_D1/DDR3_D4
DDR12_D3/DDR3_D2
DDR12_D4/DDR3_D6

SSPI_CLK/I2C_CLK
SSPI_SI/I2C_DAT
SPI_SO/SIO1
DDR3_DQS#

SPI_SI/SIO0

UART0_RX

LED_CLK
LED_DAT

SSPI_CS#
SPI_CS#0
SPI_CLK
MVDDH

MVDDH

DVDDL
RESET#
DVDDL
DVDDH

DVDDH
DVDDL

DVDDL

GPIO0
GPIO1

GPIO3
GPIO2
MDIO
VREF

MDC
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
MVDDH 163 108 DVDDL
DDR12_CKE/DDR3_BA2 164 107 AVDDL_PLL
DDR12_BA1/DDR3_A9 165 106 XI
DDR12_A1/DDR3_A13/CPU_SLEEP 166 105 XO
DDR12_A12/DDR3_A2/DRAM_INI_EN 167 104 AVDDH_PLL
DDR3_RST# 168 103 SVDDL
DDR12_A9/DDR3_A7/MEM_TYPE[1] 169 102 S5RXP
DDR12_A7/DDR3_A5/MEM_TYPE[0] 170 101 S5RXN
DDR12_A5/DDR3_A0/CLK_M_EE[1] 171 100 S5TXP
DDR12_A3/DDR3_A3/CLK_M_EE[0] 172 99 S5TXN
DDR12_A10/DDR3_BA0/EN_DECRYPT 173 98 SVDDL
DDR2_BA2/DDR3_CS# 174 97 S4RXN
DDR12_BA0/DDR3_ODT 175 96 S4RXP
DDR3_ZQ# 176 95 S4TXN
MVDDH 177 94 S4TXP
DVDDL 178 93 SVDDL
VX 179 92 CKOUT4

RTL8382M
CKOUT0 180 91 SVDDH
SVDDL 181 90 S3RXP
S0TXP 182 89 S3RXN
S0TXN 183 88 S3TXP
S0RXP 184 87 S3TXN
S0RXN 185 86 SVDDL

LLLLLLL
SVDDH 186 85 S2RXN
S1TXN 187 84 S2RXP
S1TXP 188 83 S2TXN
S1RXN 189 82 S2TXP
S1RXP 190 81 SVDDL
SVDDL 191 80 CKOUT2

GXXXV TAIWAN
DVDDL 192 79 DVDDL
AVDDH 193 78 AVDDH
P0MDIAP 194 77 P7MDIDN
P0MDIAN 195 76 P7MDIDP
P0MDIBP 196 75 P7MDICN
P0MDIBN 197 74 P7MDICP
AVDDL 198 73 AVDDL
P0MDICP 199 72 P7MDIBN
P0MDICN 200 71 P7MDIBP
P0MDIDP 201 70 P7MDIAN
P0MDIDN 202 69 P7MDIAP
AVDDH 203 68 AVDDH
P1MDIAP 204 67 P6MDIDN
P1MDIAN 205 66 P6MDIDP
P1MDIBP 206 65 P6MDICN
P1MDIBN 207 64 P6MDICP
AVDDL 208 63 AVDDL
P1MDICP 209 62 P6MDIBN
P1MDICN 210 61 P6MDIBP
P1MDIDP 211 60 P6MDIAN
P1MDIDN 212 59 P6MDIAP
PLLVDDL 213 58 ATESTCK1
ATESTCK0 214 57 PLLVDDL
P2MDIAP 215 56 P5MDIDN
P2MDIAN 216 55 P5MDIDP
54
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
1
2
3
4
5
6
7
8
9

DVDDL
DVDDL

AVDDH
P4MDIAP
P4MDIAN
P4MDIBP
P4MDIBN

P4MDICP
P4MDICN
P4MDIDP
P4MDIDN

P5MDIAP
P5MDIAN
P5MDIBP
P5MDIBN
P3MDIAN

P5MDICP
P5MDICN
P2MDIDP
P2MDIDN

AVDDL

MDIREF
AVDDL
P3MDIAP

P3MDIBN

RTT1
RTT2
AVDDL
P2MDICP
P2MDICN

AVDDH

P3MDIDN
P3MDICP
P3MDICN
P3MDIDP
P3MDIBP

AVDDH

DVDDL
DVDDH

DVDDH
AVDDH

AVDDH
AVDDH
AVDDH

AVDDL

AVDDL
AGND
P2MDIBP
P2MDIBN

JTAG_TRST#
JTAG_TDO/EEPROMTYPE
JTAG_TMS
JTAG_TCK

JTAG_TDI

Figure 8. Pin Assignments (RTL8382M-VB)

6.2. Package Identification

Green package is indicated by a ‘G’ in ‘GXXXX’ (Figure 8). The version number is shown in the
location marked ‘v’.

10/100/1000M Switch Controllers 25 Track ID: Rev. 1.2

 RTL8380M-VB/RTL8382M-VB
Datasheet

6.3. Pin Assignments Table Codes (RTL8382M-VB)

Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.

I: Input Pin AI: Analog Input Pin

O: Output Pin AO: Analog Output Pin

I/O: Bi-Directional Input/Output Pin AI/O: Analog Bi-Directional Input/Output Pin

P: Digital Power Pin AP: Analog Power Pin

G: Digital Ground Pin AG: Analog Ground Pin

IPU: Input Pin With Pull-Up Resistor; OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75KΩ) (Typical Value = 75KΩ)

IPD: Input Pin With Pull-Down Resistor; OPD: Output Pin With Pull-Down Resistor;
(Typical Value = 75KΩ) (Typical Value = 75KΩ)

6.4. Pin Assignments Table (RTL8382M-VB)

Table 15. Pin Assignments Table (RTL8382M-VB)
Name Pin No. Type Name Pin No. Type
P2MDIBP 1 AI/O AVDDH 19 AP
P2MDIBN 2 AI/O AGND 20 AG
AVDDL 3 AP MDIREF 21 AO
P2MDICP 4 AI/O AVDDL 22 AP
P2MDICN 5 AI/O RTT1 23 AI/O
P2MDIDP 6 AI/O RTT2 24 AI/O
P2MDIDN 7 AI/O AVDDH 25 AP
AVDDH 8 AP DVDDL 26 DP
P3MDIAP 9 AI/O DVDDH 27 DP
P3MDIAN 10 AI/O JTAG_TCK 28 I/OPU
P3MDIBP 11 AI/O JTAG_TMS 29 I/OPU
P3MDIBN 12 AI/O JTAG_TDO/EEPROMTYPE 30 I/OPD
AVDDL 13 AP JTAG_TDI 31 I/OPD
AVDDH 14 AP JTAG_TRST# 32 I/OPU
P3MDICP 15 AI/O DVDDL 33 DP
P3MDICN 16 AI/O DVDDL 34 DP
P3MDIDP 17 AI/O DVDDH 35 DP
P3MDIDN 18 AI/O AVDDH 36 AP

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 RTL8380M-VB/RTL8382M-VB
Datasheet
Name Pin No. Type Name Pin No. Type
P4MDIAP 37 AI/O AVDDH 78 AP
P4MDIAN 38 AI/O DVDDL 79 DP
P4MDIBP 39 AI/O CKOUT2 80 AO
P4MDIBN 40 AI/O SVDDL 81 AP
AVDDH 41 AP S2TXP 82 AO
AVDDL 42 AP S2TXN 83 AO
P4MDICP 43 AI/O S2RXP 84 AI
P4MDICN 44 AI/O S2RXN 85 AI
P4MDIDP 45 AI/O SVDDL 86 AP
P4MDIDN 46 AI/O S3TXN 87 AO
AVDDH 47 AP S3TXP 88 AO
P5MDIAP 48 AI/O S3RXN 89 AI
P5MDIAN 49 AI/O S3RXP 90 AI
P5MDIBP 50 AI/O SVDDH 91 AP
P5MDIBN 51 AI/O CKOUT4 92 AO
AVDDL 52 AP SVDDL 93 AP
P5MDICP 53 AI/O S4TXP 94 AO
P5MDICN 54 AI/O S4TXN 95 AO
P5MDIDP 55 AI/O S4RXP 96 AI
P5MDIDN 56 AI/O S4RXN 97 AI
PLLVDDL 57 AP SVDDL 98 AP
ATESTCK1 58 AO S5TXN 99 AO
P6MDIAP 59 AI/O S5TXP 100 AO
P6MDIAN 60 AI/O S5RXN 101 AI
P6MDIBP 61 AI/O S5RXP 102 AI
P6MDIBN 62 AI/O SVDDL 103 AP
AVDDL 63 AP AVDDH_PLL 104 AP
P6MDICP 64 AI/O XO 105 AO
P6MDICN 65 AI/O XI 106 AI
P6MDIDP 66 AI/O AVDDL_PLL 107 AP
P6MDIDN 67 AI/O DVDDL 108 P
AVDDH 68 AP DVDDL 109 P
P7MDIAP 69 AI/O GPIO3 110 I/OPD
P7MDIAN 70 AI/O GPIO2 111 I/OPD
P7MDIBP 71 AI/O GPIO1 112 I/OPD
P7MDIBN 72 AI/O GPIO0 113 I/OPD
AVDDL 73 AP RESET# 114 AI
P7MDICP 74 AI/O DVDDH 115 P
P7MDICN 75 AI/O SSPI_CS# 116 IPU
P7MDIDP 76 AI/O SSPI_SO/ 117 I/OPD
P7MDIDN 77 AI/O DIS_PHYAUTO_UP
SSPI_SI/I2C_DAT 118 I/OPU

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 RTL8380M-VB/RTL8382M-VB
Datasheet
Name Pin No. Type Name Pin No. Type
SSPI_CLK/I2C_CLK 119 I/OPU DDR12_A13/DDR3_A11/ 156 I/O
MDC 120 OPU LED/MODE[1]
MDIO 121 I/OPU DDR12_A11/DDR3_A10/ 157 I/O
LED/MODE[0]
LED_CLK 122 OPU
DDR12_CAS#/DDR3_RAS# 158 O
LED_DAT 123 I/OPU
DDR12_RAS#/DDR3_CAS# 159 O
UART0_TX/REG_IF_SEL 124 I/OPD
DVDDL 160 P
UART0_RX 125 IPD
DDR12_WE#/DDR3_WE# 161 O
DVDDL 126 P
MVDDH 162 P
SPI_CS#0 127 O
MVDDH 163 P
SPI_SI/SIO0 128 I/OPD
DDR12_CKE/DDR3_BA2 164 O
SPI_SO/SIO1 129 I/OPD
DDR12_BA1/DDR3_A9 165 O
SPI_CLK 130 OPD
DDR12_A1/DDR3_A13/ 166 I/O
DVDDH 131 P CPU_SLEEP
MVDDH 132 P DDR12_A12/DDR3_A2/ 167 I/O
DDR12_D4/DDR3_D6 133 I/O DRAM_INI_EN
DDR12_D3/DDR3_D2 134 I/O DDR3_RST# 168 O
DDR12_D1/DDR3_D4 135 I/O DDR12_A9/DDR3_A7/ 169 I/O
MEM_TYPE[1]
DDR12_D6/DDR3_D0 136 I/O
DDR12_A7/DDR3_A5/ 170 I/O
DDR12_DM/DDR3_DQS 137 I/O MEM_TYPE[0]
DDR3_DQS# 138 I/O DDR12_A5/DDR3_A0/ 171 I/O
DVDDL 139 P CLK_M_EE[1]
DDR12_CLK#/DDR3_CLK# 140 O DDR12_A3/DDR3_A3/ 172 I/O
DDR12_CLK/DDR3_CLK 141 O CLK_M_EE[0]
DDR12_A10/DDR3_BA0/ 173 I/O
DDR12_DQS/DDR3_DM 142 I/O
EN_DECRYPT
VREF 143 P
DDR2_BA2/DDR3_CS# 174 O
DDR12_D7/DDR3_D3 144 I/O
DDR12_BA0/DDR3_ODT 175 O
DDR12_D0/DDR3_D1 145 I/O
DDR3_ZQ# 176 -
DDR12_D2/DDR3_D7 146 I/O
MVDDH 177 P
DDR12_D5/DDR3_D5 147 I/O
DVDDL 178 P
DDR2_ODT/DDR3_CKE 148 O
VX 179 A
DDR12_CS#/DDR3_BA1 149 O
CKOUT0 180 AO
DDR12_A0/DDR3_A12/ 150 I/O
SVDDL 181 AP
DIS_EEE
S0TXP 182 AO
DDR12_A2/DDR3_A4/ 151 I/O
PWRBLINK[0] S0TXN 183 AO
DDR12_A4/DDR3_A6/ 152 I/O S0RXP 184 AI
PWRBLINK[1] S0RXN 185 AI
DDR12_A6/DDR3_A8/ 153 I/O SVDDH 186 AP
SEL_XTAL_CLK
S1TXN 187 AO
DDR12_A8/DDR3_A1/ 154 I/O
SDS_PDOWN_EN S1TXP 188 AO
DDR3_A14/SPI_ADDR_SEL 155 I/O S1RXN 189 AI
S1RXP 190 AI

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Name Pin No. Type Name Pin No. Type
SVDDL 191 AP P1MDIAN 205 AI/O
DVDDL 192 P P1MDIBP 206 AI/O
AVDDH 193 AP P1MDIBN 207 AI/O
P0MDIAP 194 AI/O AVDDL 208 AP
P0MDIAN 195 AI/O P1MDICP 209 AI/O
P0MDIBP 196 AI/O P1MDICN 210 AI/O
P0MDIBN 197 AI/O P1MDIDP 211 AI/O
AVDDL 198 AP P1MDIDN 212 AI/O
P0MDICP 199 AI/O PLLVDDL 213 AP
P0MDICN 200 AI/O ATESTCK0 214 AO
P0MDIDP 201 AI/O P2MDIAP 215 AI/O
P0MDIDN 202 AI/O P2MDIAN 216 AI/O
AVDDH 203 AP DGND EPAD G
P1MDIAP 204 AI/O

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6.5. Pin Descriptions (RTL8382M-VB)

6.5.1. 1000M Ethernet PHY MDI Interface Pins
Table 16. 1000M Ethernet PHY MDI Interface Pins
Pin Name Pin No. Type Description
P0MDIAP 194 AI/O Port 0 Media Dependent Interface A~D.
P0MDIAN 195 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P0MDIBP 196 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P0MDIBN 197 AI/O MDIAP/N and MDIBP/N.
P0MDICP 199 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P0MDICN 200 AI/O
P0MDIDP 201 AI/O
P0MDIDN 202 AI/O
P1MDIAP 204 AI/O Port 1 Media Dependent Interface A~D.
P1MDIAN 205 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P1MDIBP 206 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P1MDIBN 207 AI/O MDIAP/N and MDIBP/N.
P1MDICP 209 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P1MDICN 210 AI/O
P1MDIDP 211 AI/O
P1MDIDN 212 AI/O
P2MDIAP 215 AI/O Port 2 Media Dependent Interface A~D.
P2MDIAN 216 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P2MDIBP 1 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P2MDIBN 2 AI/O MDIAP/N and MDIBP/N.
P2MDICP 4 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P2MDICN 5 AI/O
P2MDIDP 6 AI/O
P2MDIDN 7 AI/O
P3MDIAP 9 AI/O Port 3 Media Dependent Interface A~D.
P3MDIAN 10 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P3MDIBP 11 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P3MDIBN 12 AI/O MDIAP/N and MDIBP/N.
P3MDICP 15 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P3MDICN 16 AI/O
P3MDIDP 17 AI/O
P3MDIDN 18 AI/O

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Pin Name Pin No. Type Description
P4MDIAP 37 AI/O Port 4 Media Dependent Interface A~D.
P4MDIAN 38 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P4MDIBP 39 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P4MDIBN 40 AI/O MDIAP/N and MDIBP/N.
P4MDICP 43 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P4MDICN 44 AI/O
P4MDIDP 45 AI/O
P4MDIDN 46 AI/O
P5MDIAP 48 AI/O Port 5 Media Dependent Interface A~D.
P5MDIAN 49 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P5MDIBP 50 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P5MDIBN 51 AI/O MDIAP/N and MDIBP/N.
P5MDICP 53 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P5MDICN 54 AI/O
P5MDIDP 55 AI/O
P5MDIDN 56 AI/O
P6MDIAP 59 AI/O Port 6 Media Dependent Interface A~D.
P6MDIAN 60 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P6MDIBP 61 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P6MDIBN 62 AI/O MDIAP/N and MDIBP/N.
P6MDICP 64 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P6MDICN 65 AI/O
P6MDIDP 66 AI/O
P6MDIDN 67 AI/O
P7MDIAP 69 AI/O Port 7 Media Dependent Interface A~D.
P7MDIAN 70 AI/O For 1000Base-T operation, differential data from the media is transmitted and
received on all four pairs. For 100Base-Tx and 10Base-T operation, only
P7MDIBP 71 AI/O MDIAP/N and MDIBP/N are used. Auto MDIX can reverse the pairs
P7MDIBN 72 AI/O MDIAP/N and MDIBP/N.
P7MDICP 74 AI/O
Each of the differential pairs has an internal 100 ohm termination resistor.
P7MDICN 75 AI/O
P7MDIDP 76 AI/O
P7MDIDN 77 AI/O

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6.5.2. SGMII Interface Pins

Table 17. SGMII Interface Pins
Pin Name Pin No. Type Description
S4RXP 96 AI SGMII Interface Receive Data Differential Input Pair.
S4RXN 97 AI
S4TXP 94 AO SGMII Interface Transmit Data Differential Output Pair.
S4TXN 95 AO
S5RXP 102 AI SGMII Interface Receive Data Differential Input Pair.
S5RXN 101 AI
S5TXP 100 AO SGMII Interface Transmit Data Differential Output Pair.
S5TXN 99 AO

6.5.3. QSGMII Interface Pins

Table 18. QSGMII Interface Pins
Pin Name Pin No. Type Description
S0RXP 184 AI QSGMII Interface Receive Data Differential Input Pair.
S0RXN 185 AI
S0TXP 182 AO QSGMII Interface Transmit Data Differential Output Pair.
S0TXN 183 AO
S1RXP 190 AI QSGMII Interface Receive Data Differential Input Pair.
S1RXN 189 AI
S1TXP 188 AO QSGMII Interface Transmit Data Differential Output Pair.
S1TXN 187 AO
S2RXP 84 AI QSGMII Interface Receive Data Differential Input Pair.
S2RXN 85 AI
S2TXP 82 AO QSGMII Interface Transmit Data Differential Output Pair.
S2TXN 83 AO
S3RXP 90 AI QSGMII Interface Receive Data Differential Input Pair.
S3RXN 89 AI
S3TXP 88 AO QSGMII Interface Transmit Data Differential Output Pair.
S3TXN 87 AO
S4RXP 96 AI QSGMII Interface Receive Data Differential Input Pair.
S4RXN 97 AI
S4TXP 94 AO QSGMII Interface Transmit Data Differential Output Pair.
S4TXN 95 AO

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6.5.4. 1000Base-X/100Base-FX Interface Pins

Table 19. 1000Base-X/100Base-FX Interface Pins
Pin Name Pin No. Type Description
S4RXP 96 AI 1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
S4RXN 97 AI
S4TXP 94 AO 1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
S4TXN 95 AO
S5RXP 102 AI 1000Base-X/100Base-FX Interface Receive Data Differential Input Pair.
S5RXN 101 AI
S5TXP 100 AO 1000Base-X/100Base-FX Interface Transmit Data Differential Output Pair.
S5TXN 99 AO

6.5.5. DDR1/2 SDRAM Interface Pins

Table 20. DDR1/2 SDRAM Interface Pins
Pin Name Pin No. Type Drive (mA) Description
DDR12_D[7:0] 144, 136, 147, 133, I/O 8 DDR SDRAM Data Bus.
134, 146, 135, 145
DDR12_A[13:0] 156, 167, 157, 173, I/O 8 DDR SDRAM Address Select.
169, 154, 170, 153,
171, 152, 172, 151,
166, 150
DDR2_BA[2] 174 O 8 DDR SDRAM Bank Address Select.
DDR12_BA[1:0] 165, 175 O 8 DDR SDRAM Bank Address Select.
DDR12_WE# 161 O 8 DDR SDRAM Write Enable.
DDR12_CKE 164 O 8 DDR SDRAM Clock Enable.
DDR12_RAS# 159 O 8 DDR SDRAM Row Address Strobe.
DDR12_CAS# 158 O 8 DDR SDRAM Column Address Strobe.
DDR12_CS#0 149 O 8 DDR SDRAM Chip Select 0.
DDR2_ODT 148 O 8 DDR SDRAM On-Die Termination.
DDR12_DQS 142 I/O 8 DDR SDRAM Data Strobe.
DDR12_CLK 141 O 8 DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.
DDR12_CLK# 140 O 8 DDR SDRAM Clock.
CLK and CLK# are differential clock outputs.

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6.5.6. DDR3 SDRAM Interface Pins

Table 21. DDR3 SDRAM Interface Pins
Pin Name Pin No. Type Drive (mA) Description
DDR3_D[7:0] 146, 133, 147, 135, I/O 8 DDR SDRAM Data Bus.
144, 134, 145, 136
DDR3_A[14] 155 O 8 DDR SDRAM Address Select.
DDR3_A[13:10] 166, 150,156, 157 I/O 8 DDR SDRAM Address Select.
DDR3_A[9] 165 O 8 DDR SDRAM Address Select.
DDR3_A[8:0] 153, 169, 152, 170, I/O 8 DDR SDRAM Address Select.
151, 172, 167, 154,
171
DDR3_DQS# 138 I/O 8 DDR SDRAM Data Strobe.
DDR3_DQS 137 I/O 8 DDR SDRAM Data Strobe.
DDR3_CLK# 140 O 8 DDR SDRAM Clock.
DDR3_CLK 141 O 8 DDR SDRAM Clock.
DDR3_DM 142 I/O 8 DDR SDRAM Data Mask.
DDR3_CKE 148 O 8 DDR SDRAM Clock Enable.
DDR3_BA[2:1] 164, 149 O 8 DDR SDRAM Bank Address Select.
DDR3_BA[0] 173 I/O 8 DDR SDRAM Bank Address Select.
DDR3_RAS# 158 O 8 DDR SDRAM Row Address Strobe.
DDR3_CAS# 159 O 8 DDR SDRAM Column Address Strobe.
DDR3_WE# 161 O 8 DDR SDRAM Write Enable.
DDR3_RST# 168 O 8 DDR SDRAM Reset.
DDR3_CS# 174 O 8 DDR SDRAM Chip Select.
DDR3_ODT 175 O 8 DDR SDRAM On-Die Termination.
DDR3_ZQ# 176 - 8 DDR SDRAM External Reference Ball for Output
Drive Calibration.
This ball is tied to an external 240 Ohm resistor, which
is tied to GND.

6.5.7. Master Mode SPI Flash Interface Pins

Table 22. Master Mode SPI Flash Interface Pins
Pin Name Pin No. Type Drive (mA) Description
SPI_CLK 130 OPD 12 Serial Clock Output Pin.
SPI_SO/SIO1 129 I/OPD 12 In Serial Mode: This is a flash chip output pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is MSB first.
SPI_SI/SIO0 128 I/OPD 12 In Serial Mode: This is a flash chip input pin
In Dual Mode: This is a flash chip bi-directional pin
Note: This is LSB first.
SPI_CS#0 127 O 12 Chip Select Output Pin.
Slave Transmit Enable and active low.

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6.5.8. UART Interface Pins

Table 23. UART Interface Pins
Pin Name Pin No. Type Drive (mA) Description
UART0_RX 125 IPD 4 UART0 Interface Receive Data.
UART0_TX 124 I/OPD 4 UART0 Interface Transmit Data.
UART1_RX 116 IPU 4 UART1 Interface Receive Data.
UART1_TX 117 I/OPD 4 UART1 Interface Transmit Data.

6.5.9. LED Interface Pins

Table 24. LED Interface Pins
Pin Name Pin No. Type Drive (mA) Description
LED_CLK 122 OPU 12 (1) In Serial LED Mode
Reference output clock for serial LED interface and Data is
latched on the rising of LEDCK.
(2) In SMI-like LED Mode
Reference output clock for I2C-like interface.
LED_DAT 123 I/OPU 12 (1) In Serial LED Mode
Serial bit stream of link status information.
(2) In I2C-like LED Mode
The data written to the LED IC.

6.5.10. GPIO Interface Pins

Table 25. GPIO Interface Pins
Pin Name Pin No. Type Drive (mA) Description
This pin default set as system LED.
GPIO0 113 I/OPD 4 Can be configured as General Purpose
Input/Output Pin.
GPIO[3:1] 110, 111, 112 I/OPD 4 General Purpose Input/Output Pins.
GPO10 30 I/OPD 4 General Purpose Output Pins.
GPIO11 31 I/OPD 4 General Purpose Input/Output Pins.
GPIO[14:12] 32,28,29 I/OPU 4 General Purpose Input/Output Pins.

6.5.11. EJTAG Interface Pins

Table 26. EJTAG Interface Pins
Pin Name Pin No. Type Drive (mA) Description
JTAG_TMS 29 I/OPU 4 JTAG Test Mode Select.
JTAG_TCK 28 I/OPU 4 JTAG Test Clock Input.
JTAG_TRST# 32 I/OPU 4 JTAG Test Reset.
JTAG_TDI 31 I/OPD 4 JTAG Test Data Input.
JTAG_TDO 30 I/OPD 4 JTAG Test Data Output.

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6.5.12. Configuration Strapping Pins

Table 27. Configuration Strapping Pins
Pin Name Pin No. Default Description
EEPROMTYPE 30 0b0 Select EEPROM Address Byte Size.
0b0: 1-byte 0b1: 2-byte
DIS_PHYAUTO_UP 117 0b0 Disable ASIC Auto Power Up PHY.
0b0: Enable ASIC auto power up PHY
0b1: Disable ASIC auto power up PHY
REG_IF_SEL 124 0b0 Select Switch Core Register Access Interface.
0b0: I2C 0b1: SPI slave
DIS_EEE 150 0b0 Disable 1000M EEE and 100M EEE Function.
0b0: Enable 0b1: Disable
PWRBLINK[1:0] 152, 151 0b00 Select LED Power On Blinking Timer.
0b00: Disable 0b01: 800ms
0b10: 1.6s 0b11: 3.2s
SEL_XTAL_CLK 153 0b0 Select XTAL Input is 25M or 125M.
0b0: 25M 0b1:125M
Note: This option is only for sync Ethernet.
SDS_PDOWN_EN 154 0b0 Enable SerDes Power Down Mode.
0b0: SerDes4/5 operate in normal mode
0b1: SerDes4/5 operate in power down mode
SPI_ADDR_SEL 155 0b0 Select Address Mode for SPI Flash.
0b0: 3-byte address
0b1: 4-byte address
LED_MODE[1:0] 156, 157 0b0 Select LED Mode.
0b00: Serial LED mode 0b01: Scan Single mode
0b10: Scan Bicolor mode 0b11: Disable LED
CPU_SLEEP 166 0b0 Enable CPU Function.
0b0: CPU is always under reset state
0b1: CPU is enabled
DRAM_INI_EN 167 0b0 Enable DRAM Initialization Procedure.
0b0: Enable DRAM Initialization procedure
0b1: Bypass DRAM Initialization procedure
MEM_TYPE[1:0] 169, 170 0b00 Select Memory Type for SOC.
0b00: Select SPI flash + DDR-3 0b01: Select SPI flash + DDR-2
0b10: Select SPI flash + DDR-1 0b11: Select EEPROM

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Pin Name Pin No. Default Description
CLK_M_EE[1:0] 171, 172 0b00 When MEM_TYPE Select is SPI Flash:
This Strapping Pin Selects the Initial Clock for The Memory Controller.
For DDR2:
0b00: Reserved for test; 0b01: Reserved for test;
0b10: 100MHz 0b11: Reserved for test;
For DDR3:
0b00: Reserved for test; 0b01: Reserved for test;
0b10: 125MHz 0b11: Reserved for test;
Note: The initial value for this strapping pin must be set as recommended
in the reference design guide.

When MEM_TYPE Select is EEPROM:

CLK_M_EE[0] is used to select SOC EEPROM address byte size.
0b0: 1-byte address
0b1: 2-byte address
EN_DECRYPT 173 0b0 Enable or Disable Decrypt for Flash.
0b0: Disable decrypt
0b1: Enable decrypt

6.5.13. Miscellaneous Interface Pins

Table 28. Miscellaneous Interface Pins
Pin Name Pin No. Type Drive (mA) Description
MDC 120 OPU 12 MII Management Interface Clock Pin.
MDIO 121 I/OPU 12 MII Management Interface Data Pin.
SSPI_CLK/I2C_CLK 119 I/OPU 4 SPI Serial Clock Input (Slave Mode).
I2C Interface Clock Input (Slave Mode).
I2C Interface Clock Output (Master Mode).
SSPI_SI/I2C_DAT 118 I/OPU 4 SPI Serial Data Input (Slave Mode).
I2C Interface Bi-Directional data (Slave Mode).
SSPI_SO 117 I/OPD 4 SPI Serial Data Output (Slave Mode).
SSPI_CS# 116 IUP 4 SPI Serial Chip Select (Slave Mode).
RESET# 114 AI - System Pin Reset Input (Low Active).
To complete the reset function, this pin must be asserted
for at least 10ms. It must be pulled up for normal
operation.
XI 106 AI - 25MHz Crystal Clock Input and Feedback Pin.
XO 105 AO - 25MHz Crystal Clock Output Pin.
MDIREF 21 AO - MDI Bias Resistor.
Adjust the reference current for all PHYs. This pin must
connect to AGND via a 2.49k ohm resistor.
RTT1 23 AI/O - Reserved for Internal Use (Must be Left Floating).
RTT2 24 AI/O - Reserved for Internal Use (Must be Left Floating).
VX 179 A - Low Voltage Power Control Resistor.
CKOUT0 180 AO 8 25MHz Clock Output.
CKOUT2 80 AO 8 25MHz Clock Output.

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Pin Name Pin No. Type Drive (mA) Description
CKOUT4 92 AO 8 25MHz Clock Output.
ATESTCK[1:0] 58, 214 AO - Reserved for Internal Use (Must be Left Floating).

6.5.14. Power and Ground Pins

Table 29. Power and Ground Pins
Pin Name Pin No. Type Description
AVDDL 3, 13, 22, 42, 52, 63, AP Analog Low Voltage Power.
73, 198, 208
PLLVDDL 57, 213 AP Analog PLL Low Voltage Power.
AVDDH 8, 14, 19, 25, 36, 41, AP Analog High Voltage Power.
47, 68, 78, 193, 203
DVDDL 26, 33, 34, 79, 108, P Digital Low Voltage Power.
109, 126, 139, 160,
178, 192
DVDDH 27, 35, 115, 131 P Digital High Voltage Power.
SVDDL 81, 86, 93, 98, 103, AP SerDes Low Voltage Power.
181, 191
AVDDL_PLL 107 AP PLL Low Voltage Power.
SVDDH 91, 186 AP SerDes High Voltage Power.
AVDDH_PLL 104 AP PLL High Voltage Power.
MVDDH 132, 162, 163,177 P SDRAM High Voltage Power.
VREF 143 P SSTL Reference Voltage (MVDDH/2).
AGND 20 AG Analog Ground.
DGND E-PAD G Digital Ground.

7. Switch Function Description

7.1. Hardware Reset and Software Reset
7.1.1. Hardware Reset
A hardware reset forces the RTL8380M-VB/RTL8382M-VB to start the initial power-on sequence. First
hardware will strap pins to give all default values when the ‘RESET’ signal terminates. Next the complete
SRAM BIST (Built-In Self Test) process is run. Finally the packet buffer descriptors are initialized and
internal registers and external CPU will access them.

7.1.2. Software Reset

The RTL8380M-VB/RTL8382M-VB supports software queue resets, CPU&Memory reset, and Switch
NIC reset. Reset sources are the signals that will trigger the reset command to the chip.
 CPU&Memory Reset: Resets MIPS 4KEc + Memory Controller + Peripheral + NIC
 Switch NIC Reset: Resets the NIC interface between the CPU and Switch

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7.2. Crystal
The RTL8380M-VB/RTL8382M-VB clock input frequency is 25MHz. When using a crystal, connect a
loading capacitor from XI and XO to ground. The maximum Frequency Tolerance is +/-50ppm. Duty
cycle should range from 40%~60%.

7.3. IEEE 802.3az Energy Efficient Ethernet (EEE)

The RTL8380M-VB/RTL8382M-VB supports IEEE 802.3az Energy Efficient Ethernet (EEE) for
1000Base-T, 100Base-TX in full duplex operation. The Energy Efficient Ethernet (EEE) operational
mode combines the IEEE 802.3 Media Access Control (MAC) Sub-layer with a family of Physical Layers
defined to support operation in Low Power Idle (LPI) Mode. When Low Power Idle Mode is enabled,
systems on both sides of the link can disable portions of the functionality and save power during periods
of low link utilization.
The RTL8380M-VB/RTL8382M-VB EEE operational mode supports IEEE 802.3 MAC operation at
1000Mbps/100Mbps. For 1000Mbps/100Mbps operation, the1000Base-T/ 100Base-TX PHY is supported.

7.4. Layer 2 Learning and Forwarding

The RTL8380M-VB/RTL8382M-VB has a 4K-entry VLAN table and provides a 64-entry filtering
database.
The RTL8380M-VB/RTL8382M-VB supports IVL (Individual VLAN Learning) and SVL (Shared
VLAN learning) mode. The mode used depends on the FID (Filtering Identifier) setting.

7.4.1. Forwarding
IP multicast data packets involve multicast group table lookup and forwarding operations. If the table
lookup returns a hit, the data packet is forwarded to all member ports and router ports. If the multicast
address is not stored in the address table (i.e., lookup miss), the packet is broadcast to all ports of the
broadcast domain. The VLAN Frame Forwarding Rules are defined as follows:
 The received broadcast/multicast frame will flood to VLAN member ports only, except for the source
port
 The received unicast frame will be forwarded to its destination port only if the destination port is in
the same VLAN as the source port. If the destination port belongs to a different VLAN, the frame will
be discarded

7.4.2. Learning
The RTL8380M-VB/RTL8382M-VB features a Layer 2 table (8K entries) that uses a 4-way hash
structure to store L2 entries. Each entry can be recorded in three formats, L2 Unicast, L2 Multicast, and
IP Multicast.

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The L2 Unicast hash key is {MAC(48bits), FID/VID(12bits)}; the Multicast hash key is {MAC(48bits),
FID/VID(12bits)}; the IP Multicast hash key is {MAC(48bits), FID/VID(12bits)}, {GIP(32bits),
SIP(32bits)} or {0(16bits)+GIP(32bits), FID/VID(12bits)}.

7.4.3. DA/SA Block

First bit transmitted:
0= Unicast Destination
1= Multicast Destination
Destination Address
Second bit transmitted:
0= Globally Administered
1= Locally Administered

First byte Second byte Third byte Fourth byte Fifth byte Sixth byte

First byte Second byte Third byte Fourth byte Fifth byte Sixth byte

Second bit transmitted:

0= Globally Administered
1= Locally Administered
Source Address
First bit transmitted-Routing Information Indicator (RII)
0=Routing Information Not Present (Not Source Routed)
1=Routing Information Present (Source Routed)

Figure 9. DA/SA Block

While a frame may be sent to either a unicast or a multicast destination, frames are always sent from an
individual station. The first bit of the Destination Address shows unicast or multicast. When used in its
originally intended manner, the first bit of a Source Address should always be 0, indicating an individual
sending station.
The RTL8380M-VB/RTL8382M-VB features DA blocking, SA blocking, or DA and SA blocking
function through the Address Hash Table setting.

7.5. Port Isolation

The RTL8380M-VB/RTL8382M-VB supports the Port Isolation feature. We can control whether the
hosts communicate with each other or not by controlling a register value.
If we set the register to cut the connection between hosts, all packets from a host cannot be transmitted to
another host directly. These packets can only be transmitted by passing through the router. This feature is
called ‘Port Isolation’. In Figure 10, Host A and host B connect to the port0 and port3 of the switch,
respectively, and port7 is a router. If we set the port isolation enable bit of port0 and port3 to 1, all
packets between A and B need to pass through the router (in both directions, A to B and B to A).

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A B C D E F G H
SELECTED
ON-LINE

0 3 7

Uplink port: 7
A B Downlink port: 0, 3
Figure 10. Port Isolation Example

Each port has its own port mask configuration (11 bits in total for the RTL8380M-VB, 29 bits for the
RTL8382M-VB). These bits and the TX port list will be mixed to a list. We call this mixed list the final
TX port list.
Port isolation port mask settings will affect received packets; however, the Mirroring function is not
affected by the port isolation port mask.

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7.6. IEEE 802.3x Flow Control

The RTL8380M-VB/RTL8382M-VB supports IEEE 802.3x full duplex flow control. If one port’s
received frame buffer is over the pause threshold, a pause-on frame is sent to indicate to the link partner
to stop the transmission. When the port’s received frame buffer drops below the pause threshold, it sends
a pause-off frame. The TX pause frame format is shown in Figure 11.

Pause On: 0xFFFF

Start-of-Frame Delimiter Type =0x8808 MAC Control Opcode Pause Off: 0x0000
Pause on=0001

Reserved Frame
Destination
1 byte Preamble Source Address (SA) (Transmitted Check
Address (DA)
as Zero) Sequence

42 bytes
7 bytes 1 byte 6 bytes 6 bytes 2 bytes 2 bytes 2 bytes 4 bytes

Figure 11. TX Pause Frame Format

The flow control mechanism of the RTL8380M-VB/RTL8382M-VB is implemented on the RX side. It

counts the received pages on the RX side in order to determine on which port it should send out Pause
On/Off packets.

Trigger Condition for Pause-Off

Initial state; Flow Non-Congest State Congest State

Control Enabled

Trigger Condition for Pause-On

Figure 12. Flow Control State Machine

When RTL8380M-VB/RTL8382M-VB flow control is enabled, the initial state is ‘Non_Congest’. The
state is monitored continuously. If a pause-on trigger condition occurs, it enters the ‘Congest’ state. When
in the ‘congest’ state, it is also continuously monitored. When a pause-off trigger condition occurs it re-
enters the ‘Non_Congest’ state. Figure 12 shows the flow control state machine.

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7.7. Half Duplex Backpressure

There are two mechanisms for half duplex backpressure (Backpressure is for input buffer overflow).

7.7.1. Collision-Based Backpressure (Jam Mode)

If the input buffer is ready to overflow, this mechanism will force a collision. When the link partner
detects this collision, the transmission is rescheduled.
The Reschedule procedure is:
 When the link partner detects the collision, it waits for a random backoff time. The RTL8380M-
VB/RTL8382M-VB will handle packets that are in the input packet buffer during this time
 RXDV and TXEN will be driven high. The RTL8380M-VB/RTL8382M-VB will send a 12-byte Jam
signal (pattern is preamble (7bytes) + SFD (1byte) + 0xAA (4bytes)). The RTL8380M-
VB/RTL8382M-VB will then drive TXEN low
 When the link partner (which could be another RTL8380M-VB/RTL8382M-VB) receives the Jam
signal, it will feedback a 4-byte signal (pattern is derived from the CRC of all transmitted bytes)
 After the RTL8380M-VB/RTL8382M-VB receives this jamming signal, it drives RXDV low. The link
partner waits for a random backoff time then re-sends the packet. The timing is shown in Figure 13

Congestion State
0b’1: Congested
0b’0: Not Congested Jamming
4 bytes Backoff time
96 bit times
InterframeGap
RXD XX

RXDV
JAM

TXEN 12 bytes

TXD XX

Figure 13. Signal Timing for Collision-Based Backpressure

7.7.2. Carrier-Based Backpressure (I.e., Defer Mode)

If the input buffer is about to overflow, this mechanism will send a fix pattern to defer the other station’s
transmission. The RTL8380M-VB/RTL8382M-VB will continuously send the defer signal until the input
buffer overflow is resolved.

7.8. Layer 2 Multicast and IP Multicast

There are two RTL8380M-VB/RTL8382M-VB IP multicast frame types: IPv4 multicast and IPv6
multicast.

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An IPv4 multicast frame must satisfy two conditions:
 The type must be IPv4
 DMAC should=01-00-5E-XX-XX-XX

An IPv6 multicast frame must satisfy two conditions:

 The type must be IPv6
 DMAC should=0x33-33-XX-XX-XX-XX

The RTL8380M-VB/RTL8382M-VB definition of a L2 multicast packet is that the packet is not an IP

multicast packet, and the I/G bit of the MAC address is 1.
The RTL8380M-VB/RTL8382M-VB supports IGMPv1/2/3. IGMP and MLDv1/2 packets can be trapped
to the CPU to allow software to insert an IP multicast entry into the L2 table.

7.9. IEEE 802.1d/1w/1s (STP/RSTP/MSTP)

There are 64 spanning tree instances for the RTL8380M-VB/RTL8382M-VB. The CPU will create a
different Port State for different spanning tree instances at each port.
The RTL8380M-VB/RTL8382M-VB will assign a VID for a received packet, and will look up the VLAN
table to check for Multiple Spanning Tree Instances (MSTI).
The RTL8380M-VB/RTL8382M-VB will follow the ports MSTI state to complete its corresponding
ingress/egress check. The Spanning Tree and Rapid Spanning Tree port states are shown in Figure 14.

Port State of Spanning Tree Port State of Rapid Spanning Tree

Disable Learning

Listening
Discard

Blocking Learning
Forwarding

Forwarding
Figure 14. Spanning Tree and Rapid Spanning Tree Port States
When using IEEE 802.1D, the RTL8380M-VB/RTL8382M-VB supports four status’ for each port:
Disabled
Except for software forwarding, the port will not transmit/receive packets, and will not perform learning.

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Blocking/Listening
Except for software forwarding, the port will only receive BPDU spanning tree protocol packets, but will
not transmit any packets, and will not perform learning.
Learning
The port will receive any packet, including BPDU spanning tree protocol packets, and will perform
learning, but will only transmit BPDU spanning tree protocol packets.
Forwarding
The port will transmit/receive all packets, and will perform learning.

There are five Spanning Tree port states, and four Rapid Spanning Tree port states. Their mapping
relations are DiscardingBlocking, LearningLearning, and ForwardingForwarding (see Table 30).
Table 30. Spanning Tree and Rapid Spanning Tree Action
Spanning Tree Rapid Spanning Tree
Disable Blocking Listening Learning Forwarding Discard Learning Forwarding
Receive BPDUs No Yes Yes Yes Yes Yes Yes Yes
Transmit BPDUs No No Yes Yes Yes No Yes Yes
Learn Address No No No Yes Yes No Yes Yes
Forward Frame No No No No Yes No No Yes

7.10. IEEE 802.1p and IEEE 802.1Q (VLAN)

The RTL8380M-VB/RTL8382M-VB supports IEEE 802.1Q tag-based, protocol-and-port-based, port-
based, MAC-based, IP-subnet-based, and application-based VLANs. It supports a 4K-entry VLAN table,
supporting C-VID (Customer VLAN ID) and FID (Filtering Identifier) entries. There are 6 fields in the
VLAN table, and their definitions are as below.
 MBR: Determines whether the packets belong to the same VLAN
 UNTAG: Determines whether Egress packets have a VLAN tag
 FID_MSTI: Gets different FIDs (Filtering Identifier) or determines the index of multiple spanning
tree instances from different VLANs
 L2_HKEY_UBCAST: Determines the hash key (VID or FID) for L2 unicast and broadcast traffic
 L2_HKEY_MCAST: Determines the hash key (VID or FID) for L2 multicast and IP multicast traffic
 VLAN_PROFILE: Determines the index of the VLAN profile

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The RTL8380M-VB/RTL8382M-VB supports eight global VLAN profiles. Each VLAN profile has the
following configurations:
 L2_LRN_EN: Enable L2 SA learning
 L2_UNKN_MC_FLD_PMSK: Unknown L2 multicast flooding port mask
 IP4_UNKN_MC_FLD_PMSK: Unknown IPv4 multicast flooding port mask
 IP6_UNKN_MC_FLD_PMSK: Unknown IPv6 multicast flooding port mask
For un-managed switches, there is a register setting to disable tag-based VLANs and force ‘no check’ for
any VLAN settings. If a packet is tagged in, then it is tagged out. If untagged in, then it is untagged out.
 The RTL8380M-VB/RTL8382M-VB supports ingress and egress VLAN filtering functions
 Ingress VLAN filtering: Packets from an input port that is not in the VLAN member set will be
dropped, trapped, or forwarded depending on register configuration
 Egress VLAN filtering: Packets to an output port that is not in the VLAN member set will be dropped,
trapped, or forwarded depending on register configuration

7.11. IEEE 802.1X (Network Access Control)

The RTL8380M-VB/RTL8382M-VB provides a software solution for 802.1X.
When a host connects to a switch, the switch will transfer the host information to an authentication server:
 If authentication is successful, the switch will set the control bit of this port to ‘TRUE’ (i.e., the host
will be allowed the service)
 If authentication is not successful, the switch will deny the host access to the network
The CPU port can be regarded as a special port where transmit and receive packets are unrestricted for
802.1X.
The RTL8380M-VB/RTL8382M-VB supports two types of 802.1X; Port-Based Network Access Control,
and MAC-Based Network Access Control.
 Port-Based Network Access Control: For each port, there is a bit to check whether this port has passed
authentication or not. A direction control register decides whether this port needs pass-through
authentication for both (IN/OUT) directions or only for receive (IN)
 MAC-Based Access Control: Provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. There is a
register that enables/disables each logical port MAC-based network access control function. Another
register controls transmit/receive direction authentication for each port (IN/OUT) or only receive
direction (IN)

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Table 31 illustrates the forwarding of host n.

Table 31. Forwarding of Host n
Authentication of Host n Direction of Whole Chip Fwd Frames to Host n Fwd Frames from Host n
0 (Unauthorized) 0 (BOTH) No No
0 (Unauthorized) 1 (IN) Yes No
1 (Authorized) 0 (BOTH) Yes Yes
1 (Authorized) 1 (IN) Yes Yes

7.12. Reserved Multicast Address Handling

There are some Reserved Multicast Address (RMA) definitions in the IEEE 802.1 standard. The
RTL8380M-VB/RTL8382M-VB includes 01-80-C2-00-00-00 to 01-80-C2-00-00-2F RMA support and
provides user defined RMA settings. For each RMA, the actions include: Table lookup, Drop, Trap to
CPU, and always Flood. The action priority is higher than the results of a L2 Table lookup. Default
actions are shown in Table 32.
Table 32. Reserved Multicast Address Default Actions
Name Address Default
Bridge Group Address 01-80-C2-00-00-00 Forward
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation 01-80-C2-00-00-01 Drop
IEEE Std 802.3ad Slow Protocols-Multicast Address 01-80-C2-00-00-02 Drop
IEEE Std 802.1X PAE Address 01-80-C2-00-00-03 Forward
Reserved for future protocol standards 01-80-C2-00-00-04 to 01-80-C2-00-00-0D, Drop
01-80-C2-00-00-0F
LLDP IEEE Std 802.1AB Link Layer Discovery Protocol 01-80-C2-00-00-0E Forward
Multicast Address
All LANs Bridge Management Group Address 01-80-C2-00-00-10 Drop
GMRP 01-80-C2-00-00-20 Drop
GVRP 01-80-C2-00-00-21 Forward
Reserved for use by Multiple Registration 01-80-C2-00-00-22 to 01-80-C2-00-00-2F Drop
Protocol (MRP) applications

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7.13. Layer 2 Traffic Suppression (Storm Control)

The per-port L2 storm filtering control mechanism suppresses the flow rate of some specific packets. The
RTL8380M-VB/RTL8382M-VB supports five control types: Unknown Unicast Storm, Unicast Storm,
Unknown Multicast Storm, Multicast Storm, and Broadcast Storm. Each port has control registers to
enable or disable the storm filtering function. These five traffic type definitions are:
 Unknown Unicast: If the I/G bit of the packet’s destination address is 0, it is a unicast packet and its
DA look-up in the L2 unicast table failed. I.e., the packet’s destination address is unknown
 Unicast: The unicast storm filtering control includes unknown and known unicast for RTL8380M-
VB/RTL8382M-VB
 Unknown Multicast: If the I/G bit of the packet’s destination address is 1, it is a multicast packet and
its DA look-up in the L2 unicast table failed, i.e., the packet’s destination address is unknown
 Multicast: The multicast storm filtering control includes unknown and known multicast for
RTL8380M-VB/RTL8382M-VB
 Broadcast: DMAC = FF-FF-FF-FF-FF-FF indicates this is a broadcast packet
Unknown Unicast and Unicast use the same traffic counter, and Unknown Multicast and Multicast use the
same traffic counter. The user should set the Unicast and Multicast storm type as unknown or both known
and unknown in the storm filter setting.
The traffic rate for these five types can be set on a per-port basis. The priority sequence of L2 filtering
control is:
1. Input bandwidth control
2. ACL policy
3. Storm-filtering control

7.14. PIE (Packet Inspection Engine)

PIE is a 1.5K-entry search engine that is divided into 12 blocks (block numbers are 0~11). Each block
size is 128-entries. Every entry has 216-bit data, and a 216-bit mask. There is an extra bit to indicate
whether this entry is valid or not. Each block can be disabled for power saving when it is not used. All the
entries are prepared for ingress ACL.

7.14.1. Ingress ACL

The Ingress ACL (Access Control List) perform actions such as packet drop, forwarding, ingress I-VID
Assignment, Ingress O-VID Assignment, filter, log, remarking, meter, mirror etc. When a packet hits one
entry it will execute the corresponding action mapped to this entry. Each PIE memory entry corresponds
to one action entry. The packet can match to multi-actions. When a multi-match occurs (i.e., there are
several ACL entries that match) in one block, it will execute the lowest address entry corresponding
action.

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7.15. Input Bandwidth Control and ACL Traffic Meter

7.15.1. Input Bandwidth Control
The RTL8380M-VB/RTL8382M-VB has input bandwidth control for each port (excluding the CPU port).
The bandwidth setting range is 16Kbps~1Gbps. The granularity is 16Kbps, and each port has a 16-bit
register to control the bandwidth. If the speed of received packets is faster than the bandwidth setting, it
will send a ‘Pause ON’ packet to slow the link partner transmissions when the flow control function is
enabled, and drop packets when the flow control function is disabled. When normal transmissions
become possible and the flow control function is enabled, the switch will send a ‘Pause OFF’ packet.

7.15.2. ACL Traffic Meter

For Ingress ACL entry, there is an index to point to 256 ACL rate-limited entries. The rate limit is flow
controlled via leaky bucket. The rate range is 16Kbps~1Gbps, the granularity is 16Kbps, and each rate-
limited entry has a 16-bit register to control the rate value.

7.16. IEEE 802.3ad Link Aggregation Protocol

To ensure correct frame ordering when changing the hash algorithm, the marker protocol mechanism
must be started. Software will wait for the aggregation port queues to empty, and then send a marker
message to all aggregation ports. After receiving a marker reply packet, software can change the hash
algorithm.
The RTL8380M-VB/RTL8382M-VB supports 802.3ad (Link Aggregation) for 8 groups of link
aggregators with up to 8 ports per-group (based on DMAC/SMAC/SPA/SIP/DIP/SPORT/DPORT). The
CPU port cannot be aggregated to an aggregation port. As the RTL8380M-VB/RTL8382M-VB does not
check CPU port aggregation, software should check this to avoid frame transmit errors.
Frame Distribution
Link aggregation group frames are sent to an aggregation port of the link aggregation group according to
a hash algorithm. There are seven parameters (DMAC, SMAC, SPA, SIP, DIP, SPORT, DPROT). To
prevent assigning the same hash value when hash keys simultaneously change to another value, we
stagger the least significant bit of all hash keys.
Mapping a Physical Port to a Logical Port
No matter how many physical aggregation port members are in a link aggregation group, it is regarded as
one logical port. Each link aggregation has an ID (the lowest number of the physical aggregation port
members is used as its ID). Once the ID is chosen, even if the logical port ID’s corresponding physical
port is link down, the ID and setting of the link aggregation group will not change. However, it will
change when this corresponding port is removed or a lower-numbered port is added.
Hash Algorithm Change
The algorithm will change when the following conditions occur:
 The link aggregation group member port changes to link-down or link-up
 The user/LACP (i.e., Link Aggregation Control Protocol) changes the link aggregation group member
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port or register setting

7.17. IEEE 802.1ad VLAN Stacking

The RTL8380M-VB/RTL8382M-VB supports multi-layered VLANs and can have Outer-VLAN and
Inner-VLAN tagging. Standard 802.1ad takes the S-tag (Service VLAN tag) as the relay VID. The
RTL8380M-VB/RTL8382M-VB uses the Outer-tag as S-tag, and the Inner-tag as C-tag to support
802.1ad applications.
The IEEE 802.1ad frame format is shown in Figure 15.

6 bytes 6 bytes 2 bytes 2 bytes 2 bytes 2 bytes 2 bytes 4 bytes

VLAN VLAN
Protocol Protocol Length / Frame Check
1 byte Destination Address Source Address S- Tag C- Tag Payload
Info Info Type Sequence
0x 88a8 0x8100

PCP DEI VLAN Identifier PCP CFI VLAN Identifier

3 bits 1bit 12 bits 3 bits 1 bit 12 bits

Figure 15. IEEE 802.1ad Frame Format

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7.18. Quality of Service (QoS)

There are 5 types of Priority Assignment for the RTL8380M-VB/RTL8382M-VB:
 Port-based Inner-tag Priority
 Port-based Outer-tag Priority
 Inner-tag-based Priority
 Outer-tag-based Priority
 DSCP-based Priority
These priority assignments will pass through the whole system priority selection table to decide the
packets internal priority. Afterwards the internal priority will point to the adaptive output queue ID table.
Priority Selection Tables
A received packet may be assigned up to five different priorities. These priorities are coordinated into a
final priority according to the priority selection table Figure 16. Each priority assignment has a control
register. The corresponding bit set to 1, sets the priority from high bit to low bit.
Inner-tag-based priority, Outer-tag-based priority, and DSCP-based priority may be NULL.
The priority arbiter should check whether the item is NULL or not. The NULL item priority corresponds
to the lowest priority arbitration value; the bigger the corresponding priority arbitration value, the higher
the priority assignment.
We can take an example to describe the priority order. The order is Inner-tag-based priority assignment >
DSCP-based priority assignment > Outer-tag based priority assignment > Port-based Inner-tag Priority
assignment = Port-based Outer-tag Priority assignment.

Priority weight

Port-based Inne-tag Priority Assignment 1

Port-based Inne-tag Priority Assignment 1

DSCP-based Priority Assignment 6

Inner-tag-based Priority Assignment 7

Outer-tag-based Priority Assignment 5

Figure 16. Priority Selection Table Weight Rules Example

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Internal Priority to Queue ID Table
The RTL8380M-VB/RTL8382M-VB can transfer its internal priority setting (see Figure 17) to the output
queue ID. The RTL8380M-VB/RTL8382M-VB can configure each port’s output queue level (including
the CPU port). Each port has eight output queues.

Descriptor with Priority 7 Output Queue 7

Descriptor with Priority 6 Output Queue 6

Descriptor with Priority 5 Output Queue 5

Weighted Arbitor
Descriptor with Priority 4 Output Queue 4
TX
Descriptor with Priority 3 Output Queue 3

Descriptor with Priority 2 Output Queue 2

Descriptor with Priority 1 Output Queue 1

Descriptor with Priority 0 Output Queue 0

Figure 17. Per-Port Queue Management

7.19. Packet Scheduling (WRR and WFQ)

The Packet Scheduler controls the various traffic classes (i.e., controls the packet sending sequence of the
priority queue). The RTL8380M-VB/RTL8382M-VB scheduling algorithm is divided into Weighted
Fair-Queuing (WFQ) and Weighted Round-Robin (WRR). Note that the Strict Priority queue is the
highest priority of all queues, and overrides WFQ & WRR. A larger strict priority queue ID indicates the
priority is higher.
The Scheduler operates as follows:
 Weighted Fair-Queuing (WFQ): Byte-count
 Weighted Round-Robin (WRR): Packet-count
WFQ and WRR cannot exist at the same time. WFQ or WRR can co-exist with Strict Priority Schedule.
Both WFQ and WRR are round robin, from large queue ID to small.

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7.20. Packet Drop Algorithm (TD)

The RTL8380M-VB/RTL8382M-VB supports Tail Drop (TD).
 Tail Drop (TD): For a drop threshold value, if a packet meets queue overflow conditions before
entering the output queue, the switch will drop this packet

7.21. Egress Packet Remarking

The RTL8380M-VB/RTL8382M-VB Remarking can be divided into Inner-tag remarking, Outer-tag
remarking, and DSCP remarking.
 For Inner-tag remarking, there is an internal priority to inner-tag priority remarking table that is used
to configure the final user inner-tag priority value for per-port egress of a packet
 For Outer-tag remarking, there is an internal priority to outer-tag priority remarking table that is used
to configure the final Outer-tag priority value for per-port egress of a packet
 DSCP remarking also has an internal priority to DSCP priority table for per-port egress of a packet

7.22. Ingress and Egress Port Mirror

The RTL8380M-VB/RTL8382M-VB has four mirror sets (set0~3), and the Mirroring port can monitor
several mirrored ports simultaneously. RX mirror and TX mirror function is supported by setting a source
port mask, destination port mask. The mirror function can be configured across VLANs. The
RTL8380M-VB/RTL8382M-VB supports a mirror filtering function to filter forwarded traffic. Only
mirrored traffic can egress though a mirroring port.
The RTL8380M-VB/RTL8382M-VB provide a flexible flow-based mirror function. In a flow-based
mirror, only specified packets will be mirrored through a configured ACL action and fill a corresponding
traffic mirror table entry.
For flow control, the mirroring port will drop the mirrored packets and send PAUSE frames or
backpressure signals to the mirrored port for normal packets. It will resume mirror function when flow
control is back to normal status. The design limitations for mirroring settings are as below.
 Each mirror entry can only set one mirroring port
 A mirroring port cannot be a member of a trunk group
 The mirroring port is not limited by port isolation for mirrored packets

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7.22.1. Remote Mirror (RSPAN)

The RTL8380M-VB/RTL8382M-VB support Remote Switched Port Analyzer (RSPAN) to analyze a
remote device’s traffic flow. The RTL8380M-VB/RTL8382M-VB defined RSPAN VLAN tag is
illustrated in Figure 18. Users can configure the RSPAN tag’s TPID/VID/Priority/CFI at each port. The
RTL8380M-VB/RTL8382M-VB can parse for the RSPAN tag in RX and add or remove RSPAN tags in
TX.

Layer2
DMAC SMAC PAYLOAD FCS
Header

Layer 2
DMAC SMAC RSPAN Tag PAYLOAD FCS
Header

RSPAN TPID PRIO CFI RSPAN VID

Figure 18. RSPAN Encapsulation

Figure 19 shows an example of an RSPAN application. In Source Switch A, Port0 is configured as a

mirrored port, and Port2 as a mirroring port with setting ‘TX added RSPAN tag’.
In Intermediate Switch B, Port3 and Port5 are added as RSPAN VLAN members. RSPAN mirrored
packets will be forwarded without any modification.
In Destination Switch C, Port7 and Port9 join as RSPAN VLAN members, with Port9 configured to
‘Remove RSPAN tag in TX’. This means packets are mirrored from Source Switch A Port0 to
Destination Switch C Port9 without modification.

6
Intermediate Destination
Source Switch A Switch B Switch C

0 1 2 3 4 5 7 8 9

Port 0: Mirrored (TX or RX or both) port Port 3 and Port 5 : Intermediate RSPAN port ; Port 9 : RSPAN mirroring port; TX
Port 2: RSPAN mirroring port; forwards forwards RSPAN mirrored packets without mirrored RSPAN packet without
mirrored traffic with RSPAN VLAN tag any modification RSPAN VLAN tag

Figure 19. RSPAN Illustration

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7.23. Management Information Base (MIB)

The RTL8380M-VB/RTL8382M-VB MIB (Management Information Base) counters include:
 Ethernet-like MIB (RFC 3635)
 Interface Group MIB (RFC 2863)
 RMON (Remote Network Monitoring) MIB (RFC 2819)
 Bridge MIB (RFC 1493)
 Bridge MIB Extension (RFC 2674)

7.24. NIC and CPU Tag Forwarding

NIC interface: This is used for receiving packets from the CPU, or transmitting packets to the CPU. The
architecture is shown in Figure 20.
When a packet is sent from the switch core to the CPU port, the CPU tag can carry status information.
The CPU tag can be divided into a transmit CPU tag, and a receive CPU tag.
 Transmit CPU Tag: Forces TX port mask. Indicates which ports the packet will NOT be sent to. For
example, if we set port1, port2, and port5 mask bits, then the packet will not be sent to these ports
 Receive CPU Tag: Indicates which RX port the packet came from
If no CPU tag is attached, the normal process will be followed to perform a look-up in the L2 table.

DMA MAC Rx

CPU
NIC Switch
SDRAM NIC Port MAC
Driver Core
MAC

DMA MAC Tx

Figure 20. NIC Architecture

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7.25. Indirect Table Access

The RTL8380M-VB/RTL8382M-VB employs an indirect method to set the control register and the data
register to complete a VLAN/L2 Lookup/ Forwarding/SPT/ACL Table Access:
1. Sets the register to determine which table and which entry is to be accessed
2. Determines the read or write action
3. Hardware executes table access
Read: After the control register setup has been completed by software, hardware access then puts this data
into the data register. Software then reads this data from the data register.
Write: The data is placed in the data register by software and the control register is set. Hardware writes
this data to the table.

7.26. External PHY Register Access

After the RTL8380M-VB/RTL8382M-VB powers on and initializes, it will set the PHY MII register via
MDC/MDIO. The RTL8380M-VB/RTL8382M-VB supports three access control registers to indirectly
access an external PHY via the MDC/MDIO interface.

7.27. Switch Interrupt Indication

The RTL8380M-VB/RTL8382M-VB provides one global interrupt function: switch interrupt. Interrupt
sources are listed below:
 Port Link Change interrupt
 Port SA learning constraint interrupt
 SerDes interrupt

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8. CPU Function Description

8.1. MIPS-4KEc
 MIPS 4KEc CPU Core (Targeted at 500MHz): 5-stage pipeline, MIPS32 instruction set, additional
MIPS16e instruction set support, 2 GPR sets (one shadow set), and vectored/Non-Maskable Interrupts
(NMI) support
 Cache Configuration: I-Cache is 16KB, 4-way set associative, and 16-byte line size. D-Cache is
16KB, 4-way set associative, 16-byte line size, and write-back policy. It also has virtually indexed,
physically tagged, and Prefetch instructions
 MMU Configuration: 4-entry ITLB, 4-entry DTLB, and 32-entry JTLB
 Misc.: Power-down mode, EJTAG support, internal BIST, internal real-time timer interrupts
(Count/Compare registers), and CPU breakpoints

8.2. SPI Flash

The RTL8380M-VB/RTL8382M-VB support 32M-Byte (max) serial I/O, dual I/O SPI Flash.

8.3. SDRAM Interface Configuration

The RTL8380M-VB/RTL8382M-VB support 8-bit data bus DDR1/DDR2/DDR3 SDRAM.

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9. Interface Descriptions
9.1. QSGMII
QSGMII-plus (Quad Serial Gigabit Media Independent Interface) reduces PCB complexity and IC pin
count. This innovative 5Gbps serial interface provides an up to 10 inch MAC to PHY communication
path. QSGMII can carry the full duplex gigabit Ethernet data streams of four ports simultaneously, using
only 4 pins.

MAC PHY
Port0 TX+/- Port0
RX+/-
TX RX
Port1 Port1
QGMII 25MHz QSGMII
Port2 RX+/- TX+/- Port2
RX TX
Port3 Port3

Figure 21. QSGMII Interconnection

9.2. SGMII
SGMII (Serial Gigabit Media Independent Interface) conveys PHY and MAC data with significantly less
pins than required for GMII. It operates in both half and full duplex, and at all port speeds. It includes 4
data signals and 2 CLK signals to convey frame data and link rate information between the PHY and
MAC. The data signals operate at 1.25Gbaud, and the CLK operates at 625MHz. Each of these signals is
carried as a differential pair, thus providing signal integrity while minimizing system noise.

TX +/-

MAC RX +/-
PHY

Figure 22. SGMII Signal

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9.3. DDR1 SDRAM

The RTL8380M-VB/RTL8382M-VB support DDR1 SDRAM with the following features:
 Bus width is 8 bits
 One chip selection
 Supports 4 banks
 Row count range is 4~16K, and column count range is 512~4K
 Supports maximum 128M Bytes DDR1 SDRAM

CKE
CLK
CLK#
WE#
RAS#
CAS#
DDR1 SDRAM
Controller DDR1_BA[1:0]
CS# 1Gbit
DM 128M*8bit
DQS
A[13:0]

D[7:0]

Figure 23. DDR1 SDRAM Configuration

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9.4. DDR2 SDRAM

The RTL8380M-VB/RTL8382M-VB support DDR2 SDRAM with the following features:
 Bus width is 8 bits
 One chip selection
 Supports 4 banks or 8 banks
 Row count range is 4~16K, and column count range is 512~4K
 Supports maximum 128M Bytes DDR2 SDRAM

CKE
CLK
CLK#
WE#
RAS#
CAS#
DDR2 SDRAM
DDR2_BA[2:0]
Controller
CS# 1Gbit
DM 128M*8bit
ODT
DQS
A[13:0]

D[7:0]

Figure 24. DDR2 SDRAM Configuration

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9.5. DDR3 SDRAM

The RTL8380M-VB/RTL8382M-VB support DDR3 SDRAM with the following features:
 Bus width is 8 bits
 One chip selection
 Supports 8 banks
 Supports maximum 256M Bytes DDR3 SDRAM

CKE
CLK
CLK#
WE#
RAS#
CAS#
DDR3 SDRAM
DDR3_BA[2:0]
CS# 2Gbit
Controller RST#
256M*8bit
ODT
DM
DQS#
DQS

A[14:0]

D[7:0]

Figure 25. DDR3 SDRAM Configuration

9.6. SPI Flash Interface

The RTL8380M-VB/RTL8382M-VB support SPI Flash with the following features:
 Supports serial I/O, dual I/O SPI Flash (max)
 Supports both MMIO (Memory Mapped I/O) and PIO (Programmed I/O) mode
 One chip selection
 Supports maximum 32M Bytes SPI Flash in PIO mode and 16M Bytes in MMIO mode

SPF_SCK
SPI_SIO0/SPI_SI
SPI Flash
Controller SPI_SIO1/SPI_SO
256Mbit

SPF_CS#

Figure 26. SPI Flash Configuration

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9.7. UART
The RTL8380M-VB/RTL8382M-VB provides two UARTs, and each contains a 16-byte FIFO buffer.
The baud rate can be up to 1Mbps and a programmable baud rate generator allows division of any input
reference clock by 1 to 65535, and generates an internal 16x clock. The RTL8380M-VB/RTL8382M-VB
provides a fully programmable serial interface.
In addition to the above functions, the RTL8380M-VB/RTL8382M-VB provides fully prioritized
interrupt control and loopback functionality for diagnostic capabilities.
The UART interface pins are shown in the following table.
Table 33. UART Control Interface Pins
Signal Name Type Description
TXD# Output Transmit Data.
RXD# Input Receive Data.

9.8. EJTAG
EJTAG is inexpensive, and easy to implement. EJTAG utilizes the 5-pin IEEE 1149.1 JTAG (Joint Test
Action Group) specification for off-chip communication. The interface pins are shown in Table 34.
Table 34. EJTAG Interface Pins
Signal Name Type Description
TDI Input Test Data In.
TDO Output Test Data Out.
TCK Output Test Clock.
TMS Output Test Mode Select.
TRST Output (Optional) Test Reset.

TRST EJTAG Circuitry

TMS
TAP Controller
A+ D
TCK Addr . CPU
Direct Memory
Access Data
A+ D
TDO Debug
Registers
TDI Addr.
Instruction, Data, and Processor A+ D
Data System
Control Registers Access
Memory

Address / Data Busses

Figure 27. EJTAG Using a 5-Pin JTAG Interface to Access Data Block

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EJTAG provides a path to access internal debug registers and circuitry that monitor and control the
address and data busses of the processor. The DMA and Processor circuit blocks are used to setup and
monitor the processor’s internal busses and to execute the code from the EJTAG interface.
When an access is detected, the EJTAG circuitry makes the transaction address available in the EJTAG
Address Register, and the appropriate data available in the EJTAG Data Register. It takes about 200 TCK
periods to access 32-bit address and data registers in this fashion, so with a 40MHz TCK frequency, the
access time is in the range of 5µs.

9.9. I2C Slave Interface

The RTL8380M-VB/RTL8382M-VB supports an I2C slave interface (Slave mode) for an external CPU
to access the internal register.
The interface has two I/O pins (i.e., SDA and SCL). SDA is the access data signal, and SCL is the clock
signal (typical clock is 1~2MHz). The read/write data sequence is shown below.

2 ADDRESS BYTES
1 CONTROL BYTE 1 CONTROL BYTE 4 DATA BYTES N
S W S O
T R A A A T R A A A A S
A I A E Data Data Data Data A T
R A6 A5 A4 A3 A2 A1 A0 T C Addr [7:0] C Addr [15:8] C R 1 0 1 0 A2 A1 A0 C C C C C O
A [7:0] [15:8] [23:16] [31:24]
T E K K K T D K K K K K P
MSB to LSB MSB to LSB

DUMMY WRITE

2 ADDRESS BYTES
1 CONTROL BYTE 4 DATA BYTES
S W
T R A A A A A A A S
A I Data Data Data Data T
R A6 A5 A4 A3 A2 A1 A0 T C Addr [7:0] C Addr [15:8] C C C C C O
[7:0] [15:8] [23:16] [31:24]
T E K K K K K K K P
MSB to LSB MSB to LSB

Figure 28. I2C Slave Interface Access Data Sequence

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9.10. SPI Slave Interface

The RTL8380M-VB/RTL8382M-VB supports SPI slave interface (Slave mode) for an external CPU to
access the internal register. The interface has four I/O pins (SI, SO, SCK, and CS#). The instruction sets
are as shown in the following table.
Table 35. SPI Slave Interface
Instruction Name Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8
(Code)
Write Data 02h A23~A16 A15~A8 A7~A0 D31~D24 D23~D16 D15~D8 D7~D0
Read Data 03h A23~A16 A15~A8 A7~A0 D31~D24 D23~D16 D15~D8 D7~D0
Note:
A23~A8: Maps to the switch’s 16-bits register address.
A7~A0 in Write Data Instruction: Dummy byte for switch and conforms to standard SPI 24-bits address format.
A7~A0 in Read Data Instruction: Dummy byte waits for the switch to prepare the register data and conforms to standard
SPI 24-bits address format.
D31~D0: 32-bits Register Data.

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9.11. Serial LED

The RTL8380M-VB/RTL8382M-VB supports a serial LED interface to display the link status. The serial
LED interface, LED_CK and LED_DA provide clock and data to enable/disable the external shift
registers. A 74HC164 8-Bit Serial-In, Parallel-Out Shift Register captures the per-port link status and
diagnostic information. In serial shift LED mode, the RTL8380M-VB/RTL8382M-VB supports per-port
one/two/three single-color LED to show the speed, link status, and other information.

VCC
LED_ DATA A P17_LED[2]
QA
3.3V B P17_LED[1]
QB
LED_ CLK CLK
P17_LED[0]
QC

QD P16_LED[2]
74 HC 164 P16_LED[1]
QE
P16_LED[0]
QF
P15_LED[2]
QG
P15_LED[1]
QH

LED_ DATA A QA
3.3V B
QB
LED_ CLK CLK
QC

QD
74 HC 164
QE

QF

QG

QH

LED_ DATA A P1_LED[2]

QA
3.3V B P1_LED[1]
QB
LED_ CLK CLK
P1_LED[0]
QC

QD P0_LED[2]
74 HC 164 P0_LED[1]
QE
P0_LED[0]
QF

QG

QH

Figure 29. Serial LED Connection

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The default LED status for the RTL8380M-VB/RTL8382M-VB is as follows:

LED Number 3-LEDs
LED0 Definition 1000M Link
LED1 Definition 100M Link
LED2 Definition Link/Act

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10. Electrical AC/DC Characteristics

10.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified referenced to GND unless
otherwise specified.
Table 36. Absolute Maximum Ratings
Parameter Min Max Units
Junction Temperature (Tj) - +125 C
Storage Temperature -45 +125 C
DVDDH, AVDDH, SVDDH, AVDDH_PLL Supply Referenced to DGND and
2.97 3.63 V
AGND
DVDDL, AVDDL, SVDDL, AVDDL_PLL, PLLVDDL Supply Referenced to
0.90 1.18 V
DGND and AGND
MVDDH Supply Referenced to DGND (for DDR1) 2.375 2.625 V
MVDDH Supply Referenced to DGND (for DDR2) 1.71 1.89 V
MVDDH Supply Referenced to DGND (for DDR3) 1.425 1.575 V

10.2. Operating Range

Table 37. Recommended Operating Range
Parameter Min Typical Max Units
Ambient Operating Temperature (Ta) 0 - 55 C
DVDDH, AVDDH, SVDDH, AVDDH_PLL
3.135 3.3 3.465 V
Supply Voltage Range
DVDDL, AVDDL, AVDDL_PLL, PLLVDDL
0.95 1.1 1.15 V
Supply Voltage Range
SVDDL Supply Voltage Range 1.05 1.1 1.15 V
MVDDH Supply Voltage Range(for DDR1) 2.375 2.5 2.625 V
MVDDH Supply Voltage Range(for DDR2) 1.71 1.8 1.89 V
MVDDH Supply Voltage Range(for DDR3) 1.425 1.5 1.575 V

10.3. DC Characteristics
Table 38. DC Characteristics (IO Power =3.3V)
Symbol Parameter Min Typical Max Units
VIH TTL Input High Voltage 2.0 - - V
VIL TTL Input Low Voltage - - 0.8 V
VOH Output High Voltage 2.4 - - V
VOL Output Low Voltage - - 0.4 V

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10.4. AC Characteristics
10.4.1. QSGMII Differential Transmitter Characteristics
Table 39. QSGMII Differential Transmitter Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval 199.94 200 200.06 ps 200ps±300ppm
T_X1 Eye Mask - - 0.2 UI -
T_X2 Eye Mask - - 0.4 UI -
T_Y1 Eye Mask 150 - - mV -
T_Y2 Eye Mask - - 650 mV -
VTX-DIFFp-p Output Differential Voltage 600 900 1300 mV -
TTX-EYE Minimum TX Eye Width 0.6 - - UI -
TTX-JITTER Output Jitter - - 0.4 UI -
TTX-RISE Output Rise Time 0.15 - - UI -
TTX-FALL Output Fall Time 0.15 - - UI -
RTX Differential Resistance 80 100 120 ohm -
CTX AC Coupling capacitor 75 100 200 nF -
LTX Transmit Length in PCB - - 10 inch -

TTX-EYE-MIN

T_Y2

T_Y1

Amplitude 0V VTX-DIFFp-p-MIN VTX-DIFFp-p-MAX

-T_Y1

-T_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0

Time UI

Figure 30. QSGMII Differential Transmitter Eye Diagram

10.4.2. QSGMII Differential Receiver Characteristics

Table 40. QSGMII Differential Receiver Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval 199.94 200 200.06 ps 200ps±300ppm
R_X1 Eye Mask - - 0.3 UI -
R_Y1 Eye Mask 100 - - mV -
R_Y2 Eye Mask - - 650 mV -
VRX-DIFFp-p Input Differential Voltage 200 - 1300 mV -
TRX-EYE Minimum RX Eye Width 0.4 - - UI -

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Symbol Parameter Min Typical Max Units Notes
TRX-JITTER Input Jitter Tolerance - - 0.6 UI -
RRX Differential Resistance 80 100 120 ohm -

TRX-EYE-MIN

R_Y2

R_Y1

Amplitude 0V VRX-DIFFp-p-MIN VRX-DIFFp-p-MAX

-R_Y1

-R_Y2

0.0 R_X1 0.5 1-R_X1 1.0

Time UI
Figure 31. QSGMII Differential Receiver Eye Diagram

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10.4.3. SGMII Differential Transmitter Characteristics

Table 41. SGMII Differential Transmitter Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval 799.76 800 800.24 ps 800ps±300ppm
T_X1 Eye Mask - - 0.1875 UI -
T_X2 Eye Mask - - 0.4 UI -
T_Y1 Eye Mask 125 - - mV -
T_Y2 Eye Mask - - 500 mV -
VTX-DIFFp-p Output Differential Voltage 400 700 900 mV
TTX-EYE Minimum TX Eye Width 0.625 - - UI -
TTX-JITTER Output Jitter - - 0.375 UI -
RTX Differential Resistance 80 100 120 ohm -
CTX AC Coupling capacitor 75 100 200 nF -
LTX Transmit Length in PCB - - 10 inch -

TTX-EYE-MIN

T_Y2

T_Y1

Amplitude 0V VTX-DIFFp-p-MIN VTX-DIFFp-p-MAX

-T_Y1

-T_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0

Time UI
Figure 32. SGMII Differential Transmitter Eye Diagram

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10.4.4. SGMII Differential Receiver Characteristics

Table 42. SGMII Differential Receiver Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval 799.76 800 800.24 ps 800ps±300ppm
R_X1 Eye Mask - - 0.3125 UI -
R_Y1 Eye Mask 50 - - mV -
R_Y2 Eye Mask - - 600 mV -
VRX-DIFFp-p Input Differential Voltage 100 - 1200 mV -
TRX-EYE Minimum RX Eye Width 0.375 - - UI -
TRX-JITTER Input Jitter Tolerance - - 0.625 UI -
RRX Differential Resistance 80 100 120 ohm -

TRX-EYE-MIN

R_Y2

R_Y1

Amplitude 0V VRX-DIFFp-p-MIN VRX-DIFFp-p-MAX

-R_Y1

-R_Y2

0.0 R_X1 0.5 1-R_X1 1.0

Time UI
Figure 33. SGMII Differential Receiver Eye Diagram

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10.4.5. 1000Base-X/100Base-FX Differential Transmitter Characteristics

Table 43. 1000Base-X/100Base-FX Differential Transmitter Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval (1000Base-X) 799.76 800 800.24 ps 800ps±300ppm
Unit Interval (100Base-FX) 7.9976 8.0 8.0024 ns 8ns±300ppm
T_X1 Eye Mask - - 0.1875 UI -
T_X2 Eye Mask - - 0.4 UI -
T_Y1 Eye Mask 125 - - mV -
T_Y2 Eye Mask - - 650 mV -
VTX-DIFFp-p Output Differential Voltage 400 800 1300 mV -
TTX-EYE Minimum TX Eye Width 0.625 - - UI -
TTX-JITTER Output Jitter - - 0.375 UI -
RTX Differential Resistance 80 100 120 ohm -
CTX AC Coupling capacitor 75 100 200 nF -
LTX Transmit Length in PCB - - 10 inch -

TTX-EYE-MIN

T_Y2

T_Y1

Amplitude 0V VTX-DIFFp-p-MIN VTX-DIFFp-p-MAX

-T_Y1

-T_Y2

0.0 T_X1 T_X2 1-T_X2 1-T_X1 1.0

Time UI
Figure 34. 1000Base-X/100Base-FX Differential Transmitter Eye Diagram

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10.4.6. 1000Base-X/100Base-FX Differential Receiver Characteristics

Table 44. 1000Base-X/100Base-FX Differential Receiver Characteristics
Symbol Parameter Min Typical Max Units Notes
UI Unit Interval (1000Base-X) 799.76 800 800.24 ps 800ps±300ppm
Unit Interval (100Base-FX) 7.9976 8.0 8.0024 ns 8ns±300ppm
R_X1 Eye Mask - - 0.3125 UI -
R_Y1 Eye Mask 100 - - mV -
R_Y2 Eye Mask - - 1000 mV -
VRX-DIFFp-p Input Differential Voltage 200 - 2000 mV -
TRX-EYE Minimum RX Eye Width 0.375 - - UI -
TRX-JITTER Input Jitter Tolerance - - 0.625 UI -
RRX Differential Resistance 80 100 120 ohm -

TRX-EYE-MIN

R_Y2

R_Y1

Amplitude 0V VRX-DIFFp-p-MIN VRX-DIFFp-p-MAX

-R_Y1

-R_Y2

0.0 R_X1 0.5 1-R_X1 1.0

Time UI
Figure 35. 1000Base-X/100Base-FX Differential Receiver Eye Diagram

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10.4.7. DDR2 Characteristics

Tcyc

CK# CK#

CK CK

DQS Command

DQ, DM tIS tIH

tDS tDH
tDQSQ
tDQSQ

DQS

DQ(last data valid)

DQ

DQ(first data no longer valid)

tQH

Data valid
window

Figure 36. DDR2 Timing Characteristics

Table 45. DDR2 SDRAM Timing Characteristics

Symbol Description Min Typical Max Units
fCK, fCK# Clock Frequency of the CK and CK# - 300 - MHz
Duty Duty Cycle of the CK and CK# 48 50 52 %
tJITper Clock period jitter -110 - 110 ps
tJITcc Cycle-to-cycle jitter -220 - 220 ps
tDS DQ and DM Output Setup Time 450 - - ps
tDH DQ and DM Output Hold Time 450 - - ps
tIS Address and Control Output Setup Time 600 - - ps
tIH Address and Control Output Hold Time 600 - - ps
tDQSQ Input DQS–DQ Skew, DQS to Last DQ Valid - - 300 ps
tQH Input DQ–DQS Hold, DQS to First DQ to Go Non-Valid 0.3 - - CK
Note: Test Condition, fDDR_CK=300MHz.

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10.4.8. DDR3 Characteristics

Tcyc

CK# CK#

CK CK

DQS Command

DQ, DM tIS tIH

tDS tDH
tDQSQ
tDQSQ

DQS

DQ(last data valid)

DQ

DQ(first data no longer valid)

tQH

Data valid
window

Figure 37. DDR3 Timing Characteristics

Table 46. DDR3 SDRAM Timing Characteristics

Symbol Description Min Typical Max Units
fCK, fCK# Clock Frequency of the CK and CK# - 300 - MHz
Duty Duty Cycle of the CK and CK# 47 50 53 %
tJITper Clock period jitter -90 - 90 ps
tJITcc Cycle-to-cycle jitter -165 - 165 ps
tDS DQ and DM Output Setup Time 450 - - ps
tDH DQ and DM Output Hold Time 400 - - ps
tIS Address and Control Output Setup Time 750 - - ps
tIH Address and Control Output Hold Time 550 - - ps
tDQSQ Input DQS–DQ Skew, DQS to Last DQ Valid - - 300 ps
tQH Input DQ–DQS Hold, DQS to First DQ to Go Non-Valid 0.3 - - CK
Note: Test Condition, fDDR_CK=300MHz.

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10.4.9. SPI Interface Characteristics

tSLCH tCHSH
SPI_CS#

SPI_SCK
tsetup:O thold:O tsetup:I thold:I
SPI_SI(output)
MSB

High-Z
SPI_SO(input) Data In

Figure 38. SPI Interface Timing

Table 47. SPI Interface Timing Characteristics

Symbol Description Min Typical Max Units
fSPI_SCK Clock Frequency of the SPI_SCK 49.5 50 50.5 MHz
Duty Duty Cycle of the SPI_SCK 45 50 55 %
tSLCH CS# Active Setup Time 7 8.1 - ns
tCHSH CS# Active Hold Time 8 9.65 - ns
tsetup:O Data Output Setup Time 4 8.3 - ns
thold:O Data Output Hold Time 6 9.65 - ns
tsetup:I Data Input Setup Time 4 - - ns
thold:I Data Input Hold Time 0 - - ns
Note: Test Condition, fSPI_SCK=50MHz.

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10.4.10. SMI (MDC/MDIO) Interface Characteristics

t1 t2 t3

MDC

t4 t5 t6 t7

Data Data
MDIO Write Read

Figure 39. SMI (MDC/MDIO) Timing

Table 48. SMI (MDC/MDIO) Timing Characteristics

Symbol Description Min Typ Max Units
t1 MDC Clock Period 380 - - ns
t2 MDC High Time - 190 - ns
t3 MDC Low Time - 190 - ns
t4 MDIO to MDC Rising Setup Time (Write Data) - 190 - ns
t5 MDIO to MDC Rising Hold Time (Write Data) - 190 - ns
t6 MDIO to MDC Rising Setup Time (Read Data) 40 - - ns
t7 MDIO to MDC rising hold time (Read Data) 2 - - ns

10.4.11. Serial Mode LED

Tcyc

V ih(max)
LED_CK
V ih( min)
tsetup:O thold:O

Vih(max)
LED_DA Data Output
Vih(min)

Figure 40. Serial Mode LED AC Timing Parameters

Table 49. Serial Mode LED AC Timing

Mode and Description Symbol Min Typical Max Units
Input High Voltage Vih 2.0 - - V
Input Low Voltage Vil - - 0.8 V
Serial LED_CK Clock Cycle Tcyc - 600 - ns
LED Duty Cycle of the LED_CK Duty 45 50 55 %
LED_DA to LED_CK Output Setup Time tsetup:O - 314 - ns
LED_DA to LED_CK Output Hold Time thold:O - 285 - ns

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 RTL8380M-VB/RTL8382M-VB
Datasheet

11. Package Information

11.1. LQFP216-E-PAD (24*24mm)

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 RTL8380M-VB/RTL8382M-VB
Datasheet

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 RTL8380M-VB/RTL8382M-VB
Datasheet

12. Ordering Information

Table 50. Ordering Information
Part Number Package Status
RTL8380M-VB-CG LQFP 216-Pin E-PAD (24*24mm) ‘Green’ Package (Managed) MP
RTL8382M-VB-CG LQFP 216-Pin E-PAD (24*24mm) ‘Green’ Package (Managed) MP
Note: See page 10 (RTL8380M-VB), page 25 (RTL8382M-VB)for package identification.

Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com

10/100/1000M Switch Controllers 94 Track ID: Rev. 1.2