Am 3517

AM3517, AM3505
www.ti.com SPRS550C OCTOBER 2009 REVISED MARCH 2011
AM3517/05 Sitara ARM Microprocessors

Check for Samples: AM3517, AM3505
1 AM3517/05 Sitara ARM Microprocessor

1.1
12345678
Features
5K-Byte Transmit/Receive Buffer (McBSP2) SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations 128-Channel Transmit/Receive Mode Direct Interface to I2S and PCM Device and TDM Buses HDQ/1-Wire Interface 4 UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes) 3 Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers 12 32-bit General Purpose Timers 1 32-bit Watchdog Timer 1 32-bit 32-kHz Sync Timer Up to 186 General-Purpose I/O (GPIO) Pins Display subsystem Parallel Digital Output Up to 24-Bit RGB Supports Up to 2 LCD Panels Support for Remote Frame Buffer Interface (RFBI) LCD Panels Two 10-bit Digital-to-Analog Converters (DACs) Supporting Composite NTSC/PAL Video Luma/Chroma Separate Video (S-Video) Rotation 90, 180, and 270 degrees Resize Images From 1/4x to 8x Color Space Converter 8-bit Alpha Blending Video Processing Front End (VPFE) 16-bit Video Input Port RAW Data Interface 75-MHz Maximum Pixel Clock Supports REC656/CCIR656 Standard
AM3517/05 Sitara ARM Microprocessor: MPU Subsystem 600-MHz Sitara ARM Cortex-A8 Core NEONTM SIMD Coprocessor and Vector floating point (FP) co-processor Memory Interfaces: 166 MHz 16/32- bit mDDR/DDR2 Interface with 1 GByte total addressable space Up to 83 MHz General Purpose Memory Interface supporting 16-bit Wide Multiplexed Address/Data bus 64 K-Byte SRAM 3 Removable Media Interfaces [MMC/SD/SDIO] IO Voltage: mDDR/DDR2 IOs: 1.8V Other IOs: 1.8V and 3.3V Core Voltage: 1.2V Commercial and ExtendedTemperature Grade (operating restrictions apply) 16-bit Video Input Port capable of capturing HD video HD resolution Display Subsystem Serial Communication High-End CAN Controller 10/100 Mbit Ethernet MAC USB OTG subsystem with standard DP/DM interface [HS/FS/LS] Multiport USB Host Subsystem [HS/FS/LS] 12-pin ULPI or 6/4/3-pin Serial Interface Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports Five Multichannel Buffered Serial Ports 512-Byte Transmit/Receive Buffer (McBSP1/3/4/5)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. POWERVR SGX is a trademark of Imagination Technologies Ltd. Sitara is a trademark of Texas Instruments. Cortex is a trademark of ARM Limited. NEON, Jazelle are registered trademarks of ARM Limited. ARM is a registered trademark of ARM Physical IP, Inc.. Android is a trademark of Google Inc.. All other trademarks are the property of their respective owners.
Copyright 20092011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
AM3517, AM3505
SPRS550C OCTOBER 2009 REVISED MARCH 2011 www.ti.com
Supports YCbCr422 Format (8-bit or 16-bit With Discrete Horizontal and Vertical Sync Signals) Generates Optical Black Clamping Signals Built-in Digital Clamping and Black Level Compensation 10-bit to 8-bit A-law Compression Hardware Supports up to 16K Pixels (Image Size) in Horizontal and Vertical Directions System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority) Comprehensive Power, Reset and Clock Management ARM CortexTM-A8 Memory Architecture ARMv7 Architecture In-Order, Dual-Issue, Superscalar Microprocessor Core ARM NEON Multimedia Architecture Over 2x Performance of ARMv6 SIMD Supports Both Integer and Floating Point SIMD Jazelle RCT Execution Environment Architecture Dynamic Branch Prediction with Branch Target Address Cache, Global history buffer and 8 entry return stack Embedded Trace Macrocell [ETM] support for Non_invasive Debug 16K-Byte instruction Cache (4-Way setassociative) 16K-Byte Data Cache (4-Way Set-Associative) 256K-Byte L2 Cache POWERVR SGX Graphics Accelerator Tile Based Architecture Delivering up to 10 MPoly/sec Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 Fine Grained Task Switching, Load Balancing, and Power Management Programmable, High-Quality Image Anti-Aliasing Endianess
ARM Instructions - Little Endian ARM Data Configurable SDRC Memory Controller 16/32-bit Memory Controller With 1G-Byte Total Address Space Double Data Rate (DDR2) SDRAM, mobile Double Data Rate (mDDR)SDRAM SDRAM Memory Scheduler (SMS) and Rotation Engine General Purpose Memory Controller (GPMC) 16-bit Wide Multiplexed Address/Data Bus Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.) Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space) Test Interfaces IEEE-1149.1 (JTAG) Boundary-Scan Compatible Embedded Trace Macro Interface (ETM) 65-nm CMOS technology Packages: 491-pin BGA (17x17, 0.65mm pitch) [ZCN suffix] with via channel array technology 484-pin PBGA (23x23, 1mm pitch) [ZER suffix] Applications: Single Board Computers Industrial and Home Automation Digital Signage Point of Service Portable Media Player Portable Industrial Transportation Navigation Smart White Goods Digital TV Digital Video Camera Gaming
AM3517/05 Sitara ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
1.2
Description
AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN, EMAC, and USB OTG PHY that are well suited for industrial apllications. The processor can support other applications, including: Single Board Computers Home and Industrial automation Human Machine Interface The device supports high-level operating systems (OSs), such as: Linux Windows CE Android The following subsystems are part of the device: Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor POWERVR SGX Graphics Accelerator (AM3517 Device only) Subsystem for 3D graphics acceleration to support display and gaming effects Display subsystem with several features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out. High performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme. AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package. This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05 Sitara ARM Microprocessor .
AM3517, AM3505
1.3
Functional Block Diagram

Figure 1-1 shows Microprocessor the functional . block diagram of the AM3517/05 Sitara ARM
LCD Panel MPU Subsystem ARM CortexA8TM Core 16K/16K L1$ Parallel
CVBS or S-Video
USB transceivers / device ports [3]
Analog DAC
L2$ 256K 64 HECC EMAC Async 64 64 64
POWERVR TM SGX Graphics Accelerator (AM3517 only)

32 32
32 Channel System DMA
Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV QCIF Support 32 VPFE
HS/FS/ LS USB Host
USB PHY USB OTG Controller
32
32
32
L3 Interconnect Network-Hierarchial, Performance, and Power Driven 32 64 SMS: SDRAM Memory Scheduler/ Rotation EMIF Controller DDR PHY 32 32 32 L4 Interconnect GPMC: General Purpose Memory Controller
64K On-Chip RAM
132K On-Chip BOOT ROM
Peripherals: 4xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 186xGPIO, 3xHigh-Speed MMC/SDIO, HDQ/1 Wire, 12xGPTimers, 1xWDT, 32K Sync Timer
System Controls PRCM
External Peripherals Interfaces
External DDR2/ mDDR
NAND/NOR/ FLASH, SRAM
Emulation Debug: ETM, JTAG

SPRS550-006
Figure 1-1. AM3517/05 Functional Block Diagram
AM3517, AM3505
1.4
ZCN and ZER Package Differences

Table 1-1 shows the ZER and ZCN package differences on the device. Table 1-1. ZCN and ZER Package Differences
FEATURE Pin Assignments Video Interfaces ZCN PACKAGE For ZCN package pin assignments, see Terminal Description TV Out available ZER PACKAGE For ZER package pin assignments, see Terminal Description TV Out not available
AM3517, AM3505
............ 1 1.1 Features .............................................. 1 1.2 Description ........................................... 3 1.3 Functional Block Diagram ............................ 4 1.4 ZCN and ZER Package Differences ................. 5 Revision History .............................................. 7 2 TERMINAL DESCRIPTION ............................. 8 2.1 Pin Assignments ..................................... 8 2.2 Ball Characteristics ................................. 17 2.3 Multiplexing Characteristics ........................ 51 2.4 Signal Description .................................. 57 3 ELECTRICAL CHARACTERISTICS ................. 80 3.1 Absolute Maximum Ratings ........................ 80 3.2 Recommended Operating Conditions .............. 82 3.3 DC Electrical Characteristics ....................... 84 3.4 Core Voltage Decoupling ........................... 86 3.5 Power-up and Power-down ......................... 88 4 CLOCK SPECIFICATIONS ........................... 91 4.1 Oscillator ............................................ 93 4.2 Input Clock Specifications .......................... 93 4.3 Output Clock Specifications ........................ 95
1 AM3517/05 Sitara ARM Microprocessor
4.4
VIDEO DAC SPECIFICATIONS

5.1 5.2 5.3 5.4
................................ 97 .................... 100 Interface Description .............................. 101

DPLL Specifications Electrical Specifications Over Recommended Operating Conditions .............................. 102 Analog Supply (vdda_dac) Noise Requirements ..................................................... 104 External Component Value Choice
...............
105
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ................................. 106
............................ ..................... 6.3 Timing Parameters ................................ 6.4 External Memory Interfaces ....................... 6.5 Video Interfaces ................................... 6.6 Serial Communications Interfaces ................ 6.7 Removable Media Interfaces ...................... 6.8 Test Interfaces .................................... PACKAGE CHARACTERISTICS ................... 7.1 Package Thermal Resistance ..................... 7.2 Device Support .................................... 7.3 Community Resources ............................ 7.4 Mechanical Data ..................................
6.1 6.2 Timing Test Conditions Interface Clock Specifications
106 106 107 108 150 155 196 210
214
214 214 215 216
Contents Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history table highlights the technical changes made from the previous to the current revision.
SEE ADDITIONS/MODIFICATIONS/DELETIONS Terminal Description Updated/Changed the following: Table 2-1 Ball Characteristics (ZCN Pkg.) Added note Changed IO Cell entries for balls F24, F25, G24, G25, and E25 Table 2-18 Ball Characteristics (ZER Pkg.) Added note Table 2-18 Serial Communication Interfaces - UARTs Signals Description Added ZER balls Table 2-20 Removable Media Interfaces - MMC/SDIO Signals Description Added ZCN and ZER balls to MMC3/SDIO3 section Table 2-23 Test Interfaces - HWDBG Signals Description Changed ZCN ball numbers for signal hw_dbg4 Table 2-26 System and Miscellaneous Signals Description Added ZER balls Electrical Characteristics Updated/Changed the following: Table 3-2 Estimated Power Consumption at Ball Level Changed max current for VDD_CORE Table 3-4 DC Electrical Characteristics Added IOH value to VOHand IOL value to VOL Updated/Changed the following: Table 6-38 McBSP Timing Conditions Added table note Table 6-130 MMC/SD/SDIO Timing Requirements High-Speed MMC Mode Moved all time entries from max to min column
Timing Requirements and Switching Characteristics
Contents Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
2 TERMINAL DESCRIPTION
2.1 2.1.1 Pin Assignments Pin Map (Top View)
The following illustrations show the top views of the 484-pin [ZER] and 491-pin [ZCN] package pin assignments in four quadrants (A, B, C, and D). Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins must be left unconnected.
TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com
25 24 23 22 21 20 19 18
SPRS550C OCTOBER 2009 REVISED MARCH 2011

17 16 15 14
AE
VSS
DSS_ACBIAS
DSS_PCLK
ETK_D15
ETK_D12
ETK_D8
ETK_D5
ETK_CTL
MCSPI2_ CS1
MCSPI1_ CS3
MCSPI1_ CS2
MCSPI1_ CLK
AE
AD
DSS_DATA1
DSS_DATA0
DSS_VSYNC
DSS_HSYNC
ETK_D13
ETK_D9
ETK_D6
ETK_D0
ETK_CLK
MCSPI2_ CLK
MCSPI1_ SIMO
MCSPI1_ CS1
AD
AC
DSS_DATA4
DSS_DATA3
DSS_DATA2
ETK_D14
ETK_D10
ETK_D1
MCSPI2_ SIMO
MCSPI1_ SOMI
AC
AB
DSS_DATA6
DSS_DATA5
ETK_D11
ETK_D7
ETK_D2
MCSPI2_ SOMI
MCSPI1_CS0
AB
AA
DSS_DATA9
DSS_DATA8
DSS_DATA7
UART1_TX
ETK_D3
MCSPI2_ CS0
VDDS_ DPLL_MPU _USBHOST
AA
DSS_DATA13 DSS_DATA12 DSS_DATA11 DSS_DATA10
UART1_CTS
UART1_RTS
ETK_D4
VDDSHV
VDDSHV
DSS_DATA18 DSS_DATA17 DSS_DATA16 DSS_DATA15 DSS_DATA14
UART1_RX
VDDS
VDDSHV
VDDSHV
DSS_DATA20
DSS_DATA19
VSS
VSS
VDD_CORE
VDD_CORE
VSS
JTAG_TCK
JTAG_NTRST
DSS_ DATA23
DSS_ DATA22
DSS_ DATA21
VDDS
VDDSHV
VSS
VSS
VDD_CORE
VDD_CORE
VSS
JTAG_EMU0
JTAG_TDO
JTAG_TDI
JTAG_TMS _TMSC
JTAG_RTCK
VDDSHV
VDDSHV
VDD_CORE
VDD_CORE
VSS
MCBSP1_ CLKR
JTAG_ EMU1
VDD_CORE
VDD_CORE
VSS
VSS
VSS
MCBSP_ CLKS
MCBSP1_ FSX
MCBSP1_ DR
MCBSP1_ DX
MCBSP1_ FSR
VDDSHV
VDDSHV
VSS
VSS
VSS
VSS
VSS
SYS_ CLKOUT1
MCBSP1_ CLKX
VSS
NC
NC
VDDS_DPLL_ PER_CORE
VDDSHV
VSS
VSS
VSS
SYS_ CLKOUT2
SYS_ CLKREQ
VDD_CORE
VSS
VSS
VSS
VSS
25
24
23
22
21
20
19
18
17
16
15
14
Figure 2-1. ZCN Pin Map [Quadrant A]
AM3517, AM3505
13 12 11 10 9 8 7 6 5 4 3 2 1
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AE
MMC2_ DAT7
MMC2_ DAT3
MMC2_ CMD
MMC1_ DAT7
MMC1_ DAT2
RMII_50MHZ _CLK
RMII_TXD1
RMII_MDIO _DATA
CCDC_ DATA4
CCDC_ DATA1
CCDC_ WEN
CCDC_ HD
VSS
AE
AD
MMC2_ DAT6
MMC2_ DAT2
MMC2_CLK
MMC1_ DAT6
MMC1_ DAT1
RMII_TXEN
RMII_TXD0
RMII_MDIO _CLK
CCDC_ DATA3
CCDC_ DATA0
CCDC_ VD
CCDC_ PCLK
CCDC_ FIELD
AD
AC
MMC2_ DAT5
MMC2_ DAT1
MMC1_ DAT5
MMC1_ DAT0
RMII_RXER
CCDC_ DATA7
CCDC_ DATA2
SYS_ BOOT8
SYS_ BOOT7
SYS_ BOOT6
AC
AB
MMC2_ DAT4
MMC2_ DAT0
MMC1_ DAT4
MMC1_ CMD
RMII_CRS_ DV
CCDC_ DATA6
SYS_ BOOT5
SYS_ BOOT4
AB
AA
VDDS_SRAM CAP_VDD_ _MPU SRAM_MPU
MMC1_ DAT3
MMC1_CLK
RMII_RXD1
SYS_ BOOT3
SYS_ BOOT2
SYS_ BOOT1
AA
VDDSHV
VDDSHV
VDDSHV
VDDS
RMII_RXD0
CCDC_ DATA5
SYS_ BOOT0
SYS _NRES WARM
SYS _NRES PWRON
SYS_NIRQ
VDDSHV
VDDSHV
VDDSHV
VDDSHV
VDDSHV
I2C3_SDA
I2C3_SCL
I2C2_SDA
I2C2_SCL
VSS
VSS
VDD_CORE VDD_CORE
VSS
VSS
VDDSHV
VDDSHV
I2C1_SDA
I2C1_SCL
HECC1_ RXD
HECC1_ TXD
RESERVED
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VSS
RESERVED
GPMC_ WAIT3
VSS
VSS
VDD_CORE
VDD_CORE
VDDSHV
VDDSHV
GPMC_ WAIT2
GPMC_ WAIT1
GPMC_ WAIT0
GPMC_ NWP
GPMC_ NBE1
VSS
VSS
VSS
VSS
VDD_CORE
VDD_CORE
VDDSHV
VDDSHV
VDDS
GPMC_NBE0 _CLE
GPMC_ NWE
GPMC_ NOE
GPMC_NADV _ALE
VSS
VSS
VSS
VSS
VSS
VSS
UART3_TX _IRTX
UART3_RX _IRRX
VSS
VSS
VSS
VSS
VDDSHV
VDDSHV
GPMC_ NCS6
GPMC_ NCS7
UART3_RTS UART3_CTS GPMC_CLK _SD _RCTX
VSS
VSS
VSS
VSS
VSS
VSS
VDDSHV
VDDSHV
VDDSHV
GPMC_ NCS2
GPMC_ NCS3
GPMC_ NCS4
GPMC_ NCS5
13
12
11
10
Figure 2-2. ZCN Pin Map [Quadrant B]
10
AM3517, AM3505
25
24
23
22
21
20
19
18
17
16
15
14
HDQ_ SIO
NC
NC
NC
NC
VDDSOSC
VDDSHV
VDD_CORE
VSS
VSS
VSS
VSS
SYS_ XTALIN
SYS_32K
NC
NC
TV_ OUT1
TV_VFB1
VDDSHV
VDD_CORE
VDD_CORE
VSS
VSSOSC
VSS
VSS
VDD_CORE
VDD_CORE
VSS
SYS_ XTALOUT
TV_ OUT2
TV_VFB2
VSSA_DAC
VDDA_DAC
TV_VREF
NC
VDDSHV
VDDSHV
VDDS
VDD_CORE
VSS
USB0_ID
USB0_ VBUS
VDDA1P8V _USBPHY
VSS
VSS
VDDS
VDDS
VDDS
USB0_DP
USB0_DM
VDDA3P3V _USBPHY
CAP_ VDDA1P2LDO _USBPHY
UART2_CTS
UART2_RTS
NC
VDDS
VREFSSTL
USB0_ DRVVBUS
UART2 _TX
UART2_RX
SDRC_D4
VDDS_SRAM CAP_VDD_ _CORE_BG SRAM_CORE
SDRC_NCAS
MCBSP2_ FSX
MCBSP2_ DX
SDRC_D2
SDRC_D5
SDRC_D9
SDRC_D11
SDRC_CKE0
MCBSP2_ CLKX
MCBSP3_ DR
MCBSP3_ FSX
SDRC_DM0
SDRC_D3
SDRC_D6
SDRC_D10
SDRC_D12
SDRC_NRAS
MCBSP2_DR MCBSP3_DX
MCBSP4_ CLKX
MCBSP4_ DX
SDRC_ D0
SDRC_ DQS0P
SDRC_ D7
SDRC_ D8
SDRC_ DQS1P
SDRC_ D13
SDRC_ DM1
SDRC_ NWE
VSS
MCBSP3_ CLKX
MCBSP4_ DR
MCBSP4_ FSX
SDRC_ D1
SDRC_ DQS0N
SDRC_ STRBEN0
SDRC_ STRBEN _DLY0
SDRC_ DQS1N
SDRC_ D14
SDRC_ D15
SDRC_ NCS1
25
24
23
22
21
20
19
18
17
16
15
14
Figure 2-3. ZCN Pin Map [Quadrant C]
11
AM3517, AM3505
13
12
11
10
VSS
VSS
VSS
VSS
VDD_CORE VDD_CORE
GPMC_ NCS0
GPMC_ NCS1
VSS
VSS
VDD_CORE VDD_CORE
VDDSHV
VDDSHV
VDDSHV
GPMC_D12
GPMC_D13 GPMC_D14
GPMC_D15
VSS
VSS
VDD_CORE
VDD_CORE
VSS
VSS
VDDSHV
GPMC_D7
GPMC_D8
GPMC_D9
GPMC_D10
GPMC_D11
VSS
VSS
VDD_CORE VDD_CORE
VSS
VDDS
GPMC_D5
GPMC_D6
VDDS
VDDS
VDDS
VDDS
GPMC_A10
GPMC_D0
GPMC_D1
GPMC_D2
GPMC_D3
GPMC_D4
VDDS
VDDS
VDDS
VDDS
GPMC_A4
GPMC_A5
GPMC_A6
GPMC_A7
GPMC_A8
GPMC_A9
SDRC_ NCS0
SDRC_ A4
SDRC_ A9
SDRC_DM2
SDRC_D19
GPMC_A1
GPMC_A2
GPMC_A3
SDRC_BA2
SDRC_A3
SDRC_A8
SDRC_A14
SDRC_D18
SDRC_D21
SCRC_D29
SDRC_DM3
SDRC_BA1
SDRC_A2
SDRC_A7
SDRC_ ODT
SDRC_D20
SDRC_D23
SDRC_D27
SDRC_D28
SDRC_D31
SDRC_ NCLK
DDR_ PADREF
SDRC_A1
SDRC_A6
SDRC_A11
SDRC_ A13
SDRC_ D17
SDRC_ DQS2N
SDRC_D22
SDRC_24
SDRC_D26
SDRC_ DQS3N
SDRC_D30
SDRC_CLK
SDRC_BA0
SDRC_A0
SDRC_A5
SDRC_ A10
SDRC_ A12
SDRC_ D16
SDRC_ DQS2P
SDRC_ STRBEN1
SDRC_ STRBEN _DLY1
SDRC_D25
SDRC_ DQS3P
VSS
13
12
11
10
Figure 2-4. ZCN Pin Map [Quadrant D]
12
AM3517, AM3505
www.ti.com
A B C D E F G H

J K L
22
VSS
DSS_PCLK
UART1_TX
ETK_D8
ETK_D10
ETK_D1
ETK_CLK
MCSPI2_ SOMI
MCSPI2_CLK MCSPI1_CLK
VDDSHV
22
21
VDDSHV
DSS_HSYNC
UART1_RTS
ETK_D9
ETK_D7
ETK_D5
ETK_CTL
MCSPI2_CS0 MCSPI1_CS3
MMC2_DAT3
MMC2_DAT6
21
20
DSS_DATA0
DSS_VSYNC
UART1_RX
ETK_D13
ETK_D11
ETK_D2
ETK_D0
MCSPI2_ SIMO
MCSPI1_CS1 MMC2_DAT0
MMC2_DAT5
20
19
DSS_DATA1 DSS_ACBIAS
UART1_CTS
ETK_D14
ETK_D4
ETK_D6
ETK_D3
MCSPI2_CS1 MCSPI1_CS2 MCSPI1_SIMO MMC2_DAT1
19
18
DSS_DATA2
DSS_DATA3
DSS_DATA5
ETK_D15
ETK_D12
VDDSHV
VSS
VDDSHV
MCSPI1_ SOMI
MCSPI1_CS0
MMC2_DAT4
18
17
DSS_DATA4
DSS_DATA8
DSS_DATA9
DSS_DATA6
VDDSHV
VSS
VDDSHV
VSS
VDDSHV
VDDS_DPLL_ MPU_ USBHOST
VDDS_ SRAM_MPU
17
16
DSS_DATA13
DSS_DATA7
DSS_DATA10 DSS_DATA11
VSS
VDDS
VSS
VSS
VDD_CORE
VSS
VDDS
16
15
VDDSHV
VSS
VDDS
VSS
VSS
VDD_CORE
VSS
15
14
JTAG_TCK
VDDSHV
VSS
VSS
VDD_CORE
VSS
VDD_CORE
14
13
DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0
VSS
VDDSHV
VSS
VSS
VDD_CORE
VSS
13
12
JTAG_TMS_ TMSC
JTAG_TDI
JTAG_RTCK
JTAG_TDO
JTAG_EMU1
VDDSHV
VDDSHV
VSS
VDD_CORE
VSS
VDD_CORE
12
Figure 2-5. ZER Pin Map [Quadrant A]
13
AM3517, AM3505
M N P R T U V W Y AA AB
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22
VSS
MMC1_DAT4 MMC1_CLK RMII_RXER
RMII_TXD0
RMII_ MDIO_CLK
CCDC_ DATA4
CCDC_ DATA0
CCDC_VD
VDDSHV
VSS
22
21
MMC2_CLK MMC1_CMD MMC1_DAT0
RMII_ 50MHZ_CLK
RMII_ CRS_DV
RMII_ MDIO_DATA
CCDC_ DATA2
CCDC_WEN
CCDC_HD CCDC_FIELD
CCDC_ PCLK
21
20
MMC2_CMD MMC1_DAT1 MMC1_DAT3 RMII_TXD1
RMII_RXD1
CCDC_ DATA5
CCDC_ DATA6
CCDC_ DATA1
SYS_BOOT8 SYS_BOOT7 SYS_BOOT1
20
19
MMC2_DAT7 MMC1_DAT5 MMC1_DAT2 RMII_TXEN
RMII_RXD0
CCDC_ DATA7
CCDC_ DATA3
SYS_BOOT6 SYS_BOOT5 SYS_BOOT3 SYS_BOOT0
19
18
MMC2_DAT2 MMC1_DAT6 MMC1_DAT7
VDDSHV
VSS
VDDSHV
SYS_BOOT4 SYS_BOOT2
SYS_NRE SWARM
SYS_NRES PWRON
SYS_NIRQ
18
17
CAP_VDD _SRAM_MPU
VSS
VDDSHV
VSS
VDDSHV
VSS
VDDSHV
I2C3_SDA
I2C2_SCL
I2C1_SCL
I2C1_SDA
17
16
VSS
VDDSHV
VSS
VDDSHV
VSS
VDDSHV
RESERVED
I2C3_SCL
I2C2_SDA
GPMC_ WAIT1
HECC1_RXD
16
15
VDD_CORE
VSS
VDD_CORE
VSS
VDDS
VSS
RESERVED UART3_CTS GPMC_NBE1 GPMC_NWE HECC1_TXD _RCTX
15
14
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
GPMC_ WAIT3
GPMC_NWP
GPMC_ WAIT2
GPMC_ GPMC_NOE NADV_ALE
14
13
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
VSS
GPMC_ WAIT0
UART3_RTS _SD
UART3_TX _IRTX
UART3_RX GPMC_CLK _IRRX
13
12
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
GPMC_NCS3 GPMC_NCS5 GPMC_NCS2 GPMC_NCS6
VSS
12
AA
AB
Figure 2-6. ZER Pin Map [Quadrant B]
14
AM3517, AM3505
11
VSS
MCBSP1 _CLKR
MCBSP1_FSX MCBSP1_FSR MCBSP_CLKS
VDDS_ DPLL_PER _CORE
VSS
VSS
VSS
VDD_CORE
VSS
11
10
SYS_XTALIN
VSSOSC
MCBSP1_DX
NC
SYS_ CLKOUT2
NC
VDDSHV
VSS
VDD_CORE
VSS
VDD_CORE
10
SYS_ XTALOUT
HDQ_SIO
MCBSP1_DR
NC
SYS_ CLKOUT1
NC
VDDSOSC
VSS
VSS
VDD_CORE
VSS
SYS_32K
SYS_CLKREQ
MCBSP1 _CLKX
NC
NC
NC
VDDSHV
VSS
VDD_CORE
VSS
VDD_CORE
USB0_ DRVVBUS
USB0_ID
USB0_VBUS
VDDA1P8V _USBPHY
CAP_VDDA1 P2LDO_ USBPHY
VDDA3P3V _USBPHY
VSS
VSS
NC
VDDS
VSS
USB0_DP
USB0_DM
UART2_RX
UART2_TX
VSS
VSS
NC
VSS
VDDS_SRAM CAP_VDD_ _CORE_BG SRAM_CORE
VDDS
UART2_CTS
UART2_RTS
MCBSP2_DR
MCBSP2 _CLKX
MCBSP2_FSX
VDDS
VSS
VDDS
SDRC_BA2
SDRC_BA1
VREFSSTL
MCBSP3_FSX MCBSP3_DR MCBSP3_DX
MCBSP3 _CLKX
MCBSP2_DX
SDRC_DM0
SDRC_D11
SDRC_D12
SDRC_NCS0
SDRC_NCS1
SDRC_BA0
MCBSP4 _CLKX
MCBSP4_DR
SDRC_D2
SDRC_D1
SDRC_D0
SDRC_D4
SDRC_D9
SDRC_D10
SDRC_D14
SDRC_CKE0
SDRC_NCAS
MCBSP4_DX MCBSP4_FSX
SDRC_D3
SDRC_D5
SDRC_DQS0P
SDRC_ STRBEN0
SDRC_D8
SDRC_DQS1P SDRC_DM1
SDRC_NWE
SDRC_NCLK
VSS
VDDSHV
SDRC_D6
SDRC_D7
SDRC_DQS0N
SDRC_ STRBEN _DLY0

F
SDRC_D13
SDRC_DQS1N SDRC_D15
SDRC_NRAS
SDRC_CLK
Figure 2-7. ZER Pin Map [Quadrant C]
15
AM3517, AM3505
AA
AB
11
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
VSS
GPMC_NCS7
GPMC_ NBE0_CLE GPMC_NCS1 GPMC_NCS4
VDDSHV
11
10
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
GPMC_D14
GPMC_D8 GPMC_NCS0 GPMC_D12
GPMC_D10
10
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
VSS
GPMC_D15
GPMC_D11
GPMC_D13
GPMC_D3
GPMC_D9
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV
VDDSHV
GPMC_D7
GPMC_D4
GPMC_D5
GPMC_D6
VDD_CORE
VSS
VDD_CORE
VSS
VDDS
VSS
VDDSHV
GPMC_D2
GPMC_D1
GPMC_D0
GPMC_A9
VSS
VDDS
VSS
VDDS
VSS
VDDS
VSS
GPMC_A8
GPMC_A10
GPMC_A7
GPMC_A6
SDRC_A2
VDDS
VDDS
VSS
VDDS
VSS
SDRC_D22
GPMC_A1
GPMC_A2
GPMC_A4
GPMC_A5
SDRC_A1
SDRC_A5
SDRC_A9
SDRC_A13
SDRC_DM2
SDRC_D18
SDRC_D19
SDRC_D25
SDRC_D27
SDRC_D30
GPMC_A3
SDRC_A0
SDRC_A3
SDRC_A6
SDRC_A12
SDRC_D16
SDRC_D17
SDRC_D23
SDRC_D24
SDRC_D26
SDRC_D29 SDRC_DM3
DDR_ PADREF
SDRC_A4
SDRC_A7
SDRC_A11
SDRC_A14
SDRC_ DQS2N
SDRC_D21
SDRC_ STRBEN _DLY1
SDRC_ DQS3N
SDRC_D28
SDRC_D31
VSS
VDDS
SDRC_A8
SDRC_A10
SDRC_ ODT
SDRC_ DQS2P
SDRC_ D20
SDRC_ STRBEN1
SDRC_ DQS3P
VDDS
VSS
AA
AB
Figure 2-8. ZER Pin Map [Quadrant D]
16
AM3517, AM3505
2.2
Ball Characteristics
Table 2-1 and Table 2-2describe the terminal characteristics and the signals multiplexed on each pin for the ZCN/ZER packages. The following list describes the table column headers. 1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom. 2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). Note: The Ball Characteristics table does not take into account subsystem pin multiplexing options. Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions. 3. MODE: Multiplexing mode number. (a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin corresponds to the name of the pin. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode. Note: The default mode is the mode which is automatically configured on release of the internal GLOBAL_PWRON reset; also see the RESET REL. MODE column. (b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration. 4. TYPE: Signal direction I = Input O = Output I/O = Input/Output D = Open drain DS = Differential A = Analog Note: In the safe_mode, the buffer is configured in high-impedance. 5. BALL RESET STATE: The state of the terminal at reset (power up). 0: The buffer drives VOL (pulldown/pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor. 1: The buffer drives VOH (pulldown/pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor. Z: High-impedance L: High-impedance with an active pulldown resistor H: High-impedance with an active pullup resistor 6. BALL RESET REL. STATE: The state of the terminal at reset release. 0: The buffer drives VOL (pulldown/pullup resistor not activated) 0(PD): The buffer drives VOL with an active pulldown resistor. 1: The buffer drives VOH (pulldown/pullup resistor not activated) 1(PU): The buffer drives VOH with an active pullup resistor. Z: High-impedance L: High-impedance with an active pulldown resistor H : High-impedance with an active pullup resistor 7. RESET REL. MODE: This mode is automatically configured on release of the internal GLOBAL_PWRON reset. 8. POWER: The voltage supply that powers the terminals I/O buffers. 9. VOLTAGE: Supply voltage for associated pin. 10. HYS: Indicates if the input buffer is with hysteresis. 11. LOAD: Load capacitance of the associated output buffer. 12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
17
AM3517, AM3505
13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration. Table 2-1. Ball Characteristics (ZCN Pkg.)
BALL LOCATION [1] B21 A21 D20 C20 E19 D19 C19 B19 B18 D17 C17 D16 C16 B16 A16 A15 A7 B7 D7 E7 C6 D6 B5 C5 B4 A3 B3 C3 C2 D2 B1 C1 A12 C13 D13 A11 B11 C11 D11 E11 A10 B10 C10 D10 E10 A9 B9 A8 B8 PIN NAME [2] sdrc_d0 sdrc_d1 sdrc_d2 sdrc_d3 sdrc_d4 sdrc_d5 sdrc_d6 sdrc_d7 sdrc_d8 sdrc_d9 sdrc_d10 sdrc_d11 sdrc_d12 sdrc_d13 sdrc_d14 sdrc_d15 sdrc_d16 sdrc_d17 sdrc_d18 sdrc_d19 sdrc_d20 sdrc_d21 sdrc_d22 sdrc_d23 sdrc_d24 sdrc_d25 sdrc_d26 sdrc_d27 sdrc_d28 sdrc_d29 sdrc_d30 sdrc_d31 sdrc_ba0 sdrc_ba1 sdrc_ba2 sdrc_a0 sdrc_a1 sdrc_a2 sdrc_a3 sdrc_a4 sdrc_a5 sdrc_a6 sdrc_a7 sdrc_a8 sdrc_a9 sdrc_a10 sdrc_a11 sdrc_a12 sdrc_a13 MODE [3] TYPE [4] BALL RESET STATE [5] L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VOLTAGE [9] 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V HYS [10] LOAD (pF) [11] 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PULL U/D TYPE [12] PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD IO CELL [13]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O O O O O O O O O O
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
18
AM3517, AM3505
Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL LOCATION [1] D8 E13 A14 A13 B13 D14 PIN NAME [2] sdrc_a14 sdrc_ncs0 sdrc_ncs1 sdrc_clk sdrc_nclk sdrc_cke0 MODE [3] TYPE [4] BALL RESET STATE [5] L L L L L L L O O O O O O O IO IO IO IO IO IO IO IO L L L L L L L L L L L L L L L L L L L L A O IO L PD 7 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDSHV 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V/3.3V Yes 30 PU/ PD LVCMOS No No No No No No No Yes Yes Yes Yes 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] Z Z Z Z Z PD 0 0 0 0 0 7 VDDS VDDS VDDS VDDS VDDS VDDS VOLTAGE [9] 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V HYS [10] LOAD (pF) [11] 8 8 8 8 8 8 PULL U/D TYPE [12] PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD IO CELL [13]
0 0 0 0 0 0
O O O O O O
No No No Yes No Yes
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
sdrc_cke0_s 7 afe C14 E14 B14 C21 B15 E8 D1 B20 B17 A6 A2 A20 A17 B6 B2 C8 A19 A18 A5 A4 B12 E3 sdrc_nras sdrc_ncas sdrc_nwe sdrc_dm0 sdrc_dm1 sdrc_dm2 sdrc_dm3 sdrc_dqs0p sdrc_dqs1p sdrc_dqs2p sdrc_dqs3p sdrc_dqs0n sdrc_dqs1n sdrc_dqs2n sdrc_dqs3n sdrc_odt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
sdrc_strben0 0 sdrc_strben_ 0 dly0 sdrc_strben1 0 sdrc_strben_ 0 dly1 ddr_padref gpmc_a1 gpio_34 safe_mode 0 0 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 O O IO O IO O IO O IO O IO O IO O IO
E2
gpmc_a2 gpio_35 safe_mode
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
E1
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F7
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F6
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F4
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F3
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F2
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F1
gpmc_a9
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
19
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] sys_ ndmareq2 gpio_42 safe_mode G6 gpmc_a10 sys_ ndmareq3 gpio_43 safe_mode G5 G4 G3 G2 G1 H2 H1 J5 J4 gpmc_d0 gpmc_d1 gpmc_d2 gpmc_d3 gpmc_d4 gpmc_d5 gpmc_d6 gpmc_d7 gpmc_d8 gpio_44 J3 gpmc_d9 gpio_45 J2 gpmc_d10 gpio_46 J1 gpmc_d11 gpio_47 K4 gpmc_d12 gpio_48 K3 gpmc_d13 gpio_49 K2 gpmc_d14 gpio_50 K1 gpmc_d15 gpio_51 L2 L1 gpmc_ncs0 gpmc_ncs1 gpio_52 M4 gpmc_ncs2 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
1 4 7 0 1 4 7 0 0 0 0 0 0 0 0 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 0 4 0
I IO
O I IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O IO O IO IO
H H H H H H H H H
PU PU PU PU PU PU PU PU PU
0 0 0 0 0 0 0 0 0
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V Yes Yes Yes Yes Yes Yes Yes Yes
30 30 30 30 30 30 30 30 30
PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
H H
Z Z
0 0
VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V
No Yes
30 30
NA PU/ PD
LVCMOS LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 2 vt gpio_53 safe_mode M3 gpmc_ncs3 sys_ ndmareq0 4 7 0 1
O I IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt10_pwm_ 2 evt gpio_54 safe_mode M2 gpmc_ncs4 sys_ ndmareq1 4 7 0 1
O I IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 3 vt gpio_55 safe_mode 4 7
20
AM3517, AM3505

BALL LOCATION [1] M1 PIN NAME [2] gpmc_ncs5 sys_ ndmareq2 MODE [3] TYPE [4] BALL RESET STATE [5] H BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PU 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
0 1
O I IO IO
Yes
LVCMOS
gpt10_pwm_ 3 evt gpio_56 safe_mode N5 gpmc_ncs6 sys_ ndmareq3 4 7 0 1
O I IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt11_pwm_ 3 evt gpio_57 safe_mode N4 gpmc_ncs7 gpmc_io_dir 4 7 0 1
O O IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt8_pwm_e 3 vt gpio_58 safe_mode N1 gpmc_clk gpio_59 R1 R2 R3 R4 4 7 0 4
O IO O O O O IO O IO
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpmc_nadv_ 0 ale gpmc_noe gpmc_nwe 0 0
L H H L
Z Z Z Z
0 0 0 0
VDDSHV VDDSHV VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
No No No Yes
30 30 30 30
PU/ PD PU/ PD PU/ PD PU/ PD
LVCMOS LVCMOS LVCMOS LVCMOS
gpmc_nbe0_ 0 cle gpio_60 4 0 4 7 0 4 0 0 1 4 7 0 1 4 7 0 1
T1
gpmc_nbe1 gpio_61 safe_mode
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
T2
gpmc_nwp gpio_62
O IO I I O IO
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
T3 T4
gpmc_wait0 gpmc_wait1 uart4_tx gpio_63 safe_mode
H H
PU PU
0 7
VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V
Yes Yes
30 30
PU/ PD PU/ PD
LVCMOS LVCMOS
T5
gpmc_wait2 uart4_rx gpio_64 safe_mode
I I IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
U1
gpmc_wait3 sys_ ndmareq1
I I I IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
uart3_cts_rct 2 x gpio_65 safe_mode AE23 dss_pclk gpio_66 hw_dbg12 safe_mode AD22 dss_hsync gpio_67 hw_dbg13 safe_mode 4 7 0 4 5 7 0 4 5 7
O IO O
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
21
AM3517, AM3505

BALL LOCATION [1] AD23 PIN NAME [2] dss_vsync gpio_68 safe_mode AE24 dss_acbias gpio_69 safe_mode AD24 dss_data0 uart1_cts gpio_70 safe_mode AD25 dss_data1 uart1_rts gpio_71 safe_mode AC23 dss_data2 gpio_72 safe_mode AC24 dss_data3 gpio_73 safe_mode AC25 dss_data4 MODE [3] TYPE [4] BALL RESET STATE [5] H BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PU 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 20 PULL U/D TYPE [12] PU/ PD IO CELL [13]
0 4 7 0 4 7 0 2 4 7 0 2 4 7 0 4 7 0 4 7 0
O IO
Yes
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O I IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O I IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
uart3_rx_ irrx 2 gpio_74 safe_mode AB24 dss_data5 4 7 0
O O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
uart3_tx_ irtx 2 gpio_75 safe_mode AB25 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mode AA23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mode AA24 dss_data8 gpio_78 hw_dbg16 safe_mode AA25 dss_data9 gpio_79 hw_dbg17 safe_mode Y22 dss_data10 gpio_80 safe_mode Y23 dss_data11 gpio_81 safe_mode Y24 dss_data12 gpio_82 safe_mode 4 7 0 2 4 5 7 0 2 4 5 7 0 4 5 7 0 4 5 7 0 4 7 0 4 7 0 4 7
O O IO O
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O I IO O
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
22
AM3517, AM3505

BALL LOCATION [1] Y25 PIN NAME [2] dss_data13 gpio_83 safe_mode W21 dss_data14 gpio_84 safe_mode W22 dss_data15 gpio_85 safe_mode W23 dss_data16 gpio_86 safe_mode W24 dss_data17 gpio_87 safe_mode W25 dss_data18 mcspi3_clk dss_data4 gpio_88 safe_mode V24 dss_data19 mcspi3_ simo dss_data3 gpio_89 safe_mode V25 dss_data20 mcspi3_ somi dss_data2 gpio_90 safe_mode U21 dss_data21 mcspi3_cs0 dss_data1 gpio_91 safe_mode U22 dss_data22 mcspi3_cs1 dss_data0 gpio_92 safe_mode U23 dss_data23 dss_data5 gpio_93 safe_mode H24 K21 K20 H23 H20 AD2 tv_out2 tv_out1 tv_vfb1 tv_vfb2 tv_vref ccdc_pclk gpio_94 hw_dbg0 safe_mode MODE [3] TYPE [4] BALL RESET STATE [5] L BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PD 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 20 PULL U/D TYPE [12] PU/ PD IO CELL [13]
0 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 2 3 4 7 0 2 3 4 7 0 2 3 4 7 0 2 3 4 7 0 2 3 4 7 0 3 4 7 0 0 0 0 0 0 4 5 7
O IO
Yes
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O O O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O O IO
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
O O O O I IO IO O Z Z Z L NA NA NA PD
0 0 0 0 0 7
VDDA_DAC VDDA_DAC VDDA_DAC VDDA_DAC VDDA_DAC VDDSHV
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V/3.3V Yes 15
NA NA NA NA NA PU/ PD
10-bit DAC 10-bit DAC 10-bit DAC 10-bit DAC 10-bit DAC LVCMOS
23
AM3517, AM3505

BALL LOCATION [1] AD1 PIN NAME [2] ccdc_field ccdc_data8 uart4_tx i2c3_scl gpio_95 hw_dbg1 safe_mode AE2 ccdc_ hd uart4_rts gpio_96 safe_mode AD3 ccdc_vd uart4_cts gpio_97 hw_dbg2 safe_mode AE3 ccdc_wen ccdc_data9 uart4_rx gpio_98 hw_dbg3 safe_mode AD4 ccdc_data0 i2c3_sda gpio_99 safe_mode AE4 ccdc_data1 gpio_100 safe_mode AC5 ccdc_data2 gpio_101 hw_dbg4 safe_mode AD5 ccdc_data3 gpio_102 hw_dbg5 safe_mode AE5 ccdc_data4 gpio_103 hw_dbg6 safe_mode Y6 ccdc_data5 gpio_104 hw_dbg7 safe_mode AB6 ccdc_data6 gpio_105 safe_mode AC6 ccdc_data7 gpio_106 safe_mode AE6 MODE [3] TYPE [4] BALL RESET STATE [5] L BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PD 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 15 PULL U/D TYPE [12] PU/ PD IO CELL [13]
0 1 2 3 4 5 7 0 2 4 7 0 2 4 5 7 0 1 2 4 5 7 0 3 4 7 0 4 7 0 4 5 7 0 4 5 7 0 4 5 7 0 4 5 7 0 4 7 0 4 7
IO I O IOD IO O
Yes
LVCMOS
IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/ PD
LVCMOS
IO I IO O
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/ PD
LVCMOS
IO I I IO O
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/PD
LVCMOS
I IOD I
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/PD
LVCMOS
I I
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/PD
LVCMOS
I IO O
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/ PD
LVCMOS
I IO O
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/ PD
LVCMOS
I IO O
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/ PD
LVCMOS
I IO O
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/ PD
LVCMOS
I IO
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/PD
LVCMOS
I IO
PD
VDDSHV
1.8V/3.3V
Yes
15
PU/PD
LVCMOS
rmii_mdio_da 0 ta ccdc_data8 gpio_107 1 4
IO I IO
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/PD
LVCMOS
24
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] safe_mode AD6 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
7 O I IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
rmii_mdio_cl 0 k ccdc_data9 gpio_108 safe_mode 1 4 7 0
Y7
rmii_rxd0
I I IO O
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/ PD
LVCMOS
ccdc_data10 1 gpio_109 hw_dbg8 safe_mode AA7 rmii_rxd1 4 5 7 0
I I IO O
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/ PD
LVCMOS
ccdc_data11 1 gpio_110 hw_dbg9 safe_mode AB7 rmii_crs_dv 4 5 7 0
I I IO
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/ PD
LVCMOS
ccdc_data12 1 gpio_111 safe_mode AC7 rmii_rxer 4 7 0
I I IO O
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/ PD
LVCMOS
ccdc_data13 1 gpio_167 hw_dbg10 safe_mode AD7 rmii_txd0 4 5 7 0
O I IO O
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/ PD
LVCMOS
ccdc_ data14 1 gpio_126 hw_dbg11 safe_mode AE7 rmii_txd1 4 5 7 0
O I I
PU
VDDSHV
1.8V/3.3V
Yes
25
PU/PD
LVCMOS
ccdc_data15 1 gpio_112 safe_mode AD8 rmii_txen gpio_113 safe_mode AE8 4 7 0 4 7
O I
PU
VDDSHV
1.8V/3.3V NA
25
PU/PD
LVCMOS
rmii_50mhz_ 0 clk gpio_114 safe_mode 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 4
I I
PU
VDDSHV
1.8V/3.3V NA
25
PU/ PD
LVCMOS
D25
mcbsp2_fsx gpio_116 safe_mode
IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
C25
mcbsp2_ clkx gpio_117 safe_mode
IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
B25
mcbsp2_dr gpio_118 safe_mode
I IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
D24
mcbsp2_dx gpio_119 safe_mode
IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AA9
mmc1_clk gpio_120
O IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
25
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] safe_mode AB9 mmc1_cmd gpio_121 safe_mode AC9 mmc1_dat0 mcspi2_clk gpio_122 safe_mode AD9 mmc1_dat1 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
7 0 4 7 0 1 4 7 0 IO IO IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS IO IO IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS IO IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mcspi2_simo 1 gpio_123 safe_mode AE9 mmc1_dat2 4 7 0
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mcspi2_somi 1 gpio_124 safe_mode AA10 mmc1_dat3 mcspi2_cs0 gpio_125 safe_mode AB10 mmc1_dat4 gpio_126 safe_mode AC10 mmc1_dat5 gpio_127 safe_mode AD10 mmc1_dat6 gpio_128 safe_mode AE10 mmc1_dat7 gpio_129 safe_mode AD11 mmc2_clk mcspi3_clk uart4_cts gpio_130 safe_mode AE11 4 7 0 1 4 7 0 4 7 0 4 7 0 4 7 0 4 7 0 1 2 4 7
IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO
PD
VDDSHV
1.8V/3.3V
No
30
PU/ PD
LVCMOS
IO IO
PD
VDDSHV
1.8V/3.3V
No
30
PU/ PD
LVCMOS
IO IO
PD
VDDSHV
1.8V/3.3V
No
30
PU/ PD
LVCMOS
IO IO
PD
VDDSHV
1.8V/3.3V
No
30
PU/ PD
LVCMOS
O IO I IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mmc2_ cmd 0 mcspi3_ simo uart4_rts gpio_131 safe_mode 1 2 4 7
IO IO O IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AB12
mmc2_ dat0 0 mcspi3_ somi uart4_tx gpio_132 safe_mode 1 2 4 7
IO IO O IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AC12
mmc2_ dat1 0 uart4_rx gpio_133 safe_mode 2 4 7
IO I IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AD12
mmc2_ dat2 0 mcspi3_cs1 1
IO O
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
26
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] gpio_134 safe_mode AE12 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
4 7
IO
mmc2_ dat3 0 mcspi3_cs0 gpio_135 safe_mode 1 4 7
IO IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AB13
mmc2_ dat4 0 mmc2_dir_da 1 t0 mmc3_dat0 gpio_136 safe_mode 3 4 7
IO O IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AC13
mmc2_ dat5 0 mmc2_dir_da 1 t1 mmc3_dat1 gpio_137 3 4
IO O IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_r 6 xdp safe_mode AD13 7
mmc2_ dat6 0 mmc2_dir_ cmd mmc3_dat2 gpio_138 safe_mode 1 3 4 7
IO O IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AE13
mmc2_ dat7 0 mmc2_ clkin 1 mmc3_dat3 gpio_139 3 4
IO I IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_r 6 xdm safe_mode B24 mcbsp3_dx uart2_cts gpio_140 safe_mode C24 mcbsp3_dr uart2_rts gpio_141 safe_mode A24 mcbsp3_ clkx uart2_tx gpio_142 safe_mode C23 mcbsp3_fsx uart2_rx gpio_143 safe_mode F20 uart2_cts mcbsp3_dx 7 0 1 4 7 0 1 4 7 0 1 4 7 0 1 4 7 0 1
IO I IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I O IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO O IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO I IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I IO IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 2 vt gpio_144 safe_mode F19 uart2_rts 4 7 0
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
27
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] mcbsp3_dr MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
I IO IO
gpt10_pwm_ 2 evt gpio_145 safe_mode E24 uart2_tx mcbsp3_ clkx gpt11_pwm _evt gpio_146 safe_mode E23 uart2_rx mcbsp3_fsx 4 7 0 1 2 4 7 0 1
O IO IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I IO IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt8_pwm_e 2 vt gpio_147 safe_mode AA19 uart1_tx gpio_148 safe_mode Y19 uart1_rts gpio_149 safe_mode Y20 uart1_cts gpio_150 safe_mode W20 uart1_rx 4 7 0 4 7 0 4 7 0 4 7 0
O IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
O IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I I IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mcbsp1_ clkr 2 mcspi4_clk gpio_151 safe_mode B23 mcbsp4_ clkx gpio_152 3 4 7 0 4
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_t 6 xse0 safe_mode A23 mcbsp4_dr gpio_153 7 0 4
I IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_r 6 xrcv safe_mode B22 mcbsp4_dx gpio_154 7 0 4
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_t 6 xdat safe_mode A22 mcbsp4_fsx gpio_155 7 0 4
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_t 6 xen_ n safe_mode R25 7
mcbsp1_ clkr 0 mcspi4_clk gpio_156 safe_mode 1 4 7 0
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
P21
mcbsp1_fsr
IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
28
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] gpio_157 safe_mode P22 mcbsp1_dx mcspi4_ simo mcbsp3_dx gpio_158 safe_mode P23 mcbsp1_dr mcspi4_ somi mcbsp3_dr gpio_159 safe_mode P25 mcbsp_clks gpio_160 uart1_cts safe_mode P24 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mode N24 mcbsp1_ clkx mcbsp3_ clkx gpio_162 safe_mode N2 uart3_cts_ rctx gpio_163 safe_mode N3 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
4 7 0 1 2 4 7 0 1 2 4 7 0 4 5 7 0 1 2 4 7 0 2 4 7 0 4 7
IO
IO IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I IO I IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I IO I
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
uart3_rts_ sd 0 gpio_164 safe_mode 4 7
O IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
P1
uart3_rx_ irrx 0 gpio_165 safe_mode 4 7
I IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
P2
uart3_tx_ irtx 0 gpio_166 safe_mode 4 7 0
O IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
F25
usb0_dp
IO O IO I A A O O IO L PD 7
5.0V
Yes
PU/ PD
USB_PHY
uart3_tx_ irtx 1 F24 usb0_dm 0
5.0V
Yes
PU/ PD
USB_PHY
uart3_rx_ irrx 1 G24 G25 E25 usb0_vbus usb0_id 0 0
VDDA3P3V_ 5.0V USBPHY VDDA3P3V_ 3.3V USBPHY VDDSHV 1.8V/3.3V
Yes Yes 30
PU/ PD PU/ PD
USB_PHY USB_PHY LVCMOS
usb0_drvvbu 0 s uart3_tx_ irtx 2 gpio_125 safe_mode 4 7 0
V2
hecc1_ txd
O I IO
PU
VDDSHV
1.8V/3.3V
Yes
24
PU/ PD
LVCMOS
uart3_rx_ irrx 2 gpio_130 4
29
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] safe_mode V3 hecc1_ rxd MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
7 0 I O IO H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS
uart3_rts_ sd 2 gpio_131 safe_mode V4 V5 W1 i2c1_scl i2c1_ sda i2c2_scl gpio_168 safe_mode W2 i2c2_sda gpio_183 safe_mode W4 i2c3_scl gpio_184 safe_mode W5 i2c3_sda gpio_185 safe_mode L25 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mode AE14 mcspi1_clk mmc2_dat4 gpio_171 safe_mode AD15 mcspi1_ simo mmc2_dat5 gpio_172 safe_mode AC15 mcspi1_ somi mmc2_dat6 gpio_173 safe_mode AB15 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mode AD14 mcspi1_cs1 mmc3_cmd gpio_175 safe_mode AE15 mcspi1_cs2 mmc3_clk gpio_176 safe_mode AE16 mcspi1_cs3 hsusb2_ data2 gpio_177 4 7 0 0 0 4 7 0 4 7 0 4 7 0 4 7 0 1 2 3 4 7 0 1 4 7 0 1 4 7 0 1 4 7 0 1 4 7 0 3 4 7 0 3 4 7 0 3 4
IOD IOD IOD IO
H H H
PU PU PU
0 0 7
VDDSHV VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
Yes Yes Yes
40 40 40
PU/ PD PU/ PD PU/ PD
Open Drain Open Drain Open Drain
IOD IO
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
Open Drain
IOD IO
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
Open Drain
IOD IO
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
Open Drain
IO I O O IO
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
LVCMOS
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
O IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
O O IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
O IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
30
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
mm_fsusb2_t 5 xdat safe_mode AD16 mcspi2_clk hsusb2_ data7 gpio_178 safe_mode AC16 mcspi2_ simo 7 0 3 4 7 0
IO
IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
IO IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 1 vt hsusb2_ data4 gpio_179 safe_mode AB16 mcspi2_ somi 3 4 7 0
IO IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt10_pwm_ 1 evt hsusb2_ data5 gpio_180 safe_mode AA16 mcspi2_cs0 3 4 7 0
IO IO IO IO
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt11_pwm_ 1 evt hsusb2_ data6 gpio_181 safe_mode AE17 mcspi2_cs1 3 4 7 0
O IO IO IO IO
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt8_pwm_e 1 vt hsusb2_ data3 gpio_182 3 4
mm_fsusb2_t 5 xen_ n safe_mode K24 K25 H25 M24 sys_32k sys_xtalin sys_xtalout sys_clkreq gpio_1 Y1 sys_nirq gpio_0 safe_mode Y2 Y3 sys_ nrespwron sys_ nreswarm gpio_30 Y4 sys_boot0 gpio_2 AA1 sys_boot1 gpio_3 AA2 sys_boot2 gpio_4 AA3 sys_boot3 7 0 0 0 0 4 0 4 7 0 0 4 0 4 0 4 0 4 0
I I O IO IO I IO
Z Z Z L
Z Z Z Z
0 0 0 0
VDDSHV VDDSOSC VDDSOSC VDDSHV
1.8V/3.3V 1.8V 1.8V 1.8V/3.3V
Yes NA NA Yes
30
30
PU/ PD
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
I IO IO I IO I IO I IO I
Z L
Z PD
0 0
VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V
Yes Yes
30 30
PU/ PD PU/ PD
LVCMOS LVCMOS Open Drain
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
31
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] gpio_5 AB1 sys_boot4 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
4 0
IO I O IO I O IO I IO I I O IO Z Z H Z Z PD 0 0 0/7 (1) VDDSHV VDDSHV VDDSHV 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V Yes Yes Yes 30 30 30 PU/PD PU/PD PU/ PD LVCMOS LVCMOS LVCMOS Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
mmc2_dir_da 1 t2 gpio_6 AB2 sys_boot5 4 0
mmc2_dir_da 1 t3 gpio_7 AC1 sys_boot6 gpio_8 AC2 AC3 N25 sys_boot7 sys_boot8 sys_clkout1 gpio_10 safe_mode M25 sys_clkout2 gpio_186 safe_mode U24 U25 T21 T22 T23 T24 T25 jtag_ntrst jtag_tck jtag_rtck 4 0 4 0 0 0 4 7 0 4 7 0 0 0
O IO
PD
VDDSHV
1.8V/3.3V
Yes
10
PU/ PD
LVCMOS
I I O IO I O IO IO IO IO O IO O O IO O IO O IO IO O IO IO IO IO IO O IO IO IO
L L L H H L H
PD PD Z PU PU Z PU
0 0 0 0 0 0 0
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
Yes Yes Yes Yes Yes Yes Yes
20 20 20 20 20 20 20
PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
jtag_tms_tms 0 c jtag_tdi jtag_tdo jtag_emu0 gpio_11 0 0 0 4 0 4 0 1 2 3 4 0 2 3 4
R24
jtag_emu1 gpio_31
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
AD17
etk_clk mcbsp5_ clkx mmc3_clk hsusb1_stp gpio_12
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
AE18
etk_ctl mmc3_cmd hsusb1_clk gpio_13
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
mm_fsusb1_r 5 xdp AD18 etk_d0 mcspi3_ simo mmc3_dat4 hsusb1_ data0 gpio_14 0 1 2 3 4
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
mm_fsusb1_r 5 xrcv AC18 etk_d1 mcspi3_ somi hsusb1_ data1 gpio_15 0 1 3 4
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
(1) 32
Mux0 if sys_boot6 is pulled down (clock master). TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
mm_fsusb1_t 5 xse0 AB18 etk_d2 mcspi3_cs0 hsusb1_ data2 gpio_16 0 1 3 4
IO O IO IO IO IO O IO IO IO IO O I IO IO IO O IO IO IO IO O IO IO IO IO O O IO IO IO IO O IO I IO O IO I IO IO O I O IO O IO O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mm_fsusb1_t 5 xdat AA18 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_ data7 gpio_17 Y18 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_ data4 gpio_18 AE19 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_ data5 gpio_19 AD19 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_ data6 gpio_20 AB19 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_ data3 gpio_21 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
mm_fsusb1_t 5 xen_n AE20 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 AD20 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 0 2 3 4 0 2 3 4
mm_fsusb1_r 5 xdm AC20 etk_d10 uart1_rx hsusb2_clk gpio_24 AB20 etk_d11 mcspi3_clk hsusb2_stp 0 2 3 4 0 1 3
33
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] gpio_25 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
IO IO O I IO O I IO IO O IO IO IO O IO IO IO PWR 1.2V L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mm_fsusb2_r 5 xdp AE21 etk_d12 hsusb2_dir gpio_26 AD21 etk_d13 hsusb2_nxt gpio_27 0 3 4 0 3 4
mm_fsusb2_r 5 xdm AC21 etk_d14 hsusb2_ data0 gpio_28 0 3 4
mm_fsusb2_r 5 xrcv AE22 etk_d15 hsusb2_ data1 gpio_29 0 3 4
mm_fsusb2_t 5 xse0 V16, V15, VDD_CORE 0 V11, V10, U16, U15, U11, U10, T18, T17, T9, T8, R18, R17, R9, R8, M18, L18, L9, L8, K18, K17, K9, K8, J16, J15, J11, J10, H15, H11, H10 AA13 E17 VDDS_SRA M_MPU 0
PWR PWR
1.8V 1.8V
VDDS_SRA 0 M_CORE_B G CAP_VDD_S 0 RAM_MPU CAP_VDD_S 0 RAM_CORE VDDS_DPLL 0 _MPU_USB HOST VDDS_DPLL 0 _PER_CORE VDDA_DAC 0
AA12 E16 AA15
PWR PWR PWR
1.2V 1.2V 1.8V
N20 H21 F23 G22 F22
PWR PWR PWR PWR PWR
1.8V 1.8V 3.3V 1.8V 1.2V
VDDA3P3V_ 0 USBPHY VDDA1P8V_ 0 USBPHY CAP_VDDA1 0 P2LDO_USB PHY
34
AM3517, AM3505

BALL LOCATION [1] PIN NAME [2] MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
Y16, Y15, VDDSHV Y13, Y12, Y10, W16, W15, W13, W12,W10, W9, W6, V7, V6, U19, T20, T19, T7, T6, R7, R6, P20, P19, N19, N7, N6, M7, M6, M5, L19, K19, K7, K6, K5, J7, H18, H17 Y9, W18, U20, R5, H16, H8, G17, G16, G14, G13, G11, G10, G8, F16, F13, F11, F10, F8 F14 L20 J25 VDDS
PWR
PWR
1.8V
VREFSSTL VDDSOSC VSSOSC
0 0 O 0
I PWR GND GND 1.8V 1.8V
AE25, AE1, VSS V18, V17, V14, V13, V12, V9, V8, U18, U17, U14, U13, U12, U9, U8, T14, T13, T12, R16, R15, R14, R13, R12, R11, R10, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, N18, N17, N14, N13, N12, N9, N8, M17, M16, M15, M14, M13,M12, M11, M10, M9, M8, L17, L16, L15, L14, L13, L12, L11, L10, K14, K13, K12, J18, J17, J14, J13, J12, J9, J8, H14, H13, H12, H9, A25, A1, N23, G20, G21 H22 VSSA_DAC
GND
L24, L23, NC (2) L22, L21, K23, K22, H19, N22,N21,F17 U2 (3) V1 (3) Reserved Reserved
(2) (3)
"NC" indicates "No Connect". For proper device operation, these pins must be left unconnected. For proper device operation, this pin must be pulled up to VDDSHV via a 10k- resistor.
35
AM3517, AM3505
Table 2-2. Ball Characteristics (ZER Pkg.)

BALL PIN NAME LOCATION [2] [1] E3 D3 C3 C2 F3 D2 C1 D1 G2 G3 H3 G4 H4 G1 J3 J1 T3 U3 U4 V4 V1 V2 V5 V3 W3 W4 Y3 Y4 AA2 AA3 AA4 AB2 L4 K5 J5 M3 M4 M5 N3 N2 N4 P3 P2 P1 P4 R1 R2 R3 R4 T2 J4 K4 L1 L2 sdrc_d0 sdrc_d1 sdrc_d2 sdrc_d3 sdrc_d4 sdrc_d5 sdrc_d6 sdrc_d7 sdrc_d8 sdrc_d9 sdrc_d10 sdrc_d11 sdrc_d12 sdrc_d13 sdrc_d14 sdrc_d15 sdrc_d16 sdrc_d17 sdrc_d18 sdrc_d19 sdrc_d20 sdrc_d21 sdrc_d22 sdrc_d23 sdrc_d24 sdrc_d25 sdrc_d26 sdrc_d27 sdrc_d28 sdrc_d29 sdrc_d30 sdrc_d31 sdrc_ba0 sdrc_ba1 sdrc_ba2 sdrc_a0 sdrc_a1 sdrc_a2 sdrc_a3 sdrc_a4 sdrc_a5 sdrc_a6 sdrc_a7 sdrc_a8 sdrc_a9 sdrc_a10 sdrc_a11 sdrc_a12 sdrc_a13 sdrc_a14 sdrc_ncs0 sdrc_ncs1 sdrc_clk sdrc_nclk MODE [3] TYPE [4] BALL RESET STATE [5] L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VOLTAGE [9] 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V HYS [10] LOAD (pF) [11] 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 PULL U/D TYPE [12] PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD IO CELL [13]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O O O O O O O O O O O O O O O
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No Yes No
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
36
AM3517, AM3505
Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME LOCATION [2] [1] K3 sdrc_cke0 MODE [3] TYPE [4] BALL RESET STATE [5] L BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PD 7 VDDS VOLTAGE [9] 1.8V HYS [10] LOAD (pF) [11] 8 PULL U/D TYPE [12] PU/ PD IO CELL [13]
O I O O O O O O O IO IO IO IO IO IO IO IO
Yes
LVCMOS
sdrc_cke0_s 7 afe K1 L3 K2 F4 J2 T4 AB3 E2 H2 U1 Y1 E1 H1 U2 Y2 T1 F2 F1 W1 W2 W5 sdrc_nras sdrc_ncas sdrc_nwe sdrc_dm0 sdrc_dm1 sdrc_dm2 sdrc_dm3 sdrc_dqs0p sdrc_dqs1p sdrc_dqs2p sdrc_dqs3p sdrc_dqs0n sdrc_dqs1n sdrc_dqs2n sdrc_dqs3n sdrc_odt 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
L L L L L L L L L L L L L L L L L L L L
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z PD
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDSHV
1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V/3.3V
No No No No No No No Yes Yes Yes Yes
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
sdrc_strben0 0 sdrc_strben_ 0 dly0 sdrc_strben1 0 sdrc_strben_ 0 dly1 gpmc_a1 gpio_34 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 1 4 0 1 4 0 0 0 0 0 0 0 0 O IO O IO O IO O IO O IO O IO O IO O IO O I IO O I IO IO IO IO IO IO IO IO IO
Yes
30
Y5
gpmc_a2 gpio_35
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AB4
gpmc_a3 gpio_36
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AA5
gpmc_a4 gpio_37
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AB5
gpmc_a5 gpio_38
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AB6
gpmc_a6 gpio_39
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AA6
gpmc_a7 gpio_40
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
W6
gpmc_a8 gpio_41
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AB7
gpmc_a9 sys_ ndmareq2 gpio_42
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
Y6
gpmc_a10 sys_ ndmareq3 gpio_43
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AA7 Y7 W7 AA9 Y8 AA8 AB8 W8
gpmc_d0 gpmc_d1 gpmc_d2 gpmc_d3 gpmc_d4 gpmc_d5 gpmc_d6 gpmc_d7
H H H H H H H H
PU PU PU PU PU PU PU PU
0 0 0 0 0 0 0 0
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V Yes Yes Yes Yes Yes Yes Yes
30 30 30 30 30 30 30 30
PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
37
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] W10 gpmc_d8 gpio_44 AB9 gpmc_d9 gpio_45 AB10 gpmc_d10 gpio_46 W9 gpmc_d11 gpio_47 AA10 gpmc_d12 gpio_48 Y9 gpmc_d13 gpio_49 V10 gpmc_d14 gpio_50 V9 gpmc_d15 gpio_51 Y10 Y11 gpmc_ncs0 gpmc_ncs1 gpio_52 Y12 gpmc_ncs2 MODE [3] TYPE [4] BALL RESET STATE [5] H BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PU 0 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 0 4 0
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O IO O IO IO O I IO IO O I IO IO O I IO IO O I IO IO O O IO IO O IO O O O
Yes
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
H H
Z Z
0 0
VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V
No Yes
30 30
NA PU/ PD
LVCMOS LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 2 vt gpio_53 V12 gpmc_ncs3 sys_ ndmareq0 4 0 1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt10_pwm_ 2 evt gpio_54 AA11 gpmc_ncs4 sys_ ndmareq1 4 0 1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 3 vt gpio_55 W12 gpmc_ncs5 sys_ ndmareq2 4 0 1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt10_pwm_ 3 evt gpio_56 AA12 gpmc_ncs6 sys_ ndmareq3 4 0 1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt11_pwm_ 3 evt gpio_57 V11 gpmc_ncs7 gpmc_io_dir 4 0 1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt8_pwm_e 3 vt gpio_58 AB13 gpmc_clk gpio_59 AA14 AB14 AA15 4 0 4
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpmc_nadv_ 0 ale gpmc_noe gpmc_nwe 0 0
L H H
Z Z Z
0 0 0
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
No No No
30 30 30
LVCMOS LVCMOS LVCMOS
38
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] W11 MODE [3] TYPE [4] BALL RESET STATE [5] L BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] Z 0 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
gpmc_nbe0_ 0 cle gpio_60 4 0 4 0 4 0 0 1 4 0 1 4 0 1
O IO O IO O IO I I O IO I I IO I I I IO O IO O O IO O O IO O IO O I IO O O IO O IO O IO O I IO O O IO O O IO O O I IO O O IO
Yes
LVCMOS
Y15
gpmc_nbe1 gpio_61
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
W14
gpmc_nwp gpio_62
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
V13 AA16
gpmc_wait0 gpmc_wait1 uart4_tx gpio_63
H H
PU PU
0 7
VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V
Yes Yes
30 30
PU/ PD PU/ PD
LVCMOS LVCMOS
Y14
gpmc_wait2 uart4_rx gpio_64
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
V14
gpmc_wait3 sys_ ndmareq1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
uart3_cts_rct 2 x gpio_65 B22 dss_pclk gpio_66 hw_dbg12 B21 dss_hsync gpio_67 hw_dbg13 B20 dss_vsync gpio_68 B19 dss_acbias gpio_69 A20 dss_data0 uart1_cts gpio_70 A19 dss_data1 uart1_rts gpio_71 A18 dss_data2 gpio_72 B18 dss_data3 gpio_73 A17 dss_data4 4 0 4 5 0 4 5 0 4 0 4 0 2 4 0 2 4 0 4 0 4 0
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
uart3_rx_irrx 2 gpio_74 C18 dss_data5 uart3_tx_irtx gpio_75 D17 dss_data6 uart1_tx gpio_76 hw_dbg14 B16 dss_data7 uart1_rx gpio_77 hw_dbg15 B17 dss_data8 gpio_78 4 0 2 4 0 2 4 5 0 2 4 5 0 4
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
39
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] hw_dbg16 C17 dss_data9 gpio_79 hw_dbg17 C16 dss_data10 gpio_80 D16 dss_data11 gpio_81 D14 dss_data12 gpio_82 A16 dss_data13 gpio_83 D15 dss_data14 gpio_84 B15 dss_data15 gpio_85 A15 dss_data16 gpio_86 A14 dss_data17 gpio_87 C13 dss_data18 mcspi3_clk dss_data4 gpio_88 C15 dss_data19 mcspi3_ simo dss_data3 gpio_89 A13 dss_data20 mcspi3_ somi dss_data2 gpio_90 B13 dss_data21 mcspi3_cs0 dss_data1 gpio_91 C14 dss_data22 mcspi3_cs1 gpio_92 B14 dss_data23 dss_data5 gpio_93 AB21 ccdc_pclk gpio_94 hw_dbg0 AA21 ccdc_field ccdc_data8 uart4_tx i2c3_scl gpio_95 hw_dbg1 Y21 ccdc_ hd uart4_rts MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
5 0 4 5 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 2 3 4 0 2 3 4 0 2 3 4 0 2 3 4 0 2 4 0 3 4 0 4 5 0 1 2 3 4 5 0 2
O O IO O O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O IO O O IO O O IO IO IO O IO I O IO IO O IO O L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS
40
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] gpio_96 Y22 ccdc_vd uart4_cts gpio_97 hw_dbg2 W21 ccdc_wen ccdc_data9 uart4_rx gpio_98 hw_dbg3 W22 ccdc_data0 i2c3_sda gpio_99 W20 ccdc_data1 gpio_100 V21 ccdc_data2 gpio_101 hw_dbg4 V19 ccdc_data3 gpio_102 hw_dbg5 V22 ccdc_data4 gpio_103 hw_dbg6 U20 ccdc_data5 gpio_104 hw_dbg7 V20 ccdc_data6 gpio_105 U19 ccdc_data7 gpio_106 U21 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
4 0 2 4 5 0 1 2 4 5 0 3 4 0 4 0 4 5 0 4 5 0 4 5 0 4 5 0 4 0 4
IO IO I IO O IO I I IO O I IO I I I I IO O I IO O I IO O I IO O I IO I IO IO I IO O I IO I I IO O I I IO O I I IO I I IO O O I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V 8 Yes 8 25 PU/PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS
rmii_mdio_da 0 ta ccdc_data8 gpio_107 1 4
U22
rmii_mdio_clk 0 ccdc_data9 gpio_108 1 4 0
T19
rmii_rxd0
ccdc_data10 1 gpio_109 hw_dbg8 T20 rmii_rxd1 4 5 0
ccdc_data11 1 gpio_110 hw_dbg9 T21 rmii_crs_dv 4 5 0
ccdc_data12 1 gpio_111 R22 rmii_rxer 4 0
ccdc_data13 1 gpio_167 hw_dbg10 T22 rmii_txd0 4 5 0
ccdc_ data14 1
41
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] gpio_126 hw_dbg11 R20 rmii_txd1 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
4 5 0
IO O O I I O I I I IO IO IO IO I IO IO IO O IO IO IO IO IO IO IO IO IO IO IO IO IO O IO IO IO IO IO IO IO IO IO O IO I IO IO IO O IO IO IO O IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V H PU 7 VDDSHV 1.8V/3.3V NA Yes 30 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V NA 25 PU/ PD LVCMOS 25 PU/PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS
ccdc_data15 1 gpio_112 R19 rmii_txen gpio_113 R21 4 0 4
rmii_50mhz_ 0 clk gpio_114 4 0 4
E5
mcbsp2_fsx gpio_116
D5
mcbsp2_ clkx 0 gpio_117 4 0 4 0 4 0 4 0 4 0 1 4 0
C5
mcbsp2_dr gpio_118
E4
mcbsp2_dx gpio_119
P22
mmc1_clk gpio_120
N21
mmc1_cmd gpio_121
P21
mmc1_dat0 mcspi2_clk gpio_122
N20
mmc1_dat1
mcspi2_simo 1 gpio_123 P19 mmc1_dat2 4 0
mcspi2_somi 1 gpio_124 P20 mmc1_dat3 mcspi2_cs0 gpio_125 N22 mmc1_dat4 gpio_126 N19 mmc1_dat5 gpio_127 N18 mmc1_dat6 gpio_128 P18 mmc1_dat7 gpio_129 M21 mmc2_clk mcspi3_clk uart4_cts gpio_130 M20 mmc2_ cmd mcspi3_ simo uart4_rts gpio_131 K20 4 0 1 4 0 4 0 4 0 4 0 4 0 1 2 4 0 1 2 4
mmc2_ dat0 0 mcspi3_ somi uart4_tx gpio_132 1 2 4
42
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] L19 MODE [3] TYPE [4] BALL RESET STATE [5] H BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PU 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
mmc2_ dat1 0 uart4_rx gpio_133 2 4
IO I IO IO O IO IO IO IO IO O IO IO IO O IO IO IO IO O IO IO IO I IO IO IO IO I IO I O IO IO O IO IO I IO I IO IO IO O I IO IO O IO IO
Yes
LVCMOS
M18
mmc2_ dat2 0 mcspi3_cs1 gpio_134 1 4
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
K21
mmc2_ dat3 0 mcspi3_cs0 gpio_135 1 4
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
L18
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
L20
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_r 6 xdp L21 mmc2_ dat6 0 mmc2_dir_c md mmc3_dat2 gpio_138 M19 1 3 4
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mmc2_ dat7 0 mmc2_clkin mmc3_dat3 gpio_139 1 3 4
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb3_r 6 xdm C4 mcbsp3_dx uart2_cts gpio_140 B4 mcbsp3_dr uart2_rts gpio_141 D4 0 1 4 0 1 4
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mcbsp3_ clkx 0 uart2_tx gpio_142 1 4 0 1 4 0 1
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
A4
mcbsp3_fsx uart2_rx gpio_143
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
A5
uart2_cts mcbsp3_dx
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 2 vt gpio_144 B5 uart2_rts mcbsp3_dr 4 0 1
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt10_pwm_ 2 evt gpio_145 D6 uart2_tx 4 0
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mcbsp3_clkx 1 gpt11_pwm _evt 2
43
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] gpio_146 C6 uart2_rx mcbsp3_fsx MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
4 0 1
IO I IO IO IO O IO O IO I IO I I IO IO IO IO IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I IO I IO I IO I IO I IO IO IO IO IO IO IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS
gpt8_pwm_e 2 vt gpio_147 C22 uart1_tx gpio_148 C21 uart1_rts gpio_149 C19 uart1_cts gpio_150 C20 uart1_rx 4 0 4 0 4 0 4 0
mcbsp1_ clkr 2 mcspi4_clk gpio_151 A3 3 4
mcbsp4_ clkx 0 gpio_152 4
mm_fsusb3_t 6 xse0 B3 mcbsp4_dr gpio_153 0 4
mm_fsusb3_r 6 xrcv A2 mcbsp4_dx gpio_154 0 4
mm_fsusb3_t 6 xdat B2 mcbsp4_fsx gpio_155 0 4
mm_fsusb3_t 6 xen_n B11 mcbsp1_ clkr 0 mcspi4_clk gpio_156 D11 mcbsp1_fsr gpio_157 C10 mcbsp1_dx mcspi4_ simo mcbsp3_dx gpio_158 C9 mcbsp1_dr mcspi4_ somi mcbsp3_dr gpio_159 E11 mcbsp_clks gpio_160 uart1_cts C11 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 C8 1 4 0 4 0 1 2 4 0 1 2 4 0 4 5 0 1 2 4
mcbsp1_ clkx 0 mcbsp3_clkx 2 gpio_162 4
44
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] W15 MODE [3] TYPE [4] BALL RESET STATE [5] H BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PU 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
uart3_cts_rct 0 x gpio_163 4
IO IO O IO I IO O IO IO IO A A O O IO O I IO I O IO IOD IOD IOD IO IOD IO IOD IO IOD IO IO I O O IO IO IO IO IO IO IO IO IO IO IO IO IO O IO IO
Yes
LVCMOS
W13
uart3_rts_sd 0 gpio_164 4
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
AA13
uart3_rx_irrx 0 gpio_165 4 0 4 0 0 0 0
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
Y13
uart3_tx_irtx gpio_166
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
A6 B6 C7 B7 A7
usb0_dp usb0_dm usb0_vbus usb0_id
5.0V 5.0V VDDA3P3V_ 3.3V USBPHY VDDA3P3V_ 3.3V USBPHY L PD 7 VDDSHV 1.8V/3.3V
Yes Yes Yes Yes 30
PU/ PD PU/ PD PU/ PD PU/ PD
usb0_drvvbu 0 s uart3_tx_irtx gpio_125 2 4 0
AB15
hecc1_ txd
PU
VDDSHV
1.8V/3.3V
Yes
24
PU/ PD
LVCMOS
uart3_rx_irrx 2 gpio_130 AB16 hecc1_ rxd 4 0
PU
VDDSHV
1.8V/3.3V
Yes
24
PU/ PD
LVCMOS
uart3_rts_sd 2 gpio_131 AA17 AB17 Y17 i2c1_scl i2c1_ sda i2c2_scl gpio_168 Y16 i2c2_sda gpio_183 W16 i2c3_scl gpio_184 W17 i2c3_sda gpio_185 B9 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 K22 mcspi1_clk mmc2_dat4 gpio_171 K19 mcspi1_ simo mmc2_dat5 gpio_172 J18 mcspi1_ somi mmc2_dat6 gpio_173 K18 mcspi1_cs0 mmc2_dat7 gpio_174 J20 mcspi1_cs1 mmc3_cmd gpio_175 4 0 0 0 4 0 4 0 4 0 4 0 1 2 3 4 0 1 4 0 1 4 0 1 4 0 1 4 0 3 4
H H H
PU PU PU
0 0 7
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
Yes Yes Yes
40 40 40
Open Drain Open Drain Open Drain
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
Open Drain
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
Open Drain
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
Open Drain
PU
VDDSHV
1.8V/3.3V
Yes
40
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
45
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] J19 mcspi1_cs2 mmc3_clk gpio_176 J21 mcspi1_cs3 hsusb2_ data2 gpio_177 MODE [3] TYPE [4] BALL RESET STATE [5] H BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] PU 7 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
0 3 4 0 3 4
O O IO O IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O IO IO IO IO I I O IO IO I IO I IO IO I IO I IO I IO I IO
Yes
LVCMOS
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mm_fsusb2_t 5 xdat J22 mcspi2_clk hsusb2_ data7 gpio_178 H20 mcspi2_ simo 0 3 4 0
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt9_pwm_e 1 vt hsusb2_ data4 gpio_179 H22 mcspi2_ somi 3 4 0
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt10_pwm_ 1 evt hsusb2_ data5 gpio_180 H21 mcspi2_cs0 3 4 0
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt11_pwm_ 1 evt hsusb2_ data6 gpio_181 H19 mcspi2_cs1 3 4 0
PD
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
gpt8_pwm_e 1 vt hsusb2_ data3 gpio_182 3 4
mm_fsusb2_t 5 xen_n A8 A10 A9 B8 sys_32k sys_xtalin sys_xtalout sys_clkreq gpio_1 AB18 sys_nirq gpio_0 AA18 Y18 sys_ nrespwron sys_ nreswarm gpio_30 AB19 sys_boot0 gpio_2 AB20 sys_boot1 gpio_3 W18 sys_boot2 gpio_4 AA19 sys_boot3 gpio_5 0 0 0 0 4 0 4 0 0 4 0 4 0 4 0 4 0 4
Z Z Z L
Z Z Z Z
0 0 0 0
VDDSHV VDDSOSC VDDSOSC VDDSHV
1.8V/3.3V 1.8V 1.8V 1.8V/3.3V
Yes NA NA Yes
30
30
PU/ PD
PU
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
Z L
Z PD
0 0
VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V
Yes Yes
30 30
PU/ PD PU/ PD
LVCMOS LVCMOS Open Drain
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
46
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] V18 sys_boot4 MODE [3] TYPE [4] BALL RESET STATE [5] Z BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] Z 0 VDDSHV VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] 30 PULL U/D TYPE [12] PU/ PD IO CELL [13]
I O IO I O IO I IO I I O IO O IO I I O IO I O IO IO IO IO O IO O O IO O IO O IO IO O IO IO IO IO IO O IO IO IO IO O IO
Yes
LVCMOS
mmc2_dir_da 1 t2 gpio_6 Y19 sys_boot5 4 0
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
mmc2_dir_da 1 t3 gpio_7 W19 sys_boot6 gpio_8 AA20 Y20 E9 sys_boot7 sys_boot8 sys_clkout1 gpio_10 E10 sys_clkout2 gpio_186 D13 E14 C12 A12 B12 D12 E13 jtag_ntrst jtag_tck jtag_rtck 4 0 4 0 0 0 4 0 4 0 0 0
VDDSHV
1.8V/3.3V
Yes
30
PU/ PD
LVCMOS
Z Z H
Z Z PD
0 0 0/7 (1)
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
Yes Yes Yes
30 30 30
PU/PD PU/PD PU/ PD
LVCMOS LVCMOS LVCMOS
PD
VDDSHV
1.8V/3.3V
Yes
10
PU/ PD
LVCMOS
L L L H H L H
PD PD Z PU PU Z PU
0 0 0 0 0 0 0
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V 1.8V/3.3V
Yes Yes Yes Yes Yes Yes Yes
20 20 20 20 20 20 20
PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD PU/ PD
LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS
jtag_tms_tms 0 c jtag_tdi jtag_tdo jtag_emu0 gpio_11 0 0 0 4 0 4 0
E12
jtag_emu1 gpio_31
PU
VDDSHV
1.8V/3.3V
Yes
20
PU/ PD
LVCMOS
G22
etk_clk
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
mcbsp5_ clkx 1 mmc3_clk hsusb1_stp gpio_12 G21 etk_ctl mmc3_cmd hsusb1_clk gpio_13 2 3 4 0 2 3 4
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
mm_fsusb1_r 5 xdp G20 etk_d0 mcspi3_ simo mmc3_dat4 hsusb1_ data0 gpio_14 0 1 2 3 4
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
mm_fsusb1_r 5 xrcv F22 etk_d1 mcspi3_ somi hsusb1_ data1 gpio_15 0 1 3 4
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
mm_fsusb1_t 5 xse0 F20 etk_d2 mcspi3_cs0 0 1
PU
VDDSHV
1.8V/3.3V
Yes
9, 25
PU/ PD
LVCMOS
(1)
Mux0 if sys_boot6 is pulled down (clock master). TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 47
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] hsusb1_ data2 gpio_16 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
3 4
IO IO IO O IO IO IO IO O I IO IO IO O IO IO IO IO O IO IO IO IO O O IO IO IO IO O IO I IO O IO I IO IO O I O IO O IO O IO IO O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mm_fsusb1_t 5 xdat G19 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_ data7 gpio_17 E19 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_ data4 gpio_18 F21 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_ data5 gpio_19 F19 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_ data6 gpio_20 E21 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_ data3 gpio_21 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4
mm_fsusb1_t 5 xen_n D22 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 D21 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 0 2 3 4 0 2 3 4
mm_fsusb1_r 5 xdm E22 etk_d10 uart1_rx hsusb2_clk gpio_24 E20 etk_d11 mcspi3_clk hsusb2_stp gpio_25 0 2 3 4 0 1 3 4
mm_fsusb2_r 5 xdp E18 etk_d12 0
48
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] hsusb2_dir gpio_26 D20 etk_d13 hsusb2_nxt gpio_27 MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
3 4 0 3 4
I IO O I IO IO O IO IO IO O IO IO IO A PWR VDDS 1.8V 1.2V L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS
mm_fsusb2_r 5 xdm D19 etk_d14 hsusb2_ data0 gpio_28 0 3 4
mm_fsusb2_r 5 xrcv D18 etk_d15 hsusb2_ data1 gpio_29 0 3 4
mm_fsusb2_t 5 xse0 M2 ddr_padref 0
J8, J10, VDD_CORE 0 J12, J14, J16, K9, K11, K13, K15, L8, L10, L12, L14, M7, M9, M11, M13, M15, N8, N10, N12, N14, P7, P9, P11, P13, P15, R8, R10, R12, R14 L17 J6 VDDS_SRA M_MPU VDDS_SRA M_CORE_B G 0 0
PWR PWR
1.8V 1.8V
M17 K6 K17
CAP_VDD_S 0 RAM_MPU CAP_VDD_S 0 RAM_CORE VDDS_DPLL 0 _MPU_USBH OST VDDS_DPLL 0 _PER_CORE VDDA3P3V_ 0 USBPHY VDDA1P8V_ 0 USBPHY CAP_VDDA1 0 P2LDO_USB PHY
PWR PWR PWR
1.2V 1.2V 1.8V
F11 F7 D7 E7
PWR PWR PWR PWR
1.8V 3.3V 1.8V 1.2V
49
AM3517, AM3505

BALL PIN NAME LOCATION [2] [1] A21, B1, E15, E17, F12, F14, F18, G10, G12, G13, G8, G17, H18, J17, L22, N16, P17, R16, R18, T9, T11, T13, T17, U8, U10, U12, U14, U16, U18, V7, V8, V17, AA22, AB11 VDDSHV MODE [3] TYPE [4] BALL RESET STATE [5] BALL RESET REL. POWER [8] RESET REL. MODE [7] STATE [6] VOLTAGE [9] 1.8V/3.3V HYS [10] LOAD (pF) [11] PULL U/D TYPE [12] IO CELL [13]
PWR
F5, F16, VDDS G15, H5, K7, L6, L16, N1, N5, N6, P5, R6, T5, T7, T15, U6, AA1 L5 G9 VREFSSTL VDDSOSC
PWR
1.8V
0 O 0
I PWR GND
.5 * VDDS 1.8V
A1, A11, VSS A22, E6, E16, F6, F13, F15, F17, G5, G7, G11, G14, G16, G18, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, J9, J11, J13, J15, K8, K10, K12, K14, K16, L7, L9, L11, L13, L15, M1, M6, M8, M10, M12, M14, M16, M22, N7, N9, N11, N13, N15, N17, P6, P8, P10, P12, P14, P16, R5, R7, R9, R11, R13, R15, R17, T6, T8, T10, T12, T14, T16, T18, U5, U7, U9, U11, U13, U15, U17, V6, AB1, AB12, AB22 B10 VSSOSC
GND
D8, D9, NC (2) D10, E8, F8, F9, F10, J7, G6 V15 V16 Reserved (3) Reserved (3)
(2) (3)
"NC" indicates "No Connect". For proper device operation, these pins must be left unconnected. For proper device operation, this pin must be pulled up via a 10k- resistor.
50
AM3517, AM3505
2.3
Multiplexing Characteristics
Table 2-3 provides descriptions of the AM3517/05 pin multiplexing on the ZCN and ZER packages. Table 2-3. Multiplexing Characteristics
ZER BALL NO E3 D3 C3 C2 F3 D2 C1 D1 G2 G3 H3 G4 H4 G1 J3 J1 T3 U3 U4 V4 V1 V2 V5 V3 W3 W4 Y3 Y4 AA2 AA3 AA4 AB2 L4 K5 J5 M3 M4 M5 N3 N2 N4 P3 P2 P1 P4 R1 R2 R3 R4 T2 J4
ZCN BALL NO B21 A21 D20 C20 E19 D19 C19 B19 B18 D17 C17 D16 C16 B16 A16 A15 A7 B7 D7 E7 C6 D6 B5 C5 B4 A3 B3 C3 C2 D2 B1 C1 A12 C13 D13 A11 B11 C11 D11 E11 A10 B10 C10 D10 E10 A9 B9 A8 B8 D8 E13
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
MODE 7
sdrc_d0 sdrc_d1 sdrc_d2 sdrc_d3 sdrc_d4 sdrc_d5 sdrc_d6 sdrc_d7 sdrc_d8 sdrc_d9 sdrc_d10 sdrc_d11 sdrc_d12 sdrc_d13 sdrc_d14 sdrc_d15 sdrc_d16 sdrc_d17 sdrc_d18 sdrc_d19 sdrc_d20 sdrc_d21 sdrc_d22 sdrc_d23 sdrc_d24 sdrc_d25 sdrc_d26 sdrc_d27 sdrc_d28 sdrc_d29 sdrc_d30 sdrc_d31 sdrc_ba0 sdrc_ba1 sdrc_ba2 sdrc_a0 sdrc_a1 sdrc_a2 sdrc_a3 sdrc_a4 sdrc_a5 sdrc_a6 sdrc_a7 sdrc_a8 sdrc_a9 sdrc_a10 sdrc_a11 sdrc_a12 sdrc_a13 sdrc_a14 sdrc_ncs0
51
AM3517, AM3505
Table 2-3. Multiplexing Characteristics (continued)

ZER K4 L1 L2 K3 K1 L3 K2 F4 J2 T4 AB3 E2 H2 U1 Y1 E1 H1 U2 Y2 T1 F2 F1 W1 W2 W5 Y5 AB4 AA5 AB5 AB6 AA6 W6 AB7 Y6 AA7 Y7 W7 AA9 Y8 AA8 AB8 W8 W10 AB9 AB10 W9 AA10 Y9 V10 V9 Y10 Y11 Y12 V12 AA11 W12 ZCN A14 A13 B13 D14 C14 E14 B14 C21 B15 E8 D1 B20 B17 A6 A2 A20 A17 B6 B2 C8 A19 A18 A5 A4 E3 E2 E1 F7 F6 F4 F3 F2 F1 G6 G5 G4 G3 G2 G1 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L2 L1 M4 M3 M2 M1 MODE 0 sdrc_ncs1 sdrc_clk sdrc_nclk sdrc_cke0 sdrc_nras sdrc_ncas sdrc_nwe sdrc_dm0 sdrc_dm1 sdrc_dm2 sdrc_dm3 sdrc_dqs0p sdrc_dqs1p sdrc_dqs2p sdrc_dqs3p sdrc_dqs0n sdrc_dqs1n sdrc_dqs2n sdrc_dqs3n sdrc_odt sdrc_strben0 sdrc_strben_dly0 sdrc_strben1 sdrc_strben_dly1 gpmc_a1 gpmc_a2 gpmc_a3 gpmc_a4 gpmc_a5 gpmc_a6 gpmc_a7 gpmc_a8 gpmc_a9 gpmc_a10 gpmc_d0 gpmc_d1 gpmc_d2 gpmc_d3 gpmc_d4 gpmc_d5 gpmc_d6 gpmc_d7 gpmc_d8 gpmc_d9 gpmc_d10 gpmc_d11 gpmc_d12 gpmc_d13 gpmc_d14 gpmc_d15 gpmc_ncs0 gpmc_ncs1 gpmc_ncs2 gpmc_ncs3 gpmc_ncs4 gpmc_ncs5 sys_ndmareq0 sys_ndmareq1 sys_ndmareq2 gpt9_pwm_evt gpt10_pwm_evt gpt9_pwm_evt gpt10_pwm_evt gpio_52 gpio_53 gpio_54 gpio_55 gpio_56 safe_mode safe_mode safe_mode safe_mode gpio_44 gpio_45 gpio_46 gpio_47 gpio_48 gpio_49 gpio_50 gpio_51 sys_ndmareq2 sys_ndmareq3 gpio_34 gpio_35 gpio_36 gpio_37 gpio_38 gpio_39 gpio_40 gpio_41 gpio_42 gpio_43 safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode sdrc_cke0_safe MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7
52
AM3517, AM3505

ZER AA12 V11 AB13 AA14 AB14 AA15 W11 Y15 W14 V13 AA16 Y14 V14 B22 B21 B20 B19 A20 A19 A18 B18 A17 C18 D17 B16 B17 C17 C16 D16 D14 A16 D15 B15 A15 A14 C13 C15 A13 B13 C14 B14 NA NA NA NA NA AB21 AA21 Y21 Y22 W21 W22 W20 V21 V19 V22 ZCN N5 N4 N1 R1 R2 R3 R4 T1 T2 T3 T4 T5 U1 AE23 AD22 AD23 AE24 AD24 AD25 AC23 AC24 AC25 AB24 AB25 AA23 AA24 AA25 Y22 Y23 Y24 Y25 W21 W22 W23 W24 W25 V24 V25 U21 U22 U23 K20 K21 H23 H24 H20 AD2 AD1 AE2 AD3 AE3 AD4 AE4 AC5 AD5 AE5 MODE 0 gpmc_ncs6 gpmc_ncs7 gpmc_clk gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_nbe0_cle gpmc_nbe1 gpmc_nwp gpmc_wait0 gpmc_wait1 gpmc_wait2 gpmc_wait3 dss_pclk dss_hsync dss_vsync dss_acbias dss_data0 dss_data1 dss_data2 dss_data3 dss_data4 dss_data5 dss_data6 dss_data7 dss_data8 dss_data9 dss_data10 dss_data11 dss_data12 dss_data13 dss_data14 dss_data15 dss_data16 dss_data17 dss_data18 dss_data19 dss_data20 dss_data21 dss_data22 dss_data23 tv_vfb1 tv_out1 tv_vfb2 tv_out2 tv_vref ccdc_pclk ccdc_field ccdc_hd ccdc_vd ccdc_wen ccdc_data0 ccdc_data1 ccdc_data2 ccdc_data3 ccdc_data4 ccdc_data9 ccdc_data8 uart4_tx uart4_rts uart4_cts uart4_rx i2c3_sda i2c3_scl gpio_94 gpio_95 gpio_96 gpio_97 gpio_98 gpio_99 gpio_100 gpio_101 gpio_102 gpio_103 hw_dbg4 hw_dbg5 hw_dbg6 hw_dbg2 hw_dbg3 hw_dbg0 hw_dbg1 safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode mcspi3_clk mcspi3_simo mcspi3_somi mcspi3_cs0 mcspi3_cs1 dss_data4 dss_data3 dss_data2 dss_data1 dss_data0 dss_data5 uart3_rx_irrx uart3_tx_irtx uart1_tx uart1_rx uart1_cts uart1_rts uart4_tx uart4_rx sys_ndmareq1 uart3_cts_rctx gpio_63 gpio_64 gpio_65 gpio_66 gpio_67 gpio_68 gpio_69 gpio_70 gpio_71 gpio_72 gpio_73 gpio_74 gpio_75 gpio_76 gpio_77 gpio_78 gpio_79 gpio_80 gpio_81 gpio_82 gpio_83 gpio_84 gpio_85 gpio_86 gpio_87 gpio_88 gpio_89 gpio_90 gpio_91 gpio_92 gpio_93 hw_dbg14 hw_dbg15 hw_dbg16 hw_dbg17 hw_dbg12 hw_dbg13 safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode gpio_60 gpio_61 gpio_62 safe_mode MODE 1 sys_ndmareq3 gpmc_io_dir MODE 2 MODE 3 gpt11_pwm_evt gpt8_pwm_evt MODE 4 gpio_57 gpio_58 gpio_59 MODE 5 MODE 6 MODE 7 safe_mode safe_mode
53
AM3517, AM3505

ZER U20 V20 U19 U21 U22 T19 T20 T21 R22 T22 R20 R19 R21 E5 D5 C5 E4 P22 N21 P21 N20 P19 P20 N22 N19 N18 P18 M21 M20 K20 L19 M18 K21 L18 L20 L21 M19 C4 B4 D4 A4 A5 B5 D6 C6 C22 C21 C19 C20 A3 B3 A2 B2 B11 D11 ZCN Y6 AB6 AC6 AE6 AD6 Y7 AA7 AB7 AC7 AD7 AE7 AD8 AE8 D25 C25 B25 D24 AA9 AB9 AC9 AD9 AE9 AA10 AB10 AC10 AD10 AE10 AD11 AE11 AB12 AC12 AD12 AE12 AB13 AC13 AD13 AE13 B24 C24 A24 C23 F20 F19 E24 E23 AA19 Y19 Y20 W20 B23 A23 B22 A22 R25 P21 MODE 0 ccdc_data5 ccdc_data6 ccdc_data7 rmii_mdio_data rmii_mdio_clk rmii_rxd0 rmii_rxd1 rmii_crs_dv rmii_rxer rmii_txd0 rmii_txd1 rmii_txen rmii_50mhz_clk mcbsp2_fsx mcbsp2_clkx mcbsp2_dr mcbsp2_dx mmc1_clk mmc1_cmd mmc1_dat0 mmc1_dat1 mmc1_dat2 mmc1_dat3 mmc1_dat4 mmc1_dat5 mmc1_dat6 mmc1_dat7 mmc2_clk mmc2_cmd mmc2_dat0 mmc2_dat1 mmc2_dat2 mmc2_dat3 mmc2_dat4 mmc2_dat5 mmc2_dat6 mmc2_dat7 mcbsp3_dx mcbsp3_dr mcbsp3_clkx mcbsp3_fsx uart2_cts uart2_rts uart2_tx uart2_rx uart1_tx uart1_rts uart1_cts uart1_rx mcbsp4_clkx mcbsp4_dr mcbsp4_dx mcbsp4_fsx mcbsp1_clkr mcbsp1_fsr mcspi4_clk mcbsp1_clkr mcspi4_clk mcspi3_cs1 mcspi3_cs0 mmc2_dir_dat0 mmc2_dir_dat1 mmc2_dir_cmd mmc2_clkin uart2_cts uart2_rts uart2_tx uart2_rx mcbsp3_dx mcbsp3_dr mcbsp3_clkx mcbsp3_fsx gpt9_pwm_evt gpt10_pwm_evt gpt11_pwm_evt gpt8_pwm_evt mmc3_dat0 mmc3_dat1 mmc3_dat2 mmc3_dat3 mcspi3_clk mcspi3_simo mcspi3_somi uart4_cts uart4_rts uart4_tx uart4_rx mcspi2_clk mcspi2_simo mcspi2_somi mcspi2_cs0 ccdc_data8 ccdc_data9 ccdc_data10 ccdc_data11 ccdc_data12 ccdc_data13 ccdc_data14 ccdc_data15 MODE 1 MODE 2 MODE 3 MODE 4 gpio_104 gpio_105 gpio_106 gpio_107 gpio_108 gpio_109 gpio_110 gpio_111 gpio_167 gpio_126 gpio_112 gpio_113 gpio_114 gpio_116 gpio_117 gpio_118 gpio_119 gpio_120 gpio_121 gpio_122 gpio_123 gpio_124 gpio_125 gpio_126 gpio_127 gpio_128 gpio_129 gpio_130 gpio_131 gpio_132 gpio_133 gpio_134 gpio_135 gpio_136 gpio_137 gpio_138 gpio_139 gpio_140 gpio_141 gpio_142 gpio_143 gpio_144 gpio_145 gpio_146 gpio_147 gpio_148 gpio_149 gpio_150 gpio_151 gpio_152 gpio_153 gpio_154 gpio_155 gpio_156 gpio_157 hw_dbg10 hw_dbg11 hw_dbg8 hw_dbg9 MODE 5 hw_dbg7 MODE 6 MODE 7 safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode mm_fsusb3_rxdp safe_mode safe_mode mm_fsusb3_rxdm safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode mm_fsusb3_txse safe_mode 0 mm_fsusb3_rxrcv safe_mode mm_fsusb3_txdat safe_mode mm_fsusb3_txen safe_mode _n safe_mode safe_mode
54
AM3517, AM3505

ZER C10 C9 E11 C11 C8 W15 W13 AA13 Y13 A6 B6 C7 B7 A7 AB15 AB16 AA17 AB17 Y17 Y16 W16 W17 B9 K22 K19 J18 K18 J20 J19 J21 J22 H20 H22 H21 H19 AB18 E10 G22 G21 G20 F22 F20 G19 E19 F21 F19 E21 D22 D21 E22 E20 E18 D20 ZCN P22 P23 P25 P24 N24 N2 N3 P1 P2 F25 F24 G24 G25 E25 V2 V3 V4 V5 W1 W2 W4 W5 L25 AE14 AD15 AC15 AB15 AD14 AE15 AE16 AD16 AC16 AB16 AA16 AE17 Y1 M25 AD17 AE18 AD18 AC18 AB18 AA18 Y18 AE19 AD19 AB19 AE20 AD20 AC20 AB20 AE21 AD21 MODE 0 mcbsp1_dx mcbsp1_dr mcbsp_clks mcbsp1_fsx mcbsp1_clkx uart3_cts_rctx uart3_rts_sd uart3_rx_irrx uart3_tx_irtx usb0_dp (1) usb0_dm (1) usb0_vbus usb0_id usb0_drvvbus hecc1_txd hecc1_rxd i2c1_scl i2c1_sda i2c2_scl i2c2_sda i2c3_scl i2c3_sda hdq_sio mcspi1_clk mcspi1_simo mcspi1_somi mcspi1_cs0 mcspi1_cs1 mcspi1_cs2 mcspi1_cs3 mcspi2_clk mcspi2_simo mcspi2_somi mcspi2_cs0 mcspi2_cs1 sys_nirq sys_clkout2 etk_clk etk_ctl etk_d0 etk_d1 etk_d2 etk_d3 etk_d4 etk_d5 etk_d6 etk_d7 etk_d8 etk_d9 etk_d10 etk_d11 etk_d12 etk_d13 mcspi3_clk mcspi3_simo mcspi3_somi mcspi3_cs0 mcspi3_clk mcbsp5_dr mcbsp5_fsx mcbsp5_dx mcspi3_cs1 mmc3_dat3 mmc3_dat0 mmc3_dat1 mmc3_dat2 mmc3_dat7 mmc3_dat6 mmc3_dat5 uart1_rx mcbsp5_clkx mmc3_clk mmc3_cmd mmc3_dat4 hsusb1_stp hsusb1_clk hsusb1_data0 hsusb1_data1 hsusb1_data2 hsusb1_data7 hsusb1_data4 hsusb1_data5 hsusb1_data6 hsusb1_data3 hsusb1_dir hsusb1_nxt hsusb2_clk hsusb2_stp hsusb2_dir hsusb2_nxt gpt9_pwm_evt gpt10_pwm_evt gpt11_pwm_evt gpt8_pwm_evt sys_altclk mmc2_dat4 mmc2_dat5 mmc2_dat6 mmc2_dat7 mmc3_cmd mmc3_clk hsusb2_data2 hsusb2_data7 hsusb2_data4 hsusb2_data5 hsusb2_data6 hsusb2_data3 i2c2_sccbe i2c3_sccbe gpio_168 gpio_183 gpio_184 gpio_185 gpio_170 gpio_171 gpio_172 gpio_173 gpio_174 gpio_175 gpio_176 gpio_177 gpio_178 gpio_179 gpio_180 gpio_181 gpio_182 gpio_0 gpio_186 gpio_12 gpio_13 gpio_14 gpio_15 gpio_16 gpio_17 gpio_18 gpio_19 gpio_20 gpio_21 gpio_22 gpio_23 gpio_24 gpio_25 gpio_26 gpio_27 mm_fsusb2_rxdm mm_fsusb2_rxdp mm_fsusb1_rxdm mm_fsusb1_txen _n mm_fsusb1_rxdp mm_fsusb1_rxrcv mm_fsusb1_txse 0 mm_fsusb1_txdat mm_fsusb2_txen _n mm_fsusb2_txdat safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode hw_dbg0 hw_dbg1 hw_dbg2 hw_dbg3 hw_dbg4 hw_dbg5 hw_dbg6 hw_dbg7 hw_dbg8 hw_dbg9 hw_dbg10 hw_dbg11 hw_dbg12 hw_dbg13 hw_dbg14 hw_dbg15 uart3_tx_irtx uart3_rx_irrx uart3_rts_sd gpio_125 gpio_130 gpio_131 safe_mode safe_mode safe_mode uart3_tx_irtx uart3_rx_irrx mcspi4_cs0 mcbsp3_fsx mcbsp3_clkx MODE 1 mcspi4_simo mcspi4_somi MODE 2 mcbsp3_dx mcbsp3_dr MODE 3 MODE 4 gpio_158 gpio_159 gpio_160 gpio_161 gpio_162 gpio_163 gpio_164 gpio_165 gpio_166 uart1_cts MODE 5 MODE 6 MODE 7 safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode safe_mode
(1)
This mux selection is controlled by CONTROL_DEVCONF2 register. TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 55
AM3517, AM3505

ZER D19 D18 A8 A10 A9 B8 AA18 Y18 AB19 AB20 W18 AA19 V18 Y19 W19 AA20 Y20 E9 D13 E14 C12 A12 B12 D12 E13 E12 M2 ZCN AC21 AE22 K24 K25 H25 M24 Y2 Y3 Y4 AA1 AA2 AA3 AB1 AB2 AC1 AC2 AC3 N25 U24 U25 T21 T22 T23 T24 T25 R24 B12 MODE 0 etk_d14 etk_d15 sys_32k sys_xtalin sys_xtalout sys_clkreq sys_nrespwron sys_nreswarm sys_boot0 sys_boot1 sys_boot2 sys_boot3 sys_boot4 sys_boot5 sys_boot6 sys_boot7 sys_boot8 sys_clkout1 jtag_ntrst jtag_tck jtag_rtck jtag_tms_tmsc jtag_tdi jtag_tdo jtag_emu0 jtag_emu1 ddr_padref gpio_11 gpio_31 gpio_10 safe_mode mmc2_dir_dat2 mmc2_dir_dat3 gpio_30 gpio_2 gpio_3 gpio_4 gpio_5 gpio_6 gpio_7 gpio_8 gpio_1 MODE 1 MODE 2 MODE 3 hsusb2_data0 hsusb2_data1 MODE 4 gpio_28 gpio_29 MODE 5 mm_fsusb2_rxrcv mm_fsusb2_txse 0 MODE 6 MODE 7 hw_dbg16 hw_dbg17
56
AM3517, AM3505
2.4
Signal Description
Many signals are available on multiple pins according to the software configuration of the pin multiplexing options. 1. SIGNAL NAME: The signal name 2. DESCRIPTION: Description of the signal 3. TYPE: Type = Ball type for this specific function: I = Input O = Output Z = High-impedance D = Open Drain DS = Differential A = Analog 4. BALL: Associated ball location 5. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the module/subsystem level. The pin function is selected at the module/system level. Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-2.
2.4.1
External Memory Interfaces

Table 2-4. External Memory Interfaces - GPMC Signals Description
SIGNAL NAME[1] gpmc_a1 gpmc_a2 gpmc_a3 gpmc_a4 gpmc_a5 gpmc_a6 gpmc_a7 gpmc_a8 gpmc_a9 gpmc_a10 gpmc_a11
DESCRIPTION[2] GPMC Address bit 1 GPMC Address bit 2 GPMC Address bit 3 GPMC Address bit 4 GPMC Address bit 5 GPMC Address bit 6 GPMC Address bit 7 GPMC Address bit 8 GPMC Address bit 9
TYPE[3] O O O O O O O O O
ZCN BALL[4] E3/G5 E2/G4 E1/G3 F7/G2 F6/G1 F4/H2 F3/H1 F2/J5 F1/J4 G6/J3 J2
ZER BALL[4] W5/AA7 Y5/Y7 AB4/W7 AA5/AA9 AB5/Y8 AB6/AA8 AA6/AB8 W6/W8 AB7/W10 Y6/AB9 AB10
SUBSYSTEM PIN MULTIPLEXING [5] gpmc_a17 gpmc_a18 gpmc_a19 gpmc_a20 gpmc_a21 gpmc_a22 gpmc_a23 gpmc_a24 gpmc_a25 gpmc_a26
GPMC Address bit 10 O GPMC Address bit 11 O multiplexed on gpmc_d10 GPMC Address bit12 multiplexed on gpmc_d11 GPMC Address bit13 multiplexed on gpmc_d12 GPMC Address bit 14multiplexed on gpmc_d13 GPMC Address bit15 multiplexed on gpmc_d14 GPMC Address bit16 multiplexed on gpmc_d15 GPMC Address bit17 multiplexed on gpmc_a1 O
gpmc_a12
J1
W9
gpmc_a13
K4
AA10
gpmc_a14
K3
Y9
gpmc_a15
K2
V10
gpmc_a16
K1
V9
gpmc_a17
E3
W5
57
AM3517, AM3505
Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)

SIGNAL NAME[1] gpmc_a18 DESCRIPTION[2] GPMC Address bit18 multiplexed on gpmc_a2 GPMC Address bit19 multiplexed on gpmc_a3 GPMC Address bit20 multiplexed on gpmc_a4 GPMC Address bit21 multiplexed on gpmc_a5 GPMC Address bit22 multiplexed on gpmc_a6 GPMC Address bit23 multiplexed on gpmc_a7 GPMC Address bit24 multiplexed on gpmc_a8 GPMC Address bit25 multiplexed on gpmc_a9 GPMC Address bit26 multiplexed on gpmc_a10 GPMC Data bit 0 GPMC Data bit 1 GPMC Data bit 2 GPMC Data bit 3 GPMC Data bit 4 GPMC Data bit 5 GPMC Data bit 6 GPMC Data bit 7 GPMC Data bit 8 GPMC Data bit 9 GPMC Data bit 10 GPMC Data bit 11 GPMC Data bit 12 GPMC Data bit 13 GPMC Data bit 14 GPMC Data bit 15 GPMC Chip Select 0 GPMC Chip Select 1 GPMC Chip Select 2 GPMC Chip Select 3 GPMC Chip Select 4 GPMC Chip Select 5 GPMC Chip Select 6 GPMC Chip Select 7 GPMC clock TYPE[3] O ZCN BALL[4] E2 ZER BALL[4] Y5 SUBSYSTEM PIN MULTIPLEXING [5]
gpmc_a19
E1
AB4
gpmc_a20
F7
AA5
gpmc_a21
F6
AB5
gpmc_a22
F4
AB6
gpmc_a23
F3
AA6
gpmc_a24
F2
W6
gpmc_a25
F1
AB7
gpmc_a26
G6
Y6
gpmc_d0 gpmc_d1 gpmc_d2 gpmc_d3 gpmc_d4 gpmc_d5 gpmc_d6 gpmc_d7 gpmc_d8 gpmc_d9 gpmc_d10 gpmc_d11 gpmc_d12 gpmc_d13 gpmc_d14 gpmc_d15 gpmc_ncs0 gpmc_ncs1 gpmc_ncs2 gpmc_ncs3 gpmc_ncs4 gpmc_ncs5 gpmc_ncs6 gpmc_ncs7 gpmc_clk
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O O O O O
G5 G4 G3 G2 G1 H2 H1 J5 J4 J3 J2 J1 K4 K3 K2 K1 L2 L1 M4 M3 M2 M1 N5 N4 N1
AA7 Y7 W7 AA9 Y8 AA8 AB8 W8 W10 AB9 AB10 W9 AA10 Y9 V10 V9 Y10 Y11 Y12 V12 AA11 W12 AA12 V11 AB13
gpmc_a1/gpmc_d0 gpmc_a2/gpmc_d1 gpmc_a3/gpmc_d2 gpmc_a4/gpmc_d3 gpmc_a5/gpmc_d4 gpmc_a6/gpmc_d5 gpmc_a7/gpmc_d6 gpmc_a8/gpmc_d7 gpmc_a9/gpmc_d8 gpmc_a10/gpmc_d9 gpmc_a11/gpmc_d10 gpmc_a12/gpmc_d11 gpmc_a13/gpmc_d12 gpmc_a14/gpmc_d13 gpmc_a15/gpmc_d14 gpmc_a16/gpmc_d15
58
AM3517, AM3505
Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)

SIGNAL NAME[1] gpmc_nadv_ale DESCRIPTION[2] Address Valid or Address Latch Enable Output Enable Write Enable Lower Byte Enable. Also used for Command Latch Enable Upper Byte Enable Flash Write Protect External indication of wait External indication of wait External indication of wait External indication of wait TYPE[3] O ZCN BALL[4] R1 ZER BALL[4] AA14 SUBSYSTEM PIN MULTIPLEXING [5]
gpmc_noe gpmc_nwe gpmc_nbe0_cle
O O O
R2 R3 R4
AB14 AA15 W11
gpmc_nbe1 gpmc_nwp gpmc_wait0 gpmc_wait1 gpmc_wait2 gpmc_wait3
O O I I I I
T1 T2 T3 T4 T5 U1
Y15 W14 V13 AA16 Y14 V14
Table 2-5. External Memory Interfaces - SDRC Signals Description

SIGNAL NAME[1] sdrc_d0 sdrc_d1 sdrc_d2 sdrc_d3 sdrc_d4 sdrc_d5 sdrc_d6 sdrc_d7 sdrc_d8 sdrc_d9 sdrc_d10 sdrc_d11 sdrc_d12 sdrc_d13 sdrc_d14 sdrc_d15 sdrc_d16 sdrc_d17 sdrc_d18 sdrc_d19 sdrc_d20 sdrc_d21 sdrc_d22 sdrc_d23 sdrc_d24 sdrc_d25 sdrc_d26 DESCRIPTION [2] SDRAM data bit 0 SDRAM data bit 1 SDRAM data bit2 SDRAM data bit 3 SDRAM data bit 4 SDRAM data bit 5 SDRAM data bit 6 SDRAM data bit 7 SDRAM data bit 8 SDRAM data bit 9 SDRAM data bit 10 SDRAM data bit 11 SDRAM data bit 12 SDRAM data bit 13 SDRAM data bit 14 SDRAM data bit 15 SDRAM data bit 16 SDRAM data bit 17 SDRAM data bit 18 SDRAM data bit 19 SDRAM data bit 20 SDRAM data bit 21 SDRAM data bit 22 SDRAM data bit 23 SDRAM data bit 24 SDRAM data bit 25 SDRAM data bit 26 TYPE [3] IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO ZCN BALL [4] B21 A21 D20 C20 E19 D19 C19 B19 B18 D17 C17 D16 C16 B16 A16 A15 A7 B7 D7 E7 C6 D6 B5 C5 B4 A3 B3 ZER BALL [4] E3 D3 C3 C2 F3 D2 C1 D1 G2 G3 H3 G4 H4 G1 J3 J1 T3 U3 U4 V4 V1 V2 V5 V3 W3 W4 Y3 TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 59
AM3517, AM3505
Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)

SIGNAL NAME[1] sdrc_d27 sdrc_d28 sdrc_d29 sdrc_d30 sdrc_d31 sdrc_ba0 sdrc_ba1 sdrc_ba2 sdrc_a0 sdrc_a1 sdrc_a2 sdrc_a3 sdrc_a4 sdrc_a5 sdrc_a6 sdrc_a7 sdrc_a8 sdrc_a9 sdrc_a10 sdrc_a11 sdrc_a12 sdrc_a13 sdrc_a14 sdrc_ncs0 sdrc_ncs1 sdrc_clk sdrc_nclk sdrc_cke0 sdrc_nras sdrc_ncas sdrc_nwe sdrc_dm0 sdrc_dm1 sdrc_dm2 sdrc_dm3 sdrc_strben0 sdrc_strben_dly0 sdrc_strben1 sdrc_strben_dly1 sdrc_odt sdrc_dqs0p sdrc_dqs0n sdrc_dqs1p 60 DESCRIPTION [2] SDRAM data bit 27 SDRAM data bit 28 SDRAM data bit 29 SDRAM data bit 30 SDRAM data bit 31 SDRAM bank select 0 SDRAM bank select 1 SDRAM bank select 2 SDRAM address bit 0 SDRAM address bit 1 SDRAM address bit 2 SDRAM address bit 3 SDRAM address bit 4 SDRAM address bit 5 SDRAM address bit 6 SDRAM address bit 7 SDRAM address bit 8 SDRAM address bit 9 SDRAM address bit 10 SDRAM address bit 11 SDRAM address bit 12 SDRAM address bit 13 SDRAM address bit 14 Chip select 0 Chip select 1 Clock Clock Invert Clock Enable 0 SDRAM Row Access SDRAM column address strobe SDRAM write enable Data Mask 0 Data Mask 1 Data Mask 2 Data Mask 3 PCB layout trace loop 0 pin 0 PCB layout trace loop 0 pin 1 PCB layout trace loop 1 pin 0 PCB layout trace loop 1 pin 1 On-die termination output for sdrc_ncs0 only Data Strobe 0 Data Strobe 0 Data Strobe 1 TYPE [3] IO IO IO IO IO O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O A A A A O IO IO IO ZCN BALL [4] C3 C2 D2 B1 C1 A12 C13 D13 A11 B11 C11 D11 E11 A10 B10 C10 D10 E10 A9 B9 A8 B8 D8 E13 A14 A13 B13 D14 C14 E14 B14 C21 B15 E8 D1 A19 A18 A5 A4 C8 B20 A20 B17 ZER BALL [4] Y4 AA2 AA3 AA4 AB2 L4 K5 J5 M3 M4 M5 N3 N2 N4 P3 P2 P1 P4 R1 R2 R3 R4 T2 J4 K4 L1 L2 K3 K1 L3 K2 F4 J2 T4 AB3 F2 F1 W1 W2 T1 E2 E1 H2
AM3517, AM3505
Table 2-5. External Memory Interfaces - SDRC Signals Description (continued)

SIGNAL NAME[1] sdrc_dqs1n sdrc_dqs2p sdrc_dqs2n sdrc_dqs3p sdrc_dqs3n ddr_padref DESCRIPTION [2] Data Strobe 1 Data Strobe 2 Data Strobe 2 Data Strobe 3 Data Strobe 3 Impedance control for DDR2 output. This pin must be connected to ground via a 50-ohm ( 2%) resistor. VREFSSTL is .5 * VDDS = 0.9V for DDR data PHY0 reference voltage input TYPE [3] IO IO IO IO IO A ZCN BALL [4] A17 A6 B6 A2 B2 B12 ZER BALL [4] H1 U1 U2 Y1 Y2 M2
VREFSSTL
IO
F14
L5
2.4.2
Video Interfaces
Table 2-6. Video Interfaces - CCDC Signals Description
SIGNAL NAME[1] ccdc_pclk ccdc_field ccdc_hd ccdc_vd ccdc_wen ccdc_data0 ccdc_data1 ccdc_data2 ccdc_data3 ccdc_data4 ccdc_data5 ccdc_data6 ccdc_data7 ccdc_data8 ccdc_data9 ccdc_data10 ccdc_data11 ccdc_data12 ccdc_data13 ccdc_data14 ccdc_data15 (1)
DESCRIPTION [2] CCDC pixel clock CCDC field ID signal CCDC horizontal sync CCDC vertical sync CCDC write enable CCDC data bit 0 CCDC data bit 1 CCDC data bit 2 CCDC data bit 3 CCDC data bit 4 CCDC data bit 5 CCDC data bit 6 CCDC data bit 7 CCDC data bit 8 CCDC data bit 9 CCDC data bit 10 CCDC data bit 11 CCDC data bit 12 CCDC data bit 13 CCDC data bit 14 CCDC data bit 15
TYPE [3] IO IO IO IO I I I I I I I I I I I I I I I I I
ZCN BALL [4] AD2 AD1 AE2 AD3 AE3 AD4 AE4 AC5 AD5 AE5 Y6 AB6 AC6 AE6 AD6 Y7 AA7 AB7 AC7 AD7 AE7
ZER BALL [4] AB21 AA21 Y21 Y22 W21 W22 W20 V21 V19 V22 U20 V20 U19 U21 U22 T19 T20 T21 R22 T22 R20
SYSTEM MUX MODE (1) mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode0 mode1 mode1 mode1 mode1 mode1 mode1 mode1 mode1
See Multiplexing Characteristics table for more information.
Table 2-7. Video Interfaces - DSS Signals Description

SIGNAL NAME[1] dss_pclk dss_hsync dss_vsync DESCRIPTION [2] LCD Pixel Clock LCD Horizontal Synchronization LCD Vertical Synchronization TYPE [3] O O O ZCN BALL [4] AE23 AD22 AD23 ZER BALL [4] B22 B21 B20
61
AM3517, AM3505
Table 2-7. Video Interfaces - DSS Signals Description (continued)

SIGNAL NAME[1] dss_acbias DESCRIPTION [2] AC bias control (STN) or pixel data enable (TFT) output LCD Pixel Data bit 0 LCD Pixel Data bit 1 LCD Pixel Data bit 2 LCD Pixel Data bit 3 LCD Pixel Data bit 4 LCD Pixel Data bit 5 LCD Pixel Data bit 6 LCD Pixel Data bit 7 LCD Pixel Data bit 8 LCD Pixel Data bit 9 LCD Pixel Data bit 10 LCD Pixel Data bit 11 LCD Pixel Data bit 12 LCD Pixel Data bit 13 LCD Pixel Data bit 14 LCD Pixel Data bit 15 LCD Pixel Data bit 16 LCD Pixel Data bit 17 LCD Pixel Data bit 18 LCD Pixel Data bit 19 LCD Pixel Data bit 20 LCD Pixel Data bit 21 LCD Pixel Data bit 22 LCD Pixel Data bit 23 TYPE [3] O ZCN BALL [4] AE24 ZER BALL [4] B19
dss_data0 dss_data1 dss_data2 dss_data3 dss_data4 dss_data5 dss_data6 dss_data7 dss_data8 dss_data9 dss_data10 dss_data11 dss_data12 dss_data13 dss_data14 dss_data15 dss_data16 dss_data17 dss_data18 dss_data19 dss_data20 dss_data21 dss_data22 dss_data23
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O
AD24 AD25 AC23 AC24 AC25 AB24 AB25 AA23 AA24 AA25 Y22 Y23 Y24 Y25 W21 W22 W23 W24 W25 V24 V25 U21 U22 U23
A20 A19 A18 B18 A17 C18 D17 B16 B17 C17 C16 D16 D14 A16 D15 B15 A15 A14 C13 C15 A13 B13 C14 B14
Table 2-8. Video Interfaces RFBI Signals Description

SIGNAL NAME [1] rfbi_a0 rfbi_cs0 rfbi_da0 rfbi_da1 rfbi_da2 rfbi_da3 rfbi_da4 rfbi_da5 rfbi_da6 rfbi_da7 rfbi_da8 rfbi_da9 rfbi_da10 rfbi_da11 rfbi_da12 rfbi_da13 DESCRIPTION [2] RFBI command/data control 1st LCD chip select RFBI data bus 0 RFBI data bus 1 RFBI data bus 2 RFBI data bus 3 RFBI data bus 4 RFBI data bus 5 RFBI data bus 6 RFBI data bus 7 RFBI data bus 8 RFBI data bus 9 RFBI data bus 10 RFBI data bus 11 RFBI data bus 12 RFBI data bus 13 TYPE [3] O O IO IO IO IO IO IO IO IO IO IO IO IO IO IO ZCN BALL [4] AE24 AD22 AD24 AD25 AC23 AC24 AC25 AB24 AB25 AA23 AA24 AA25 Y22 Y23 Y24 Y25 ZER BALL [4] B19 B21 A20 A19 A18 B18 A17 C18 D17 B16 B17 C17 C16 D16 D14 A16 SUBSYSTEM PIN MULTIPLEXING [5] dss_acbias dss_hsync dss_data0 dss_data1 dss_data2 dss_data3 dss_data4 dss_data5 dss_data6 dss_data7 dss_data8 dss_data9 dss_data10 dss_data11 dss_data12 dss_data13
62
AM3517, AM3505
Table 2-8. Video Interfaces RFBI Signals Description (continued)

SIGNAL NAME [1] rfbi_da14 rfbi_da15 rfbi_rd rfbi_wr rfbi_te_vsync0 DESCRIPTION [2] RFBI data bus 14 RFBI data bus 15 Write Enable for RFBI TYPE [3] IO IO O ZCN BALL [4] W21 W22 AE23 AD23 W23 ZER BALL [4] D15 B15 B22 B20 A15 SUBSYSTEM PIN MULTIPLEXING [5] dss_data14 dss_data15 dss_pclk dss_vsync dss_data16
Read enable for RFBI O
tearing effect removal I and Vsync input from 1st LCD Hsync for 1st LCD I tearing effect removal I and Vsync input from 2nd LCD Hsync for 2nd LCD 2nd LCD chip select I O
rfbi_hsync0 rfbi_te_vsync1
W24 W25
A14 C13
dss_data17 dss_data18
rfbi_hsync1 rfbi_cs1
V24 V25
C15 A13
dss_data19 dss_data20
Table 2-9. Video Interfaces TV Signals Description

SIGNAL NAME [1] tv_out1 tv_out2 tv_vfb1 DESCRIPTION [2] TV analog output Composite: tv_out1 TV analog output S-VIDEO: tv_out2 tv_vfb1: Feedback through external resistor to composite tv_vfb2: Feedback through external resistor to S-VIDEO External capacitor TYPE [3] O O O ZCN BALL [4] K21 H24 K20 ZER BALL [4] NA NA NA
tv_vfb2
H23
NA
tv_vref
H20
NA
2.4.3
Serial Communication Interfaces

Table 2-10. HDQ Signals Description
SIGNAL NAME [1] hdq_sio
DESCRIPTION [2]
TYPE [3]
ZCN BALL [4] L25
ZER BALL [4] B9
Bidirectional HDQ 1-Wire IO control and data Interface. Output is open drain.
Table 2-11. Serial Communication Interfaces I2C Signals Description (I2C1)

SIGNAL NAME [1] i2c1_scl i2c1_sda DESCRIPTION [2] I2C Master Serial clock. Output is open drain. I2C Serial Bidirectional Data. Output is open drain. TYPE [3] IOD IOD ZCN BALL [4] V4 V5 ZER BALL [4] AA17 AB17
Table 2-12. Serial Communication Interfaces - I2C Signals Description (I2C2)

SIGNAL NAME [1] i2c2_scl i2c2_sda DESCRIPTION [2] I2C Master Serial clock. Output is open drain. I2C Serial Bidirectional Data. Output is open drain. TYPE [3] IOD IOD ZCN BALL [4] W1 W2 ZER BALL [4] Y17 Y16
63
AM3517, AM3505
Table 2-13. Serial Communication Interfaces - I2C Signals Description (I2C3)

SIGNAL NAME [1] i2c3_scl i2c3_sda DESCRIPTION [2] I2C Master Serial clock. Output is open drain. I2C Serial Bidirectional Data. Output is open drain. TYPE [3] IOD IOD ZCN BALL [4] W4 W5 ZER BALL [4] W16 W17
Table 2-14. Serial Communication Interfaces McBSP LP Signals Description

SIGNAL NAME [1] mcbsp1_dr mcbsp1_clkr mcbsp1_fsr mcbsp1_dx mcbsp1_clkx mcbsp1_fsx mcbsp_clks DESCRIPTION [2] Received serial data Receive Clock Receive frame synchronization Transmitted serial data Transmit clock Transmit frame synchronization External clock input (shared by McBSP1, 2, 3, 4, and 5) Received serial data Transmitted serial data Combined serial clock Combined frame synchronization TYPE [3] I IO IO IO IO IO I ZCN BALL [4] P23 R25 P21 P22 N24 P24 P25 ZER BALL [4] C9 B11 D11 C10 C8 C11 E11 MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 1)
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 2) mcbsp2_dr mcbsp2_dx mcbsp2_clkx mcbsp2_fsx I IO IO IO B25 D24 C25 D25 C5 E4 D5 E5
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3) mcbsp3_dr mcbsp3_dx mcbsp3_clkx mcbsp3_fsx Received serial data Transmitted serial data Combined serial clock Combined frame synchronization Received serial data Transmitted serial data Combined serial clock Combined frame synchronization Received serial data Transmitted serial data Combined serial clock Combined frame synchronization I IO IO IO C24 B24 A24 C23 B4 C4 D4 A4
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 4) mcbsp4_dr mcbsp4_dx mcbsp4_clkx mcbsp4_fsx I IO IO IO A23 B22 B23 A22 B3 A2 A3 B2
MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 5) mcbsp5_dr mcbsp5_dx mcbsp5_clkx mcbsp5_fsx I IO IO IO Y18 AD19 AD17 AE19 E19 F19 G22 F21
Table 2-15. Serial Communication Interfaces McSPI Signals Description

SIGNAL NAME [1] mcspi1_clk DESCRIPTION [2] SPI Clock TYPE [3] IO ZCN BALL [4] AE14 ZER BALL [4] K22 MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)
64
AM3517, AM3505
Table 2-15. Serial Communication Interfaces McSPI Signals Description (continued)

SIGNAL NAME [1] mcspi1_simo mcspi1_somi mcspi1_cs0 mcspi1_cs1 mcspi1_cs2 mcspi1_cs3 DESCRIPTION [2] TYPE [3] ZCN BALL [4] AD15 AC15 AB15 AD14 AE15 AE16 ZER BALL [4] K19 J18 K18 J20 J19 J21 Slave data in, master data IO out Slave data out, master data in SPI Enable 0, polarity configured by software SPI Enable 1, polarity configured by software SPI Enable 2, polarity configured by software SPI Enable 3, polarity configured by software SPI Clock IO IO O O O
MULTICHANNEL SERIAL PORT INTERFACE (McSPI2) mcspi2_clk mcspi2_simo mcspi2_somi mcspi2_cs0 mcspi2_cs1 IO AD16,AC9 AC16,AD9 AB16,AE9 AA16,AA10 AE17 J22 H20 H22 H21 H19 Slave data in, master data IO out Slave data out, master data in SPI Enable 0, polarity configured by software SPI Enable 1, polarity configured by software SPI Clock IO IO O
MULTICHANNEL SERIAL PORT INTERFACE (McSPI3) mcspi3_clk mcspi3_simo mcspi3_somi mcspi3_cs0 mcspi3_cs1 IO W25,AD11,AA18 V24,AE11,AD18 V25, AB12, AC18 U21,AE12,AB18 U22, AD12, AB19 C13, M21, G19, E20 C15, M20, G20 A13, K20, F22 B13, K21, F20 C14, M18, E21 Slave data in, master data IO out Slave data out, master data in SPI Enable 0, polarity configured by software SPI Enable 1, polarity configured by software SPI Clock IO IO O
MULTICHANNEL SERIAL PORT INTERFACE (McSPI4) mcspi4_clk mcspi4_simo mcspi4_somi mcspi4_cs0 IO W20, R25 P22 P23 P24 C20, B11 C10 C9 C11 Slave data in, master data IO out Slave data out, master data in SPI Enable 0, polarity configured by software IO IO
Table 2-16. Serial Communication Interfaces HECC Signals Description

SIGNAL NAME [1] hecc1_txd hecc1_rxd DESCRIPTION [2] Transmit serial data pin Receive serial data pin TYPE [3] O I ZCN BALL [4] V2 V3 ZER BALL [4] AB15 AB16
Table 2-17. Serial Communication Interfaces EMAC (RMII) Signals Description

SIGNAL NAME [1] rmii_mdio_data rmii_mdio_clk rmii_rxd0 rmii_rxd1 DESCRIPTION [2] Management data I/O Management data clock EMAC receive data pin 0 EMAC receive data pin 1 TYPE [3] IO O I I ZCN BALL [4] AE6 AD6 Y7 AA7 ZER BALL [4] U21 U22 T19 T20 TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 65
AM3517, AM3505
Table 2-17. Serial Communication Interfaces EMAC (RMII) Signals Description (continued)
SIGNAL NAME [1] rmii_crs_dv rmii_rxer rmii_txd0 rmii_txd1 rmii_txen rmii_50mhz_clk DESCRIPTION [2] EMAC carrier sense/receive data valid EMAC receive error EMAC transmit data pin 0 EMAC transmit data pin 1 EMAC transmit enable TYPE [3] I I O O O ZCN BALL [4] AB7 AC7 AD7 AE7 AD8 AE8 ZER BALL [4] T21 R22 T22 R20 R19 R21
EMAC RMII 50 MHz clock I
Table 2-18. Serial Communication Interfaces UARTs Signals Description

SIGNAL NAME [1] uart1_cts uart1_rts uart1_rx uart1_tx uart2_cts uart2_rts uart2_rx uart2_tx uart3_cts_rctx DESCRIPTION [2] UART1 Clear To Send UART1 Request To Send UART1 Receive data UART1 Transmit data UART2 Clear To Send UART2 Request To Send UART2 Receive data UART2 Transmit data UART3 Clear To Send (input), Remote TX (output) UART3 Request To Send , IR enable UART3 Receive data , IR and Remote RX UART3 Transmit data , IR TX UART4 Clear To Send UART4 Request To Send UART4 Receive data UART4 Transmit data TYPE [3] I O I O I O I O IO ZCN BALL [4] AD24,Y20,P25 AD25,Y19 AA23,W20,AC20 AB25,AA19 B24,F20 C24,F19 C23,E23 A24,E24 U1,N2 ZER BALL [4] C19,A20,E11 C21,A19 C20,B16,E22 C22,D17 A5,C4 B5,B4 C6,A4 D6,D4 W15,V14 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA
uart3_rts_sd uart3_rx_irrx uart3_tx_irtx
O I O
N3,V3 AC25,P1,F25,V2 AB24,P2,F24,E25
W13AB16 AA13,A17,A6,AB15 Y13,C18,B6,A7
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4) uart4_cts uart4_rts uart4_rx uart4_tx I O I O AD3,AD11 AE2,AE11 T5,AE3,AC12 T4,AD1,AB12 Y22,M21 Y21,M20 Y14,W21,L19 AA16,AA21,K20
Table 2-19. Serial Communication Interfaces USB Signals Description

SIGNAL NAME [1] usb0_dp usb0_dm usb0_drvvbus usb0_id DESCRIPTION [2] TYPE [3] ZCN BALL [4] F25 F24 E25 G25 ZER BALL [4] A6 B6 A7 B7 UNIVERSAL SERIAL BUS INTERFACE (USB0) USB D+ (differential signal A pair) USB D- (differential signal pair) Digital output to control external supply USB operating mode identification pin A O A
66
AM3517, AM3505
Table 2-19. Serial Communication Interfaces USB Signals Description (continued)

SIGNAL NAME [1] usb0_vbus DESCRIPTION [2] TYPE [3] ZCN BALL [4] G24 ZER BALL [4] C7 For host or device mode A operation, tie the VBUS/USB power signal to the USB connector. When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector. Vminus receive data (not used in 3- or 4-pin configurations) Vplus receive data (not used in 3- or 4-pin configurations) Differential receiver signal input (not used in 3-pin mode) Single-ended zero. Used as VM in 4-pin VP_VM mode. USB data. Used as VP in 4-pin VP_VM mode. Transmit enable Vminus receive data (not used in 3- or 4-pin configurations) Vplus receive data (not used in 3- or 4-pin configurations) Differential receiver signal input (not used in 3-pin mode) Single-ended zero. Used as VM in 4-pin VP_VM mode. USB data. Used as VP in 4-pin VP_VM mode. Transmit enable Vminus receive data (not used in 3- or 4-pin configurations) Vplus receive data (not used in 3- or 4-pin configurations) Differential receiver signal input (not used in 3-pin mode) Single-ended zero. Used as VM in 4-pin VP_VM mode. USB data. Used as VP in 4-pin VP_VM mode. Transmit enable IO
MM_FSUSB3 mm_fsusb3_rxdm AE13 M19
mm_fsusb3_rxdp
IO
AC13
L20
mm_fsusb3_rxrcv
IO
A23
B3
mm_fsusb3_txse0
IO
B23
A3
mm_fsusb3_txdat mm_fsusb3_txen_n MM_FSUSB2 mm_fsusb2_rxdm
IO IO IO
B22 A22 AD21
A2 B2 D20
mm_fsusb2_rxdp
IO
AB20
E20
mm_fsusb2_rxrcv
IO
AC21
D19
mm_fsusb2_txse0
IO
AE22
D18
mm_fsusb2_txdat mm_fsusb2_txen_n MM_FSUSB1 mm_fsusb1_rxdm
IO IO IO
AE16 AE17 AD20
J21 H19 D21
mm_fsusb1_rxdp
IO
AE18
G21
mm_fsusb1_rxrcv
IO
AD18
G20
mm_fsusb1_txse0
IO
AC18
F22
mm_fsusb1_txdat mm_fsusb1_txen_n HSUSB2
IO IO
AB18 AB19
F20 E21
67
AM3517, AM3505

SIGNAL NAME [1] hsusb2_clk DESCRIPTION [2] Dedicated for external transceiver 60-MHz clock input from PHY Dedicated for external transceiver Stop signal Dedicated for external transceiver Data direction control from PHY Dedicated for external transceiver Next signal from PHY Dedicated for external transceiver Bidirectional data bus Dedicated for external transceiver Bidirectional data bus Dedicated for external transceiver Bidirectional data bus Dedicated for external transceiver Bidirectional data bus TYPE [3] O ZCN BALL [4] AC20 ZER BALL [4] E22
hsusb2_stp hsusb2_dir
O I
AB20 AE21
E20 E18
hsusb2_nxt
AD21
D20
hsusb2_data0
IO
AC21
D19
hsusb2_data1
IO
AE22
D18
hsusb2_data2
IO
AE16
J21
hsusb2_data3
IO
AE17
H19
hsusb2_data4
Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation. Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation. Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation. Dedicated for external transceiver Bidirectional data bus Dedicated for external transceiver 60-MHz clock input from PHY Dedicated for external transceiver Stop signal Dedicated for external transceiver Data direction control from PHY Dedicated for external transceiver Next signal from PHY Dedicated for external transceiver Bidirectional data bus Dedicated for external transceiver Bidirectional data bus Dedicated for external transceiver Bidirectional data bus IO
AC16
H20
hsusb2_data5
AB16
H22
hsusb2_data6
AA16
H21
hsusb2_data7
AD16
J22
HSUSB1 hsusb1_clk O AE18 G21
hsusb1_stp hsusb1_dir
O I
AD17 AE20
G22 D22
hsusb1_nxt
AD20
D21
hsusb1_data0
IO
AD18
G20
hsusb1_data1
IO
AC18
F22
hsusb1_data2
IO
AB18
F20
68
AM3517, AM3505

SIGNAL NAME [1] hsusb1_data3 DESCRIPTION [2] Dedicated for external transceiver Bidirectional data bus TYPE [3] IO ZCN BALL [4] AB19 ZER BALL [4] E21
hsusb1_data4
Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation Dedicated for external IO transceiver Bidirectional data bus additional signals for 12-pin ULPI operation
Y18
E19
hsusb1_data5
AE19
F21
hsusb1_data6
AD19
F19
hsusb1_data7
AA18
G19
2.4.4
Removable Media Interfaces

Table 2-20. Removable Media Interfaces MMC/SDIO Signals Description
SIGNAL NAME [1] mmc1_clk mmc1_cmd mmc1_dat0 mmc1_dat1 mmc1_dat2 mmc1_dat3 mmc1_dat4 mmc1_dat5 mmc1_dat6 mmc1_dat7 mmc2_clk mmc2_dir_dat0
DESCRIPTION [2] MMC/SD Output Clock
TYPE [3] O
ZCN BALL [4] AA9 AB9 AC9 AD9 AE9 AA10 AB10 AC10 AD10 AE10 AD11 AB13
ZER BALL [4] P22 N21 P21 N20 P19 P20 N22 N19 N18 P18 M21 L18
MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1) MMC/SD command signal IO MMC/SD Card Data bit 0 / IO SPI Serial Input MMC/SD Card Data bit 1 MMC/SD Card Data bit 2 MMC/SD Card Data bit 3 MMC/SD Card Data bit 4 MMC/SD Card Data bit 5 MMC/SD Card Data bit 6 MMC/SD Card Data bit 7 MMC/SD Output Clock Direction control for DAT0 signal case an external transceiver used IO IO IO IO IO IO IO O O
MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)
mmc2_dir_dat1
Direction control for DAT1 O and DAT3 signals case an external transceiver used Direction control for DAT2 signal case an external transceiver used O
AC13
L20
mmc2_dir_dat2
AB1
V18
mmc2_dir_dat3
Direction control for DAT4, O DAT5, DAT6, and DAT7 signals case an external transceiver used MMC/SD input clock MMC/SD Card Data bit 0 MMC/SD Card Data bit 1 MMC/SD Card Data bit 2 I IO IO IO
AB2
Y19
mmc2_clkin mmc2_dat0 mmc2_dat1 mmc2_dat2
AE13 AB12 AC12 AD12
NA K20 L19 M18 TERMINAL DESCRIPTION 69
Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Table 2-20. Removable Media Interfaces MMC/SDIO Signals Description (continued)

SIGNAL NAME [1] mmc2_dat3 mmc2_dat4 mmc2_dat5 mmc2_dat6 mmc2_dat7 mmc2_dir_cmd DESCRIPTION [2] MMC/SD Card Data bit 3 MMC/SD Card Data bit 4 MMC/SD Card Data bit 5 MMC/SD Card Data bit 6 MMC/SD Card Data bit 7 Direction control for CMD signal case an external transceiver is used TYPE [3] IO IO IO IO IO O ZCN BALL [4] AE12 AB13 AC13 AD13 AE13 AD13 ZER BALL [4] K21 L18 L20 L21 M19 NA
mmc2_cmd mmc3_clk mmc3_cmd mmc3_dat0 mmc3_dat1 mmc3_dat2 mmc3_dat3 mmc3_dat4 mmc3_dat5 mmc3_dat6 mmc3_dat7
MMC/SD command signal IO MMC/SD Output Clock O
AE11 AE15,AD17 AD14,AE18 AB13,Y18 AC13,AE19 AD13,AD19 AE13,AA18 AD18 AD20 AE20 AB19
M20 J19,G22 J20,G21 E19,L18 L20,F21 L21,F19 M19,G19 G20 D21 D22 E21
MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3) MMC/SD command signal IO MMC/SD Card Data bit 0 / IO SPI Serial Input MMC/SD Card Data bit 1 MMC/SD Card Data bit 2 MMC/SD Card Data bit 3 MMC/SD Card Data bit 4 MMC/SD Card Data bit 5 MMC/SD Card Data bit 6 MMC/SD Card Data bit 7 IO IO IO IO IO IO IO
70
AM3517, AM3505
2.4.5
Test Interfaces
Table 2-21. Test Interfaces ETK Signals Description
SIGNAL NAME [1] etk_ctl etk_clk etk_d0 etk_d1 etk_d2 etk_d3 etk_d4 etk_d5 etk_d6 etk_d7 etk_d8 etk_d9 etk_d10 etk_d11 etk_d12 etk_d13 etk_d14 etk_d15
DESCRIPTION [2] ETK trace ctl ETK trace clock ETK data 0 ETK data 1 ETK data 2 ETK data 3 ETK data 4 ETK data 5 ETK data 6 ETK data 7 ETK data 8 ETK data 9 ETK data 10 ETK data 11 ETK data 12 ETK data 13 ETK data 14 ETK data 15
TYPE [3] O O O O O O O O O O O O O O O O O O
ZCN BALL [4] AE18 AD17 AD18 AC18 AB18 AA18 Y18 AE19 AD19 AB19 AE20 AD20 AC20 AB20 AE21 AD21 AC21 AE22
ZER BALL [4] G21 G22 G20 F22 F20 G19 E19 F21 F19 E21 D22 D21 E22 E20 E18 D20 D19 D18
Table 2-22. Test Interfaces JTAG Signals Description

SIGNAL NAME [1] jtag_ntrst jtag_tck jtag_rtck jtag_tms_tmsc jtag_tdi jtag_tdo jtag_emu0 jtag_emu1 DESCRIPTION [2] Test Reset Test Clock ARM Clock Emulation Test Mode Select Test Data Input Test Data Output Test emulation 0 Test emulation 1 TYPE [3] I I O IO I O IO IO ZCN BALL [4] U24 U25 T21 T22 T23 T24 T25 R24 ZER BALL [4] D13 E14 C12 A12 B12 D12 E13 E12
Table 2-23. Test Interfaces HWDBG Signals Description

SIGNAL NAME [1] hw_dbg0 hw_dbg1 hw_dbg2 hw_dbg3 hw_dbg4 hw_dbg5 hw_dbg6 hw_dbg7 hw_dbg8 hw_dbg9 hw_dbg10 hw_dbg11 hw_dbg12 DESCRIPTION [2] Debug signal 0 Debug signal 1 Debug signal 2 Debug signal 3 Debug signal 4 Debug signal 5 Debug signal 6 Debug signal 7 Debug signal 8 Debug signal 9 Debug signal 10 Debug signal 11 Debug signal 12 TYPE [3] O O O O O O O O O O O O O ZCN BALL [4] AD2,AD17 AD1,AE18 AD3,AD18 AE3,AC18 AC5,AB18 AD5,AA18 Y18,AE5 Y6,AE19 Y7,AD19 AA7,AB19 AC7,AE20 AD7,AD20 AE23,AC20 ZER BALL [4] G22 G21 G20 F22 F20 G19 E19 F21 F19 E21 D22 D21 E22 TERMINAL DESCRIPTION Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 71
AM3517, AM3505
Table 2-23. Test Interfaces HWDBG Signals Description (continued)

SIGNAL NAME [1] hw_dbg13 hw_dbg14 hw_dbg15 hw_dbg16 hw_dbg17 DESCRIPTION [2] Debug signal 13 Debug signal 14 Debug signal 15 Debug signal 16 Debug signal 17 TYPE [3] O O O O O ZCN BALL [4] AD22,AB20 AB25,AE21 AA23,AD21 AA24,AC21 AA25,AE22 ZER BALL [4] E20 E18 D20 D19 D18
2.4.6
Miscellaneous
Table 2-24. Miscellaneous GP Timer Signals Description
SIGNAL NAME [1] gpt8_pwm_evt gpt9_pwm_evt gpt10_pwm_evt gpt11_pwm_evt
DESCRIPTION [2] PWM or event for GP timer 8 PWM or event for GP timer 9 PWM or event for GP timer 10 PWM or event for GP timer 11
TYPE [3] IO IO IO IO
ZCN BALL [4] N4,E23,AE17 M4,M2,F20,AC16 M3,M1,F19,AB16 N5,E24,AA16
ZER BALL [4] V11,C6,H19 Y12,AA11,A5,H20 V12,W12,B5,H22 AA12,D6,H21
72
AM3517, AM3505
2.4.7
General-Purpose IOs
Table 2-25. General-Purpose IOs Signals Description
SIGNAL NAME [1] gpio_0 gpio_1 gpio_2 gpio_3 gpio_4 gpio_5 gpio_6 gpio_7 gpio_8 gpio_10 gpio_11 gpio_12 gpio_13 gpio_14 gpio_15 gpio_16 gpio_17 gpio_18 gpio_19 gpio_20 gpio_21 gpio_22 gpio_23 gpio_24 gpio_25 gpio_26 gpio_27 gpio_28 gpio_29 gpio_30 gpio_31 gpio_34 gpio_35 gpio_36 gpio_37 gpio_38 gpio_39 gpio_40 gpio_41 gpio_42 gpio_43 gpio_44 gpio_45 gpio_46 gpio_47
DESCRIPTION [2] General-purpose IO 0 General-purpose IO 1 General-purpose IO 2 General-purpose IO 3 General-purpose IO 4 General-purpose IO 5 General-purpose IO 6 General-purpose IO 7 General-purpose IO 8 General-purpose IO 10 General-purpose IO 11 General-purpose IO 12 General-purpose IO 13 General-purpose IO 14 General-purpose IO 15 General-purpose IO 16 General-purpose IO 17 General-purpose IO 18 General-purpose IO 19 General-purpose IO 20 General-purpose IO 21 General-purpose IO 22 General-purpose IO 23 General-purpose IO 24 General-purpose IO 25 General-purpose IO 26 General-purpose IO 27 General-purpose IO 28 General-purpose IO 29 General-purpose IO 30 General-purpose IO 31 General-purpose IO 34 General-purpose IO 35 General-purpose IO 36 General-purpose IO 37 General-purpose IO 38 General-purpose IO 39 General-purpose IO 40 General-purpose IO 41 General-purpose IO 42 General-purpose IO 43 General-purpose IO 44 General-purpose IO 45 General-purpose IO 46 General-purpose IO 47
TYPE [3] IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
ZCN BALL [4] Y1 M24 Y4 AA1 AA2 AA3 AB1 AB2 AC1 N25 T25 AD17 AE18 AD18 AC18 AB18 AA18 Y18 AE19 AD19 AB19 AE20 AD20 AC20 AB20 AE21 AD21 AC21 AE22 Y3 R24 E3 E2 E1 F7 F6 F4 F3 F2 F1 G6 J4 J3 J2 J1
ZER BALL [4] AB18 B8 AB19 AB20 W18 AA19 V18 Y19 W19 E9 E13 G22 G21 G20 F22 F20 G19 E19 F21 F19 E21 D22 D21 E22 E20 E18 D20 D19 D18 Y18 E12 W5 Y5 AB4 AA5 AB5 AB6 AA6 W6 AB7 Y6 W10 AB9 AB10 W9
73
AM3517, AM3505
Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME [1] gpio_48 gpio_49 gpio_50 gpio_51 gpio_52 gpio_53 gpio_54 gpio_55 gpio_56 gpio_57 gpio_58 gpio_59 gpio_60 gpio_61 gpio_62 gpio_63 gpio_64 gpio_65 gpio_66 gpio_67 gpio_68 gpio_69 gpio_70 gpio_71 gpio_72 gpio_73 gpio_74 gpio_75 gpio_76 gpio_77 gpio_78 gpio_79 gpio_80 gpio_81 gpio_82 gpio_83 gpio_84 gpio_85 gpio_86 gpio_87 gpio_88 gpio_89 gpio_90 gpio_91 gpio_92 gpio_93 gpio_94 DESCRIPTION [2] General-purpose IO 48 General-purpose IO 49 General-purpose IO 50 General-purpose IO 51 General-purpose IO 52 General-purpose IO 53 General-purpose IO 54 General-purpose IO 55 General-purpose IO 56 General-purpose IO 57 General-purpose IO 58 General-purpose IO 59 General-purpose IO 60 General-purpose IO 61 General-purpose IO 62 General-purpose IO 63 General-purpose IO 64 General-purpose IO 65 General-purpose IO 66 General-purpose IO 67 General-purpose IO 68 General-purpose IO 69 General-purpose IO 70 General-purpose IO 71 General-purpose IO 72 General-purpose IO 73 General-purpose IO 74 General-purpose IO 75 General-purpose IO 76 General-purpose IO 77 General-purpose IO 78 General-purpose IO 79 General-purpose IO 80 General-purpose IO 81 General-purpose IO 82 General-purpose IO 83 General-purpose IO 84 General-purpose IO 85 General-purpose IO 86 General-purpose IO 87 General-purpose IO 88 General-purpose IO 89 General-purpose IO 90 General-purpose IO 91 General-purpose IO 92 General-purpose IO 93 General-purpose IO 94 TYPE [3] IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO ZCN BALL [4] K4 K3 K2 K1 L1 M4 M3 M2 M1 N5 N4 N1 R4 T1 T2 T4 T5 U1 AE23 AD22 AD23 AE24 AD24 AD25 AC23 AC24 AC25 AB24 AB25 AA23 AA24 AA25 Y22 Y23 Y24 Y25 W21 W22 W23 W24 W25 V24 V25 U21 U22 U23 AD2 ZER BALL [4] AA10 Y9 V10 V9 Y11 Y12 V12 AA11 W12 AA12 V11 AB13 W11 Y15 W14 AA16 Y14 V14 B22 B21 B20 B19 A20 A19 A18 B18 A17 C18 D17 B16 B17 C17 C16 D16 D14 A16 D15 B15 A15 A14 C13 C15 A13 B13 C14 B14 AB21
74
AM3517, AM3505

SIGNAL NAME [1] gpio_95 gpio_96 gpio_97 gpio_98 gpio_99 gpio_100 gpio_101 gpio_102 gpio_103 gpio_104 gpio_105 gpio_106 gpio_107 gpio_108 gpio_109 gpio_110 gpio_111 gpio_112 gpio_113 gpio_114 gpio_116 gpio_117 gpio_118 gpio_119 gpio_120 gpio_121 gpio_122 gpio_123 gpio_124 gpio_125 gpio_126 gpio_127 gpio_128 gpio_129 gpio_130 gpio_131 gpio_132 gpio_133 gpio_134 gpio_135 gpio_136 gpio_137 gpio_138 gpio_139 gpio_140 gpio_141 gpio_142 DESCRIPTION [2] General-purpose IO 95 General-purpose IO 96 General-purpose IO 97 General-purpose IO 98 General-purpose IO 99 General-purpose IO 100 General-purpose IO 101 General-purpose IO 102 General-purpose IO 103 General-purpose IO 104 General-purpose IO 105 General-purpose IO 106 General-purpose IO 107 General-purpose IO 108 General-purpose IO 109 General-purpose IO 110 General-purpose IO 111 General-purpose IO 112 General-purpose IO 113 General-purpose IO 114 General-purpose IO 116 General-purpose IO 117 General-purpose IO 118 General-purpose IO 119 General-purpose IO 120 General-purpose IO 121 General-purpose IO 122 General-purpose IO 123 General-purpose IO 124 General-purpose IO 125 General-purpose IO 126 General-purpose IO 127 General-purpose IO 128 General-purpose IO 129 General-purpose IO 130 General-purpose IO 131 General-purpose IO 132 General-purpose IO 133 General-purpose IO 134 General-purpose IO 135 General-purpose IO 136 General-purpose IO 137 General-purpose IO 138 General-purpose IO 139 General-purpose IO 140 General-purpose IO 141 General-purpose IO 142 TYPE [3] IO IO IO IO I I IO IO IO IO IO IO IO IO IO IO IO I I I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO ZCN BALL [4] AD1 AE2 AD3 AE3 AD4 AE4 AC5 AD5 AE5 Y6 AB6 AC6 AE6 AD6 Y7 AA7 AB7 AE7 AD8 AE8 D25 C25 B25 D24 AA9 AB9 AC9 AD9 AE9 AA10 AB10 AC10 AD10 AE10 AD11 AE11 AB12 AC12 AD12 AE12 AB13 AC13 AD13 AE13 B24 C24 A24 ZER BALL [4] AA21 Y21 Y22 W21 W22 W20 V21 V19 V22 U20 V20 U19 U21 U22 T19 T20 T21 R20 R19 R21 E5 D5 C5 E4 P22 N21 P21 N20 P19 P20 N22 N19 N18 P18 M21 M20 K20 L19 M18 K21 L18 L20 L21 M19 C4 B4 D4
75
AM3517, AM3505

SIGNAL NAME [1] gpio_143 gpio_144 gpio_145 gpio_146 gpio_147 gpio_148 gpio_149 gpio_150 gpio_151 gpio_152 gpio_153 gpio_154 gpio_155 gpio_156 gpio_157 gpio_158 gpio_159 gpio_160 gpio_161 gpio_162 gpio_163 gpio_164 gpio_165 gpio_166 gpio_167 gpio_168 gpio_170 gpio_171 gpio_172 gpio_173 gpio_174 gpio_175 gpio_176 gpio_177 gpio_178 gpio_179 gpio_180 gpio_181 gpio_182 gpio_183 gpio_184 gpio_185 gpio_186 DESCRIPTION [2] General-purpose IO 143 General-purpose IO 144 General-purpose IO 145 General-purpose IO 146 General-purpose IO 147 General-purpose IO 148 General-purpose IO 149 General-purpose IO 150 General-purpose IO 151 General-purpose IO 152 General-purpose IO 153 General-purpose IO 154 General-purpose IO 155 General-purpose IO 156 General-purpose IO 157 General-purpose IO 158 General-purpose IO 159 General-purpose IO 160 General-purpose IO 161 General-purpose IO 162 General-purpose IO 163 General-purpose IO 164 General-purpose IO 165 General-purpose IO 166 General-purpose IO 167 General-purpose IO 168 General-purpose IO 170 General-purpose IO 171 General-purpose IO 172 General-purpose IO 173 General-purpose IO 174 General-purpose IO 175 General-purpose IO 176 General-purpose IO 177 General-purpose IO 178 General-purpose IO 179 General-purpose IO 180 General-purpose IO 181 General-purpose IO 182 General-purpose IO 183 General-purpose IO 184 General-purpose IO 185 General-purpose IO 186 TYPE [3] IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO ZCN BALL [4] C23 F20 F19 E24 E23 AA19 Y19 Y20 W20 B23 A23 B22 A22 R25 P21 P22 P23 P25 P24 N24 N2 N3 P1 P2 AC7 W1 L25 AE14 AD15 AC15 AB15 AD14 AE15 AE16 AD16 AC16 AB16 AA16 AE17 W2 W4 W5 M25 ZER BALL [4] A4 A5 B5 D6 C6 C22 C21 C19 C20 A3 B3 A2 B2 B11 D11 C10 C9 E11 C11 C8 W15 W13 AA13 Y13 R22 Y17 B9 K22 K19 J18 K18 J20 J19 J21 J22 H20 H22 H21 H19 Y16 W16 W17 E10
76
AM3517, AM3505
2.4.8
System and Miscellaneous Terminals

Table 2-26. System and Miscellaneous Signals Description
SIGNAL NAME [1] sys_32k sys_xtalin sys_xtalout sys_altclk
DESCRIPTION [2] 32-kHz clock input Main input clock. Oscillator input Output of oscillator Alternate clock source selectable for GPTIMERs (maximum 54 MHz), USB (48 MHz) , or NTSC/PAL (54 MHz) Request from device for system clock (open source type) Configurable output clock1 Configurable output clock2 Boot configuration mode bit 0 Boot configuration mode bit 1 Boot configuration mode bit 2 Boot configuration mode bit 3 Boot configuration mode bit 4 Boot configuration mode bit 5 Boot configuration mode bit 6 Boot configuration mode bit 7 Boot configuration mode bit 8 Power On Reset Warm Boot Reset (open drain output) External FIQ input External DMA request 0 (system expansion). Level (active low) or edge (falling) selectable. External DMA request 1 (system expansion). Level (active low) or edge (falling) selectable. External DMA request 2 (system expansion). Level (active low) or edge (falling) selectable. External DMA request 3 (system expansion). Level (active low) or edge (falling) selectable.
TYPE [3] I I O I
ZCN BALL [4] K24 K25 H25 L25
ZER BALL [4] A8 A10 A9 B9
sys_clkreq sys_clkout1 sys_clkout2 sys_boot0 sys_boot1 sys_boot2 sys_boot3 sys_boot4 sys_boot5 sys_boot6 sys_boot7 sys_boot8 sys_nrespwron sys_nreswarm sys_nirq sys_ndmareq0
IO O O I I I I I I I I I I IOD I I
M24 N25 M25 Y4 AA1 AA2 AA3 AB1 AB2 AC1 AC2 AC3 Y2 Y3 Y1 M3
B8 E9 E10 AB19 AB20 W18 AA19 V18 Y19 W19 AA20 Y20 AA18 Y18 AB18 V12
sys_ndmareq1
M2,U1
AA11,V14
sys_ndmareq2
F1,M1
W12,AB7
sys_ndmareq3
G6,N5
AA12,V6
77
AM3517, AM3505
2.4.9
Power Supplies
Table 2-27. Power Supplies Description
SIGNAL NAME[1]
DESCRIPTION[2]
BALL (ZCN Pkg.) [4] V16, V15, V11, V10, U16, U15, U11, U10, T18, T17, T9, T8, R18, R17, R9, R8, M18, L18, L9, L8, K18, K17, K9, K8, J16, J15, J11, J10, H15, H11, H10 AE25, AE1, V18, V17, V14, V13, V12, V9, V8, U18, U17, U14, U13, U12, U9, U8, T14, T13, T12, R16, R15, R14, R13, R12, R11, R10, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, N18, N17, N14, N13, N12, N9, N8, M17, M16, M15, M14, M13,M12, M11, M10, M9, M8, L17, L16, L15, L14, L13, L12, L11, L10, K14, K13, K12, J18, J17, J14, J13, J12, J9, J8, H14, H13, H12, H9, A25, A1, N23, G20, G21 AA13 E17 AA12
BALL (ZER Pkg.) [4]
VDD_CORE
1.2-V core and oscillator macros power supply.
J8,J10, J12, J14, J16, K9, K11, K13, K15, L8, L10, L12, L14, M7, M9, M11, M13, M15, N8, N10, N12, N14, P7, P9, P11, P13, P15, R8, R10, R12, R14
VSS
Core and I/O common ground.
A1, A11,A22, E6, E16, F6, F13, F15, F17, G5, G7, G11, G14, G16, G18, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, J9, J11, J13, J15, K8, K10, K12, K14, K16, L7, L9, L11, L13, L15, M1, M6, M8, M10, M12, M14, M16, M22, N7, N9, N11, N13, N15, N17, P6, P8, P10, P12, P14, P16, R5, R7, R9, R11, R13, R15, R17, T6, T8, T10, T12, T14, T16, T18, U5, U7, U9, U11, U13, U15, U17, V6, AB1, AB12, AB22
VDDS_SRAM_MPU VDDS_SRAM_CORE_BG CAP_VDD_SRAM_MPU
1.8-V MPU SLDO analog power supply. 1.8-V Core SLDO and VDDA of BandGap analog power supply. 1.2-V SRAMOUT for MPU SLDO. For proper device operation, connect to a 1F decoupling capacitor. 1.2-V SRAMOUT for Core SLDO. For proper device operation, connect to a 1F decoupling capacitor. 1.8-V MPUSS DPLL and USBHOST DPLL analog power supply. 1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply. 1.8-V DAC analog power supply. DAC analog ground. 3.3-V USB transceiver analog power supply. 1.8-V USB transceiver power supply. Output of the 1.2-V internal LDO. For proper device operation, connect a 0.22uF capacitor between this pin and VSSA.
L17 J6 M17
CAP_VDD_SRAM_CORE VDDS_DPLL_MPU_USBH OST VDDS_DPLL_PER_CORE VDDA_DAC VSSA_DAC VDDA3P3V_USBPHY VDDA1P8V_USBPHY CAP_VDDA1P2LDO_USB PHY
E16 AA15 N20 H21 H22 F23 G22 F22
K6 K17 F11 NA NA F7 D7 E7
78
AM3517, AM3505
Table 2-27. Power Supplies Description (continued)

SIGNAL NAME[1] DESCRIPTION[2] BALL (ZCN Pkg.) [4] Y16, Y15, Y13, Y12, Y10, W16, W15, W13, W12,W10, W9, W6, V7, V6, U19, T20, T19, T7, T6, R7, R6, P20, P19, N19, N7, N6, M7, M6, M5, L19, K19, K7, K6, K5, J7, H18, H17 Y9, W18, U20, R5, H16, H8, G17, G16, G14, G13, G11, G10, G8, F16, F13, F11, F10, F8 L20 J25 BALL (ZER Pkg.) [4]
VDDSHV
1.8/3.3-V power supply.
A21, B1,E15, E17, F12, F14, F18, G10, G12, G13, G8, G17, H18, J17, L22, N16, P17, R16, R18, T9, T11, T13, T17, U8, U10, U12, U14, U16, U18, V7, V8, V17, AA22, AB11
VDDS
1.8-V power supply.
F5, F16, G9, G15, H5, K7, L6, L16, N1, N5, N6, P5, R6, T5, T7, T15, U6, AA1 G9 B10
VDDSOSC VSSOSC
1.8-V oscillator power supply. Oscillator ground.
79
AM3517, AM3505
3 ELECTRICAL CHARACTERISTICS
3.1 Absolute Maximum Ratings
The following table specifies the absolute maximum ratings over the operating junction temperature range of commercial and extended temperature devices. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Notes: Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions. Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range
PARAMETER VDD_CORE VDDS VDDSHV VDDS_SRAM_MPU Supply voltage range for core macros Second supply voltage range for 1.8-V I/O macros Supply voltage range for 1.8/3.3V I/O macros Analog Supply voltage range for 1.8-V MPU SLDO MIN -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.3 -0.3 -0.3 -0.3 MAX 1.6 2.25 3.8 2.25 2.25 2.1 2.1 2.43 3.6 2.0 2.1 VDDSOSC + 0.3 VDDS + 0.3 VDDSHV + 0.3 3.8 5.5 5.25 >1000 >500 200 -20 -65 20 150 mA mA C V UNIT V V V V V V V V V V V V
VDDS_SRAM_CORE_BG Analog Supply voltage range for 1.8-V Core SLDO and VDDA of BandGap VDDS_DPLL_MPU_USB HOST VDDS_DPLL_PER_COR E VDDA_DAC VDDA3P3V_USBPHY VDDA1P8V_USBPHY VDDSOSC VPAD Analog power supply for 1.8-V MPUSS DPLL and USBHOST DPLL Analog power supply for 1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER Analog Power Supply for 1.8-V DAC Analog power supply for 3.3-V USB transceiver Power Supply for 1.8-V USB transceiver Power Supply for 1.8-V oscillator Voltage range at PAD Oscillator input (sys_xtalin) VDDS 1.8-V I/O macros Dual-voltage LVCMOS inputs, VDDSHV = 1.8 V Dual-voltage LVCMOS inputs, VDDSHV = 3.3 V USB VBUS pin (usb0_vbus) USB 5V Tolerant IOs (usb0_dp, usb0_dm, usb0_id) VESD ESD stress voltage (1) HBM (human body model) (2) CDM (charged device model) (3) IIOI Iclamp Tstg (1) (2) (3) (4) Current-pulse injection on each I/O pin (4) Clamp current for an input or output Storage temperature range
Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. The level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary precautions are taken. Actual performance of the device may exceed the value listed above. The level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. Actual performance of the device may exceed the value listed above. Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.
80
ELECTRICAL CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
The supply voltages and power consumption estimates are detailed in Table 3-2. Table 3-2. Estimated Power Consumption at Ball Level
SIGNAL NAME VDD_CORE VDDS_SRAM_MPU VDDS_DPLL_MPU_USB HOST VDDS_DPLL_PER_COR E VDDA_DAC VDDA3P3V_USBPHY VDDA1P8V_USBPHY VDDSHV VDDS VDDSOSC DESCRIPTION 1.2-V core and oscillator macros power supply 1.8-V MPU SLDO analog power supply 1.8-V MPUSS DPLL and USBHOST DPLL analog power supply 1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply 1.8-V DAC analog power supply 3.3-V USB transceiver analog power supply 1.8-V USB transceiver power supply 3.3-/1.8--V power supply 1.8-V power supply 1.8-V oscillator power supply AM3517 AM3505 VDDS_SRAM_CORE_BG 1.8-V Core SLDO and VDDA of BandGap analog power supply MAX CURRENT (mA) 1500 mA 1400 mA 40 mA 40 mA 25 mA 25 mA 65 mA 10 mA 50 mA 300 mA 200 mA 20 mA
81
AM3517, AM3505
3.2
Recommended Operating Conditions

All AM3517/05 modules are used under the operating conditions contained in Table 3-3. Note: Logic functions and parameter values are not assured if the device is operated out of the range specified in the recommended operating conditions. Table 3-3. Recommended Operating Conditions
PARAMETER VDD_CORE VDDS_SRAM_ MPU VDDS_SRAM_ CORE_BG VDDS_DPLL_ MPU_ USBHOST VDDS_DPLL_ PER_CORE VDDA_DAC VSSA_DAC VDDA3P3V_ USBPHY VDDA1P8V_ USBPHY VDDSHV VDDS Tj
DESCRIPTION Core and oscillator macros power supply Noise (peak-peak) MPU SRAM LDO analog power supply Noise (peak-peak) Core SRAM LDO and BandGap analog power supply Noise (peak-peak) MPU and USBHOST DPLL analog power supply Noise (peak-peak)
MIN 1.152 1.71 1.71
NOM 1.20 1.80 1.80
MAX 1.248 24.00 1.89 50.00 1.89 50.00
UNIT V mVpp V mVpp V mVpp V mVpp V mVpp V mVpp V V mVpp V mVpp V V V C C hrs.
1.71
1.80
1.89 35.00
Peripherals and Core DPLLs analog power supply 1.71 Noise (peak-peak) DAC analog power supply Noise (peak-peak) DAC analog ground Analog power supply for 3.3-V USB transceiver Noise (peak-peak) Power Supply for 1.8-V USB transceiver Noise (peak-peak) 3.3-/1.8-V power supply 1.8-V power supply Operating junction temperature range Commercial Temperature Extended Temperature 1.8 V Mode 3.3 V Mode 1.71 3.14 1.71 0 -40 1.71 3.14 1.71
1.80 1.80 0.00 3.30 1.80 1.80 3.30 1.80
1.89 35.00 1.89 30.00 3.47 70.00 1.89 50.00 1.89 3.47 1.89 90 105
Device Operating Life Power-On Hours (POH) (1) (1) (2)
500 MHz ARM Clock Freq. 600 MHz ARM Clock Freq.
< 90C TJ 90 - 105 C TJ < 90C TJ 90 - 105 C TJ
100K 100K 100K 50K (2)
The POH information is provided solely for your convenience and does not extend or modify the warranty provided under TIs standard terms and conditions for TI semiconductor products. Maximum lifetime will be 100k Power On Hours as long as no more than 50k is greater than 90C.
82
AM3517, AM3505
The following diagram illustrates the power domains:
vdds_dpll_mpu_usbhost
BandGap
DLL/DCDL
LDO3 1.0 V/1.2 V
VDDSHV
vddshv
BCK MEM
LDO in 1.8 V out 1.2 V
MPU
VDDS
vdds
DPLL_MPU
vdd_core
Core
DPLL_CORE
SRAM 1 LDO 0 V/1.0 V/1.2 V
SRAM1 ARRAY
LDO HSDIVIDER
tv_ref
(for capacitor)
vdds_dpll_per_core vdda_dac
Dual Video DAC
SRAM 2 LDO 0 V/1.0 V/1.2 V
SRAM2 ARRAY
cap_vdd_sram_core
Periph1
DPLL4
LDO HSDIVIDER
vss vssa_dac
Periph2
DPLL5
vdd_core domain
Device
030-003
Figure 3-1. AM3517/05 Voltage Domains
83
AM3517, AM3505
3.3
DC Electrical Characteristics
Table 3-4 summarizes the dc electrical characteristics. Table 3-4. DC Electrical Characteristics
PARAMETER LVCMOS Pin Buffers VIH High-level input voltage VDDSHV = 1.8 V
(1)
MIN
NOM
MAX
UNIT
0.65 x VDDSHV. 2 0.8 x VDDSOSC 0.35 x VDDSHV 0.8 0.2 x VDDSOSC VDDSHV 0.45 2.4 0.45 0.4 -9 -310 9 -70
VDDSHV = 3.3 V(1) sys_xtalin VIL Low-level input voltage VDDSHV = 1.8 V(1) VDDSHV = 3.3 V(1) sys_xtalin VOH High-level output voltage VDDSHV = 1.8 V(1) IOH = -2 mA VDDSHV = 3.3 V(1) IOH = -2 mA VOL Low-level output voltage VDDSHV = 1.8 V(1) IOL = 2 mA VDDSHV = 3.3 V(1) IOL = 2 mA II Input current for dual voltage IO pins VI = Vss to VDDSHV VI = Vss to VDDSHV VI = Vss to VDDSHV Input current for DDR2/mDDR 1.8V IO pins IOZ IOH IOL tT Off-state output current High-level output current (dual-voltage LVCMOS IOs) Low-level output current (dual-voltage LVCMOS IOs) Input transition time (rise time, tR or fall time, tF evaluated between 10% and 90% at PAD) VDDSHV = 1.8 Normal mode V(1) High-speed mode VDDSHV = 3.3 Normal mode V(1) High-speed mode Capacitan ce Input capacitance (dual-voltage LVCMOS I/Os) Output capacitance (dual-voltage LVCMOS I/Os) VI = Vss to VDDSHV VO = VDDSHV or 0V Input pins with pull disabled Input pins with 100 A pull-up enabled Input pins with 100 A pull-down enabled Input pins with 100 A pull-down enabled Pull disabled
75
270
77
286
-20
20 -2 2 10 3 10 3 3 3
A mA mA ns
pF pF
Complex IO Dedicated to USB : USB0_DM and USB0_DP VIH

(2)
High-level input voltage
Low/Full speed High speed
2.0
VIL
Low-level input voltage
0.8
(2)
VOH
High-level output voltage
2.8 360
VDDA3P3V_ USBPHY 440
V mV
(1) (2) 84
These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR interfaces. DDR2/mDDR IOs are 1.8V IOs and adhere to the JESD79-2A standard. These parameters must adhere to the requirements defined in section 7.1.7.2 of Universal Serial Bus Specifications revision 2.0. ELECTRICAL CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Table 3-4. DC Electrical Characteristics (continued)

PARAMETER VOL Low-level output voltage Low/Full speed High speed 0.0 -10 MIN NOM 0.3 10 MAX V mV UNIT
85
AM3517, AM3505
3.4
Core Voltage Decoupling

For module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device because this minimizes the inductance of the circuit board wiring and interconnects. Table 3-5 summarizes the power supplies decoupling characteristics. Table 3-5. Core Voltage Decoupling Characteristics
PARAMETER MIN 50 TYP 100 100 100 100 100 100 100 100 100 100 100 MAX 120 UNIT nF nF nF nF nF nF nF nF nF nF nF
Cvdd_core
(1)
Ccap_vdd_sram_core Cvdds_dpll_mpu_usbhost Cvdds_dpll_per_core Cvdda_dac Cvdd_sram_core Cvdd_sram_core_bg Cvdds_sram_mpu Cvddshv Cvdda3p3v_usbphy Cvdda1p8v_usbphy (1) 1 capacitor per 2 to 4 balls
86
AM3517, AM3505
The following illustrates an example of power supply decoupling.

Device
vdda_dac Cvdda_dac vdds_sram_mpu vdds_sram_mpu Cvdds_sram_mpu
vdda_dac vssa_dac
Video DAC SRAM_LDO1
cap_vdd_sram_mpu Ccap_vdd_sram_mpu vdds_sram_core_bg vdds_sram_core_bg Cvdds_sram_core_bg vdd_sram_core Cvdd_sram_core
SRAM_LDO2
vdd_sram_core
WKUP_LDO
cap_vdd_sram _core Ccap_vdd_sram_core
BG
DPLL_MPU
vdds_dpll_mpu _usbhost
vdds_dpll_mpu_usbhost Cvdds_dpll_mpu_usbhost
DPLL_CORE
vdds_dpll_per_core Cvdds_dpll_per_core
DPLL5
vdds_dpll_per_core
DPLL4
Vdd_core vdd_core Cvdd_core VSS
030-004
Core MPU
(1)
(2)
Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers. The decoupling capacitor value depends on the board characteristics.
Figure 3-2. Power Supply Decoupling
87
AM3517, AM3505
3.5
Power-up and Power-down

This section provides the timing requirements for the AM3517/05 hardware signals.
3.5.1
Power-up Sequence
The following steps give an example of power-up sequence supported by the AM3517/05 . 1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) and oscillator supply (VDDSOSC) should come up first to a stable state. 2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state. 3. Core (VDD_CORE) supply follows next to a stable state. 4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state. 5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up. 6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the sys_32k and sys_xtalin clocks are stable. Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.
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AM3517, AM3505
Figure 3-3 shows the power-up sequence.
VDDS, VDDS_SRAM_CORE_BG VDDS_SRAM_MPU, VDDSOSC
1.8V
VDDSHV
3.3V
VDD_CORE
1.2V
sys_nrespwron
sys_32k
sys_xtalin
VDDS_DPLL_PER_CORE , VDDS_DPLL_MPU_USBHOST, VDDA_DAC, VDDA1P8V_USBPHY
1.8V
VDDA3P3V_USBPHY
3.3V
Figure 3-3. Power-up Sequence
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AM3517, AM3505
3.5.2
Power-down Sequence
The AM3517/05 device proceeds with the power-down sequence shown below. The following steps give an example of the power-down sequence supported by the AM3517/05 device. 1. Reset AM3517/05 device. 2. Stop all signals driven to AM3517/05 . 3. Option 1: Power down all domains simutaneously. 4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence: (a) Power off all complex I/O domains (b) Power off core domain (VDD_CORE) (c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE) (d) Power off all SRAM LDOs (e) Power off all standard I/O domains (VDDS and VDDSHV)
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AM3517, AM3505
4 CLOCK SPECIFICATIONS
The AM3517/05 device has three external input clocks, a low frequency (sys_32k), a high frequency (sys_xtalin), and an optional (sys_altclk). The AM3517/05 device has two configurable output clocks, sys_clkout1 and sys_clkout2. Figure 4-1 shows the interface to the external clock sources and clock outputs.
Microprocessor sys_32k Power IC Alternate Clock Source Selectable (54, 48 MHz or other [up to 59 MHz]) Ethernet input 50-MHz clock To Peripherals (From OSC_CLK: 26 MHz) To Peripherals (From OSC_CLK: 26 MHz, core_clk [DPLL, up to 166 MHz], DPLL-96 MHZ or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16) To Quartz (Oscillator output) or Unconnected
sys_altclk rmii_50mhz_clk sys_clkout1 sys_clkout2
sys_xtalout
sys_xtalin sys_clkreq sys_xtalout Oscillator is Used sys_xtalin
From Quartz (Oscillator input), Square Clock, or Crystal Clock Request. To Square Clock Source or from Peripherals sys_xtalout Unconnected Oscillator is Bypassed sys_xtalin Square Clock Source
sys_clkreq
GPin
sys_clkreq
Figure 4-1. Clock Interface The AM3517/05 device operation requires the following three input clocks: The 32-kHz clock can be generated using one of the following options and can be selected via the sys_boot7 pin. See Figure 4-2. External: Supplied by an oscillator on the sys_32k pin. Internal: 32-kHz clock generation using a fixed divider on the HS system clock (26MHz). The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54 MHz or other clock source (up to 54 MHz). The system clock input (26 MHz) is used to generate the main source clock of the AM3517/05 device. It supplies the DPLLs as well as several AM3517/05 modules. The system clock input can be connected to either: A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is used as an input (GPIN). A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to request the external system clock.
CLOCK SPECIFICATIONS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
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AM3517, AM3505
0 Sys_32k_in 1 32.5 kHz Fixed Divider /800 Sys_clk= 26 MHz
Sys_32k
Sys_xtalin
Sys_xtalout 0 1 JTAG Overrides for DFT 1 Sys_clk PowerOn Reset Latch Sys_boot7
Figure 4-2. 32-kHz Clock Generation The AM3517/05 outputs externally two clocks: sys_clkout1 can output the oscillator clock (26 MHz) at any time. sys_clkout2 can output the oscillator clock, core_clk, 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable.
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4.1
Oscillator
The sys_xtalin (26 MHz) oscillator provides the primary reference clock for the device. The on-chip oscillator requires an external crystal connected across the sys_xtalin and sys_xtalout pins, along with two load capacitors, as shown in Figure 4-3. The external crystal load capacitors must be connected only to the oscillator ground pin (VSSOSC). Do not connect to board ground (VSS). Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the sys_xtalin pin with a 1.8V amplitude. The sys_xtalout should be left unconnected and the VSSOSC signal should be connected to board ground (VSS).
sys_xtalin
sys_xtalout
VSSOSC
Crystal 26 MHz
C1
C2
Figure 4-3. AM3517/05 Oscillator Connections The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (sys_xtalin and sys_xtalout) and to the VSS pin.
CL= C1C2 / (C1 + C2) (1)
Table 4-1. Crystal Electrical Characteristics

PARAMETER Oscillation frequency Crystal ESR Frequency stability Parallel Load Capacitance (C1 and C2) Shunt Capacitance MIN TYP 26 50 +/- 50 20 5 MAX UNIT MHz ppm pF pF
4.2
Input Clock Specifications

The clock system accepts three input clock sources: 32-kHz digital CMOS clock Crystal oscillator clock or CMOS digital clock (26 MHz) Alternate clock (48 or 54 MHz, or other up to 54 MHz) Table 4-2. 26Mhz sys_clk Input Clock Timing Requirements
PARAMETER f(xtalin) tw(xtalin) tj(xtalin)
DESCRIPTION Frequency, sys_xtalin Duty Cycle, sys_xtalin Jitter, sys_xtalin
MIN 45 -1
TYP 26
MAX 55 1
UNIT MHz % % CLOCK SPECIFICATIONS 93
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Table 4-2. 26Mhz sys_clk Input Clock Timing Requirements (continued)

PARAMETER tt(xtalin) DESCRIPTION Transition time, sys_xtalin MIN TYP MAX 5 UNIT ns
Table 4-3. 32-kHz Input Clock Source Electrical Characteristics

PARAMET ER f Ci Ri DESCRIPTION Frequency, sys_32k Input capacitance Input resistance 0.25 MIN TYP 32.768 0.45 10
6
MAX
UNIT kHz pF G
Table 4-4 details the input requirements of the 32-kHz input clock. Table 4-4. 32-kHz Input Clock Source Timing Requirements (1)
PARAMETE R 1 / tc(32k) tR(32k) tF(32k) tJ(32k) (1) Frequency, sys_32k Rise transition time, sys_32k Fall transition time, sys_32k Frequency stability, sys_32k DESCRIPTION MIN TYP 32 20 20 +/-200 MAX UNIT kHz ns ns ppm
See Electrical Characteristics for Standard LVCMOS IOs part for sys_32k VIH/VIL parameters.
Table 4-5. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Electrical Characteristics
NAME f Ci Ri DESCRIPTION Frequency , sys_altclk Input capacitance Input resistance 0.25 MIN 48, 54, or up to 59 0.74 106 MAX UNIT MHz pF G
Table 4-6 details the input requirements of the 48- or 54-MHz input clock. Table 4-6. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Timing Requirements (1)
PARAMETER 1 / tc(sys_altclk) tw(sys_altclk) tj(sys_altclk) tr(sys_altclk) tf(sys_altclk) ft(sys_altclk) (1) (2) Duty cycle Jitter Rise transition time Fall transition time Frequency tolerance -50 DESCRIPTION Frequency, sys_altclk 45 -1 MIN 48, 54, or up to 59 60 1 10 10 50 MAX
(2)
UNIT MHz % % ns ns ppm
Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300 period samples. The sinusoidal noise is added on top of the vdds supply voltage. See Section 3, Electrical Characteristics, for sys_altclk VIH/VIL parameters.
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AM3517, AM3505
4.3
Output Clock Specifications

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available: sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity of sys_clkout1 is programmable. sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active only when the core domain is active. Table 4-7 summarizes the sys_clkout1 output clock electrical characteristics. Table 4-7. sys_clkout1 Output Clock Electrical Characteristics
NAME f CI (1) Frequency
DESCRIPTION Load capacitance (1) f(max) = 38.4 MHz f(max) = 26 MHz
MIN
TYP 26 70 125
MAX
UNIT MHz pF
The load capacitance is adapted to a frequency.
Table 4-8 details the sys_clkout1 output clock timing characteristics. Table 4-8. sys_clkout1 Output Clock Switching Characteristics
NAME f CO1 CO2 CO3 (1) 1 / CO0 tw(CLKOUT1) tR(CLKOUT1) tF(CLKOUT1) DESCRIPTION Frequency Pulse duration, sys_clkout1 low or high Rise time, sys_clkout1 (1) Fall time, sys_clkout1 (1) 0.40 * tc(CLKOUT1) MIN TYP 26 0.60 * tc(CLKOUT1) 3.31 3.31 MAX UNIT MHz ns ns ns
With a load capacitance of 25 pF.
CO0 sys_clkout1
CO1
CO1
030-014
Figure 4-4. sys_clkout1 System Output Clock Table 4-9 summarizes the sys_clkout2 output clock electrical characteristics. Table 4-9. sys_clkout2 Output Clock Electrical Characteristics
NAME f CL (1) (2) DESCRIPTION Frequency, sys_clkout2 Load capacitance (2)
(1)
MIN f(max) = 166 MHz 2
TYP 8
MAX 166 12
UNIT MHz pF
The maximum frequency supported is core_clk/2 MHz. The load capacitance is adapted to a frequency.
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AM3517, AM3505
Table 4-10 details the sys_clkout2 output clock timing characteristics. Table 4-10. sys_clkout2 Output Clock Switching Characteristics
NAME f CO1 CO2 CO3 (1) 1 / CO0 tw(CLKOUT2) tR(CLKOUT2) tF(CLKOUT2) DESCRIPTION Frequency Pulse duration, sys_clkout2 low or high Rise time, sys_clkout2 (1) Fall time, sys_clkout2
(1)
MIN 0.40 * tc(CLKOUT2)
TYP
MAX 166 0.60 * tc(CLKOUT2) 3.7 4.3
UNIT MHz ns ns ns
With a load capacitance of 25 pF.
CO0 sys_clkout2
CO1
CO1
030-015
Figure 4-5. sys_clkout2 System Output Clock
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AM3517, AM3505
4.4
DPLL Specifications
The AM3517/05 integrates four DPLLs. The PRM and CM drive them. The four main DPLLs are: DPLL1 (MPU) DPLL3 (Core) DPLL4 (Peripherals) DPLL5 (Second Peripherals DPLL) Figure 4-6 illustrates the DPLL implementation.
Device VDDS_DPLL_MPU_USBHOST Power Rail
DPLL1
DPLL3
DPLL4
DPLL5
VDDS_DPLL_PER_CORE
030-016
Figure 4-6. DPLL Implementation
4.4.1
Digital Phase-Locked Loop (DPLL)

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the AM3517/05 device. DPLL1 gets an always-on clock used to produce the synthesized clock. They get a high-speed bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode. The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes performance during frequency scaling. Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition, all DPLL outputs can be controlled by an independent divider (M2 to M6). The clock generating DPLLs of the AM3517/05 device have following features: Independent power domain per DPLL Controlled by clock-manager (CM) Fed with always-on system clock with independent gating control per DPLL Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-MHz noise Up to four independent output dividers for simultaneous generation of multiple clock frequencies
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4.4.1.1
DPLL1 (MPU)
DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE DPLL) output as a high-frequency bypass input clock. 4.4.1.2 DPLL3 (CORE)
DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the emulation trace clock. It is located in the core domain area. All interface clocks and a few module functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input to DPLL1. 4.4.1.3 DPLL4 (Peripherals)
DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and emulation trace clock. It is located in the core domain area. All interface clocks and few module functional clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with always-on clock trees. 4.4.1.4 DPLL5 (Second peripherals DPLL)
DPLL5 supplies the 120-MHz functional clock to the CM.
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4.4.2
DPLL Noise Isolation

The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the cell to isolate it from substrate noise injection. The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the supply rails. The maximum input noise level allowed is 30 mVPP for frequencies below 1 MHz. Figure 4-7 illustrates an example of a noise filter.
Noise Filter VDDS_DPLL_MPU_USBHOST DPLL_MPU DPLL_CORE DLL C
Noise Filter VDDS_DPLL_PER_CORE DPLL5 DPLL4 C
030-017
Figure 4-7. DPLL Noise Filter Table 4-11 specifies the noise filter requirements. Table 4-11. DPLL Noise Filter Requirements
NAME Filtering capacitor (1) The capacitors must be inserted between power and ground as close as possible. (2) This circuit is provided only as an example. (3) The filter must be located as close as possible to the device. (4) No filtering required if noise is below 10 mVPP. MIN TYP 100 MAX UNIT nF
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AM3517, AM3505
5 VIDEO DAC SPECIFICATIONS

A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1 illustrates the AM3517/05 DAC architecture.
Device TV DCT tv_vfb1
Video DAC 1
TVOUT BUFFER
tv_out1 DSS tv_vfb2 DIN2[9:0] Video DAC 2 TVOUT TVOUT BUFFER BUFFER
tv_out2
vdda_dac
vssa_dac
tv_vref
V_ref
CBG
030-018
Figure 5-1. Video DAC Architecture The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and Table 5-4.
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ROUT2
ROUT1
DIN1[9:0]
AM3517, AM3505
5.1
Interface Description
Table 5-1 summarizes the external pins of the video DAC. Table 5-1. External Pins of 10-bit Video DAC
PIN NAME tv_out1
I/O O
DESCRIPTION TV analog output composite DAC1 video output. An external resistor is connected between this node and tv_vfb1. The nominal value of ROUT1 is 1650 . Finally, note that this is the output node that drives the load (75 ). DAC2 video output. An external resistor is connected between this node and tv_vfb2. The nominal value of ROUT2 is 1650 . Finally, note that this is the output node that drives the load (75 ). A decoupling capacitor (CBG) needs to be connected for optimum performance. Amplifier feedback node. An external resistor is connected between this node and tv_out1. The nominal value of ROUT1 is 1650 (1%). Amplifier feedback node. An external resistor is connected between this node and tv_out2. The nominal value of ROUT2 is 1650 (1%).
tv_out2
TV analog output S-VIDEO
tv_vref tv_vfb1 tv_vfb2
I O O
Reference output voltage from internal bandgap Amplifier feedback node Amplifier feedback node
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AM3517, AM3505
5.2
Electrical Specifications Over Recommended Operating Conditions

(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 , RLOAD = 75 , unless otherwise noted) Table 5-2. DAC Static Electrical Specification
PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP 10 1 1 RLOAD = 75 0,7 0.88 50 20 17 67.5 0.525 100-kHz reference noise bandwidth 3700 75 0.55 129 4000 40 2 channels, no load 2 channels Lasts less than 1 ns Measured at fCLK = 54 MHz, fOUT = 2 MHz sine wave, vdd = 1.3 V Lasts less than 1 ns T = 30C, vdda = 1.8 V T = 30C, vdd = 1.3 V 8 50 60 2 2.5 1.5 1 4200 dB mA mA mA mA mA mA mA 19 82.5 0.575 V 1 1 1 MAX UNIT Bits LSB LSB V mV mV/C % FS
R INL (1) DNL (2) RVOUT REFERENCE VREF RSET PSRR Ivdda-up -
Resolution Integral nonlinearity Differential nonlinearity Full-scale output voltage Output offset voltage Output offset voltage drift Gain error Output impedance Reference voltage range Reference noise density Full-scale current adjust resistor Reference PSRR
(3)
DC ACCURACY
ANALOG OUTPUT
(Up to 6 MHz)
POWER CONSUMPTION Analog Supply Current (4) Analog supply driving a 75- load (RMS) Digital supply current (5) Peak digital supply current (6) Analog power at power-down Digital power at power-down
Ivdda-up (peak) Peak analog supply current: Ivdd-up Ivdd-up (peak) Ivdda-down Ivdd-down (1) (2) (3) (4) (5) (6)
The INL is measured at the output of the DAC (accessible at an external pin during bypass mode). The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode). Assuming a capacitor of 0.1 F at the tv_ref node. The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD. The peak digital supply current occurs at full-scale transition for duration less than 1 ns.
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AM3517, AM3505
(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 , RLOAD = 75 , unless otherwise noted) Table 5-3. Video DAC Dynamic Electrical Specification
PARAMETER fCLK
(1)
CONDITIONS/ASSUMPTIONS Equal to input clock frequency rms clock jitter required in order to assure 10-bit accuracy Corner frequency for signal Image frequency Time from the start of the output transition to output within 1 LSB of final value. Measured from 10% to 90% of full-scale transition Measured from 10% to 90% of full-scale transition
MIN
TYP 54
MAX 40
UNIT MHz ps dB dB ns ns ns MHz deg. dB dB dB
Output update rate Clock jitter Attenuation at 5.1 MHz Attenuation at 54 MHz (1)
0.1 25
0.5 30 85 25 25 6 1.5% 1
1.5 33
tST tRout tFout BW
Output settling time Output rise time Output fall time Signal bandwidth Differential gain (2) Differential phase (2)
SFDR SNR PSRR Crosstalk (1) (2) (3) (4)
Within bandwidth Signal-to-noise ratio 1 kHz to 6 MHz bandwidth Power supply rejection ratio Between the two video channels
fCLK = 54 MHz, fOUT = 1 MHz fCLK = 54 MHz, fOUT = 1 MHz Up to 6 MHz
45 55 (3) 20 (4) 50 40
dB
For internal input clock information, For more information, see the Device Display Interface Subsystem Reference Guide [literature number SPRUFV2]. The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling. The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling. The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.
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AM3517, AM3505
5.3
Analog Supply (vdda_dac) Noise Requirements

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the noise requirements stated in this section. The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of
100 PSRRDAC = DI OUT I OUTFS VAC % FSR V
supply variation as shown in the following equation:
Depending on frequency, the PSRR is defined in Table 5-4. Table 5-4. Video DAC Power Supply Rejection Ratio
Supply Noise Frequency 0 to 100 kHz > 100 kHz PSRR % FSR/V 1 The rejection decreases 20 dB/dec. Example: at 1 MHz the PSRR is 10% of FSR/V
A graphic representation is shown in Figure 5-2.

PSRR (% FSR/V)
First pole of DAC output load 10
1 f
030-019
100 kHz 1 MHz
Figure 5-2. Video DAC Power Supply Rejection Ratio To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements translate to the following limits on vdda_dac (for the Video DAC). The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5: Table 5-5. Video DAC Maximum Peak-to-Peak Noise on vdda_dac
Tone Frequency 0 to 100 kHz > 100 kHz Maximum Peak-to-Peak Noise on vdda_dac < 30 mVpp Decreases 20 dB/dec. Example: at 1 MHz the maximum is 3 mVpp
The maximum noise spectral density (white noise) is defined in Table 5-6: Table 5-6. Video DAC Maximum Noise Spectral Density
Supply Noise Bandwidth 0 to 100 kHz > 100 kHz Maximum Supply Noise Density < 20 V / Hz Decreases 20 dB/dec. Example: at 1 MHz the maximum noise density is 2 / Hz
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AM3517, AM3505
Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External Component Value Choice).
5.4
External Component Value Choice

The full-scale output voltage VOUTMAX is regulated by the reference amplifier, and is set by an internal resistor RSET. IOUTMAX can be expressed as:
IOUTMAX = IREF /8 * (63 + 15/16) (2)
Where:
VREF = 0.5V IREF = VREF/RSET (3) (4)
The output current IOUT appearing at DAC output is a function of both the input code and IOUTMAX and can be expressed as:
IOUT = (DAC_CODE/1023) * IOUTMAX (5)
Where:
DAC_CODE = 0 to 1023 is the DAC input code in decimal. (6)
The output voltage is:

VOUT = IOUT *N* RCABLE (7)
Where:
(N = amplifier gain = 21) RCABLE (cable typical impedance) (8) (9)
The TV-out buffer requires a per channel external resistors: ROUT1/2. The equation below can be used to select different resistor values (if necessary):
ROUT = (N+1) RCABLE = 1650 (10)
Recommended parameter values are: Table 5-7. Video DAC Recommended External Components Values
Recommended Value CBG ROUT1/2 100 1650 UNIT nF
In order to limit the reference noise bandwidth and to suppress transients on VREF, it is necessary to connect a large decoupling capacitor BG) between the tv_vref and vssa_dac pins.
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AM3517, AM3505
6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

Note: The timing data shown is preliminary data and is subject to change in future revisions.
6.1
Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions of Table 3-3, unless otherwise specified.
6.2 6.2.1
Interface Clock Specifications Interface Clock Terminology

The Interface clock is used at the system level to sequence the data and/or control transfers accordingly with the interface protocol.
6.2.2
Interface Clock Frequency

The two interface clock characteristics are: The maximum clock frequency The maximum operating frequency The interface clock frequency documented in this document is the maximum clock frequency, which corresponds to the maximum frequency programmable on this output clock. This frequency defines the maximum limit supported by the AM3517/05 IC and doesn't take into account any system consideration (PCB, peripherals). The system designer will have to consider these system considerations and AM3517/05 IC timings characteristics as well, to define properly the maximum operating frequency, which corresponds to the maximum frequency supported to transfer the data on this interface.
6.2.3
Clock Jitter Specifications

Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this document is the time difference between the typical cycle period and the actual cycle period affected by noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.
Cycle (or Period) Jitter Tn-1 Tn Tn+1
Max. Cycle Jitter = Max (Ti) Min. Cycle Jitter = Min (Ti) Jitter Standard Deviation (or rms Jitter) = Standard Deviation (Ti)
030-020
Figure 6-1. Cycle (or Period) Jitter
6.2.4
Clock Duty Cycle Error

The maximum duty cycle error is the difference between the absolute value of the maximum high-level pulse duration or the maximum low-level pulse duration and the typical pulse duration value: Maximum pulse duration = typical pulse duration + maximum duty cycle error
106
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Minimum pulse duration = typical pulse duration - maximum duty cycle error
6.3
Timing Parameters
The timing parameter symbols used in the timing requirement and switching characteristic tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies have been abbreviated as follows: Table 6-1. Timing Parameters
LOWERCASE SUBSCRIPTS Symbols c d dis en h su START t v w X H L V IV AE FE LE Z Parameter Cycle time (period) Delay time Disable time Enable time Hold time Setup time Start bit Transition time Valid time Pulse duration (width) Unknown, changing, or dont care level High Low Valid Invalid Active Edge First Edge Last Edge High impedance
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
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AM3517, AM3505
6.4
External Memory Interfaces

The AM3517/05 processor includes the following external memory interfaces: General-purpose memory controller (GPMC) SDRAM controller (SDRC)
6.4.1
General-Purpose Memory Controller (GPMC)

The GPMC is the AM3517/05 unified memory controller used to interface external memory devices such as: Asynchronous SRAM-like memories and ASIC devices Asynchronous page mode and synchronous burst NOR flash NAND flash
6.4.1.1
GPMC/NOR Flash Interface Synchronous Timing
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions
TIMING CONDITION PARAMETER MIN Input Conditions tR tF Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 0.3 0.3 1.8 1.8 ns ns 1.8V, 3.3V MAX UNIT
Table 6-3. GPMC/NOR Flash Interface Timing Requirements Synchronous Mode

NO. F12 F13 F21 F22 (1) tsu(DV-CLKH) th(CLKH-DV) tsu(WAITV-CLKH) th(CLKH-WAITV) PARAMETER MIN Setup time, read gpmc_d[15:0] valid before gpmc_clk high Hold time, gpmc_d[15:0] valid after gpmc_clk high Setup time, gpmc_waitx (1) valid before gpmc_clk high Hold Time, gpmc_waitx (1) valid after gpmc_clk high 2.021 3.403 3.782 3.343 1.8V, 3.3V MAX ns ns ns ns UNIT
Wait monitoring support is limited to a WaitMonitoringTime value > 0.
Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode

NO. F0 F1 F1 tc(CLK) tw(CLKH) tw(CLKL) tdc(CLK) PARAMETER MIN Cycle time (1), output clock gpmc_clk period Typical pulse duration, output clock gpmc_clk high Typical pulse duration, output clock gpmc_clk low Duty cycle error, output clk gpmc_clk 10 0.5 P (2) 0.5 P (2) -500 0.5 P (2) 0.5 P (2) 500 1.8V, 3.3V MAX ns ns ns ps UNIT
(1) (2) 108
Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider. P = gpmc_clk period TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Table 6-4. GPMC/NOR Flash Interface Switching Characteristics Synchronous Mode (continued)
NO. tj(CLK) tR(CLK) tF(CLK) tR(DO) tF(DO) F2 F3 F4 F5 F6 F7 td(CLKH-nCSV) td(CLKH-nCSIV) td(ADDV-CLK) td(CLKH-ADDIV) td(nBEV-CLK) td(CLKH-nBEIV) PARAMETER MIN Jitter standard deviation (3), output clock gpmc_clk Rise time, output clock gpmc_clk Fall time, output clock gpmc_clk Rise time, output data Fall time, output data Delay time, gpmc_clk rising edge to gpmc_ncsx (4) transition Delay time, gpmc_clk rising edge to gpmc_ncsx (4) invalid Delay time, address bus valid to gpmc_clk first edge Delay time, gpmc_clk rising edge to gpmc_a[16:1] invalid Delay time, gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_clk first edge Delay time, gpmc_clk rising edge to gpmc_nbe0_cle, gpmc_nbe1 invalid F
(5)
1.8V, 3.3V MAX 33.30 1.6 1.6 2 2 - 1.9 F

(5)
UNIT ps ns ns ns ns ns ns ns ns
+ 3.3
E (6) - 1.9 B (7) - 4.1 -2.103 B (7) - 1.37 D (8) - 2.1
E (6) + 3.3 B (7) + 2.1
B (7) + 2.1 D (8) + 1.1
ns ns
(3) (4) (5)
(6) (7) (8)
The jitter probability density can be approximated by a Gaussian function. In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. For nCS falling edge (CS activated): Case GpmcFCLKDivider = 0: F = 0.5 * CSExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even) F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3) F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3) F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK B = ClkActivationTime * GPMC_FCLK For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 109
AM3517, AM3505
NO. F8 F9 td(CLKH-nADV) td(CLKH-nADVIV) PARAMETER MIN Delay time, gpmc_clk rising edge to gpmc_nadv_ale transition Delay time, gpmc_clk rising edge to gpmc_nadv_ale invalid G (9) - 1.9 D (10) - 1.9 1.8V, 3.3V MAX G (9) + 4.1 D (10) + 4.1 ns ns UNIT
(9)
For ADV falling edge (ADV activated): Case GpmcFCLKDivider = 0: G = 0.5 * ADVExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even) G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3) G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3) G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime --ClkActivationTime - 2) is a multiple of 3) For ADV rising edge (ADV deactivated) in Reading mode: Case GpmcFCLKDivider = 0: G = 0.5 * ADVExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even) G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3) G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime --ClkActivationTime --1) is a multiple of 3) G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime --ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode: Case GpmcFCLKDivider = 0: G = 0.5 * ADVExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even) G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3) G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3) G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3) (10) For single read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: D = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: D = (WrCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK 110 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
NO. F10 F11 F14 F15 F17 td(CLKH-nOE) td(CLKH-nOEIV) td(CLKH-nWE) td(CLKH-Data) td(CLKH-nBE) PARAMETER MIN Delay time, gpmc_clk rising edge to gpmc_noe transition Delay time, gpcm rising edge to gpmc_noe invalid Delay time, gpmc_clk rising edge to gpmc_nwe transition Delay time, gpmc_clk rising edge to data bus transition Delay time, gpmc_clk rising edge to gpmc_nbex_cle transition H (11) - 2.1 E (12) - 2.1 I (13) - 1.9 J (14) - 2.1 J (14) - 2.1 1.8V, 3.3V MAX H (11) + 2.1 E (12) + 2.1 I (13) + 4.1 J (14) + 1.1 J (14) + 1.1 ns ns ns ns ns UNIT
(11) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction): Case GpmcFCLKDivider = 0: H = 0.5 * OEExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even) H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3) H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3) H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3) For OE rising edge (OE deactivated): GpmcFCLKDivider = 0: H = 0.5 * OEExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even) H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3) H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3) H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3) (12) For single read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: E = (CSRdOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: E = (CSWrOffTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (13) For WE falling edge (WE activated): Case GpmcFCLKDivider = 0: I = 0.5 * WEExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even) I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3) I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime --ClkActivationTime - 1) is a multiple of 3) I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3) For WE rising edge (WE deactivated): Case GpmcFCLKDivider = 0: I = 0.5 * WEExtraDelay * GPMC_FCLK Case GpmcFCLKDivider = 1: I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even) I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise Case GpmcFCLKDivider = 2: I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3) I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3) I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3) (14) J = GPMC_FCLK period
111
AM3517, AM3505
NO. F18 F19 tW(nCSV) tW(nBEV) PARAMETER MIN Pulse duration, gpmc_ncsx (15) low Pulse duration, gpmc_nbe0_cle, gpmc_nbe1 low Pulse duration, gpmc_nadv_ale low Read Write Read Write Read Write H A (16) A (16) C (17) C K
(17) (18)
1.8V, 3.3V MAX
UNIT ns ns ns ns ns ns
F20 F23 F24
tW(nADVV) td(CLKH-IODIR) td(CLKH-IODIRIV)
K (18)
(11)
Delay time, gpmc_clk rising edge to gpmc_io_dir high (IN direction) Delay time, gpmc_clk rising edge to gpmc_io_dir low (OUT direction)
- 2.1
(11)
+ 4.1
ns ns
M (19) - 2.1
M (19) + 4.1
(15) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (16) For single read: A = (CSRdOffTime - CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst read: A = (CSRdOffTime - CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period For burst write: A = (CSWrOffTime - CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period with n being the page burst access number. (17) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: C = (RdCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: C = (WrCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page burst access number. (18) For read: K = (ADVRdOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For write: K = (ADVWrOffTime - ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK (19) M = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR behavior is automatically handled by GPMC controller.
112
AM3517, AM3505
F1 F0 gpmc_clk F2 F18 gpmc_ncsx F4 gpmc_a[10:1] F6 F19 gpmc_nbe0_cle F19 gpmc_nbe1 F6 gpmc_nadv_ale F10 gpmc_noe F13 F12 gpmc_d[15:0] gpmc_waitx F23 gpmc_io_dir OUT IN F24 OUT
030-021
F1 F3
Valid Address F7
F8 F20
F8 F9 F11
D0
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-2. GPMC/NOR Flash Synchronous Single Read (GpmcFCLKDivider = 0)
113
AM3517, AM3505
F1 F0 gpmc_clk F2 gpmc_ncsx F4 gpmc_a[10:1] F6 gpmc_nbe0_cle F7 gpmc_nbe1 F6 gpmc_nadv_ale F10 gpmc_noe F13 F12 gpmc_d[15:0] F21 gpmc_waitx F23 gpmc_io_dir OUT IN F24 OUT
030-022
F1 F3
Valid Address F7
F8
F8
F9 F11 F13 F12 D1 D2 D3
D0 F22
Figure 6-3. GPMC/NOR Flash Synchronous Burst Read 4x16-bit (GpmcFCLKDivider = 0)
114
AM3517, AM3505
F1 F1 gpmc_clk F2 gpmc_ncsx F4 gpmc_a[10:1] F6 gpmc_nbe0_cle F17 F17 gpmc_nbe1 F6 gpmc_nadv_ale F14 gpmc_nwe F15 gpmc_d[15:0] gpmc_waitx gpmc_io_dir OUT
030-023
F0 F3
Valid Address F17 F17 F17
F17 F9
F8
F8 F14 F15 D2 F15
D0
D1
D3
Figure 6-4. GPMC/NOR Flash Synchronous Burst Write (GpmcFCLKDivider = 0)
115
AM3517, AM3505
F1 F0 gpmc_clk F2 gpmc_ncsx F6 gpmc_nbe0_cle F6 gpmc_nbe1 F4 gpmc_a[26:17] F4 gpmc_a[16:1]_d[15:0] gpmc_nadv_ale F10 gpmc_noe gpmc_waitx F23 gpmc_io_dir OUT IN F24 OUT
030-024
F1 F3 F7
Valid F7 Valid Address (MSB) F12 F5 Address (LSB) F8 F8 D0 F13 D1 D2 F9 F11 F12 D3
Figure 6-5. GPMC/Multiplexed NOR Flash Synchronous Burst Read
116
AM3517, AM3505
F1 F1 gpmc_clk F2 gpmc_ncsx F4 gpmc_a[26:17] F6 gpmc_nbe0_cle F17 F17 gpmc_nbe1 F6 gpmc_nadv_ale F14 gpmc_nwe F15 gpmc_d[15:0] gpmc_waitx gpmc_io_dir OUT
030-025
F0 F3
Address (MSB) F17 F17 F17
F17 F9 F14 F15 D2 F15 D3
F8
F8
Address (LSB)
D0
D1
Figure 6-6. GPMC/Multiplexed NOR Flash Synchronous Burst Write 6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD Output load capacitance 30 pF
(2)
VALUE 1.8 1.8
UNIT ns ns
Input signal rise time Input signal fall time
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing Internal Parameters (1)
NO. FI1 FI2 FI3 FI4 FI5 FI6 (1) (2) PARAMETER MIN Maximum output data generation delay from internal functional clock Maximum input data capture delay by internal functional clock Maximum device select generation delay from internal functional clock Maximum address generation delay from internal functional clock Maximum address valid generation delay from internal functional clock Maximum byte enable generation delay from internal functional clock 1.8V,3.3V MAX 6.5 4 6.5 6.5 6.5 6.5
UNIT ns ns ns ns ns ns
The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field. Internal parameters are referred to the GPMC functional internal clock which is not provided externally. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 117
AM3517, AM3505
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing Internal Parameters(1) (2) (continued)
NO. FI7 FI8 FI9 PARAMETER MIN Maximum output enable generation delay from internal functional clock Maximum write enable generation delay from internal functional clock Maximum functional clock skew 1.8V,3.3V MAX 6.5 6.5 100 ns ns ps UNIT
Table 6-7. GPMC/NOR Flash Interface Timing Requirements Asynchronous Mode

NO. FA5 (1) FA20
(3)
PARAMETER MIN tacc(DAT) tacc1-pgmode(DAT) tacc2-pgmode(DAT) Data maximum access time Page mode successive data maximum access time Page mode first data maximum access time
1.8V,3.3V MAX H (2) P (4) H (2)
UNIT GPMC_FCLK cycles GPMC_FCLK cycles GPMC_FCLK cycles
FA21 (5) (1) (2) (3) (4) (5)
The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field. H = AccessTime * (TimeParaGranularity + 1) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field. P = PageBurstAccessTime * (TimeParaGranularity + 1) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics Asynchronous Mode

NO. tR(DO) tF(DO) FA0 tW(nBEV) PARAMETER MIN Rise time, output data Fall time, output data Pulse duration, gpmc_nbe0_cle, gpmc_nbe1 valid time Pulse duration, gpmc_ncsx(13) v low Delay time, gpmc_ncsx(13) valid to gpmc_nadv_ale invalid Read Write Read Write Read Write B(2) 0.2 B(2) 0.2 C(3) 0.2 J(9) 0.2 J(9) 0.2 N(12) N(12) A(1) A(1) B(2) + 2.0 B(2) + 2.0 C(3) + 2.0 J(9) + 2.0 J(9) + 2.0 1.8V/ 3.3V MAX 2.0 2.0 ns ns ns ns ns ns ns ns ns ns ns UNIT
FA1 FA3
tW(nCSV) td(nCSV-nADVIV)
FA4 FA9 FA10
td(nCSV-nOEIV) td(AV-nCSV) td(nBEV-nCSV)
Delay time, gpmc_ncsx(13) valid to gpmc_noe invalid (Single read) Delay time, address bus valid to gpmc_ncsx(13) valid Delay time, gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_ncsx(13) valid Delay time, gpmc_ncsx(13) valid to gpmc_nadv_ale valid Delay time, gpmc_ncsx(13) valid to gpmc_noe valid Delay time, gpmc_ncsx(13) valid to gpmc_io_dir high Delay time, gpmc_ncsx(13) valid to gpmc_io_dir low Address invalid duration between 2 successive R/W accesses
FA12 FA13 FA14 FA15 FA16
td(nCSV-nADVV) td(nCSV-nOEV) td(nCSV-IODIR) td(nCSV-IODIR) tw(AIV)
K(10) 0.2 L(11) 0.2 L(11) 0.2 M(14) 0.2 G(7)
K(10) + 2.0 L(11) + 2.0 L(11) + 2.0 M(14) + 2.0
ns ns ns ns ns
118
AM3517, AM3505
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics Asynchronous Mode (continued)
NO. FA18 FA20 FA25 FA27 FA28 FA29 FA37 td(nCSV-nOEIV) tw(AV) td(nCSV-nWEV) td(nCSV-nWEIV) td(nWEV-DV) td(DV-nCSV) td(nOEV-AIV) PARAMETER MIN Delay time, gpmc_ncsx(13) valid to gpmc_noe invalid (Burst read) Pulse duration, address valid 2nd, 3rd, and 4th accesses Delay time, gpmc_ncsx(13) valid to gpmc_nwe valid Delay time, gpmc_ncsx(13) valid to gpmc_nwe invalid Delay time, gpmc_ new valid to data bus valid Delay time, data bus valid to gpmc_ncsx(13) valid Delay time, gpmc_noe valid to gpmc_a[16:1]_d[15:0] address phase end J(9) 0.2 E(5) 0.2 F(6) 0.2 I(8) 0.2 D(4) E(5) + 2.0 F(6) + 2.0 2.0 J(9) + 2.0 2.0 1.8V/ 3.3V MAX I(8) + 2.0 ns ns ns ns ns ns ns UNIT
(1) For single read: A = (CSRdOffTime CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For single write: A = (CSWrOffTime CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: A = (CSRdOffTime CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: A = (CSWrOffTime CSOnTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the page burst access number (2) For reading: B = ((ADVRdOffTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay CSExtraDelay)) * GPMC_FCLK For writing: B = ((ADVWrOffTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay CSExtraDelay)) * GPMC_FCLK (3) C = ((OEOffTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay CSExtraDelay)) * GPMC_FCLK (4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK (5) E = ((WEOnTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay CSExtraDelay)) * GPMC_FCLK (6) F = ((WEOffTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay CSExtraDelay)) * GPMC_FCLK (7) G = Cycle2CycleDelay * GPMC_FCLK (8) I = ((OEOffTime + (n 1) * PageBurstAccessTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay CSExtraDelay)) * GPMC_FCLK (9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK (10) K = ((ADVOnTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay CSExtraDelay)) * GPMC_FCLK (11) L = ((OEOnTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay CSExtraDelay)) * GPMC_FCLK (12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK For burst read: N = (RdCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK For burst write: N = (WrCycleTime + (n 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK (13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. (14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR behavior is automatically handled by GPMC controller.
119
AM3517, AM3505
GPMC_FCLK gpmc_clk FA5 FA1 gpmc_ncsx FA9 gpmc_a[10:1] FA10 gpmc_nbe0_cle gpmc_nbe1 FA10 gpmc_nadv_ale FA4 FA13 gpmc_noe gpmc_d[15:0] gpmc_waitx FA14 gpmc_io_dir OUT FA15 IN OUT
030-026
Valid Address FA0 Valid FA0 Valid FA3 FA12
Data IN 0
Data IN 0
Figure 6-7. GPMC/NOR Flash Asynchronous Read Single Word Timing(1) (2) (3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bit field. (3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
120
AM3517, AM3505
GPMC_FCLK gpmc_clk FA5 FA1 gpmc_ncsx FA16 FA9 gpmc_a[10:1] FA10 gpmc_nbe0_cle gpmc_nbe1 FA10 FA3 FA12 gpmc_nadv_ale FA4 FA13 gpmc_noe gpmc_d[15:0] gpmc_waitx FA15 gpmc_io_dir FA14 OUT IN FA14 OUT FA15 IN
030-027 Data Upper
FA5 FA1
FA9 Address 0 FA0 FA10 Valid FA0 Valid FA10 FA3 FA12 FA4 FA13 Valid FA0 Valid Address 1 FA0
Figure 6-8. GPMC/NOR Flash Asynchronous Read 32-bit Timing(1) (2) (3)
121
AM3517, AM3505
GPMC_FCLK gpmc_clk FA21 FA1 gpmc_ncsx FA9 gpmc_a[10:1] FA10 gpmc_nbe0_cle FA0 FA10 gpmc_nbe1 FA12 gpmc_nadv_ale FA18 FA13 gpmc_noe gpmc_d[15:0] gpmc_waitx FA15 gpmc_io_dir
OUT
FA20
FA20
FA20
Add0 FA0
Add1
Add2
Add3
Add4
D0
D1
D2
D3
D3
FA14
IN
OUT 030-028
Figure 6-9. GPMC/NOR Flash Asynchronous Read Page Mode 4x16-bit Timing(1) (2) (3) (4)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3. (2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside AccessTime register bit field. (3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input page data). FA20 value must be stored in PageBurstAccessTime register bit field. (4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
122
AM3517, AM3505
gpmc_fclk gpmc_clk FA1 gpmc_ncsx FA9 gpmc_a[10:1] FA10 gpmc_nbe0_cle FA0 FA10 gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA27 FA25 gpmc_nwe FA29 gpmc_d[15:0] gpmc_waitx gpmc_io_dir OUT
030-029
Valid Address FA0
Data OUT
Figure 6-10. GPMC/NOR Flash Asynchronous Write Single Word Timing
123
AM3517, AM3505
GPMC_FCLK gpmc_clk FA1 FA5 gpmc_ncsx FA9 gpmc_a[26:17] FA10 gpmc_nbe0_cle FA10 gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA4 FA13 gpmc_noe FA29 gpmc_a[16:1]_d[15:0] gpmc_io_dir gpmc_waitx
030-030
Address (MSB) FA0 Valid FA0 Valid
FA37
Data IN Data IN
Address (LSB) FA14 OUT FA15 IN
OUT
Figure 6-11. GPMC/Multiplexed NOR Flash Asynchronous Read Single Word Timing(1) (2) (3)
124
AM3517, AM3505
gpmc_fclk gpmc_clk FA1 gpmc_ncsx FA9 gpmc_a[26:17] FA10 gpmc_nbe0_cle FA0 FA10 gpmc_nbe1 FA3 FA12 gpmc_nadv_ale FA27 FA25 gpmc_nwe FA29 gpmc_a[16:1]_d[15:0] gpmc_waitx gpmc_io_dir OUT
030-031
Address (MSB) FA0
FA28 Data OUT
Valid Address (LSB)
Figure 6-12. GPMC/Multiplexed NOR Flash Asynchronous Write Single Word Timing 6.4.1.3 GPMC/NAND Flash Interface Timing
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER MIN Input Conditions tR tF CLOAD Input signal rise time Input signal fall time Output load capacitance 1.8 1.8 30 ns ns pF
(2)
1.8V, 3.3V MAX
UNIT
Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters (1)
NO. GNFI1 GNFI2 GNFI3 (1) (2) PARAMETER MIN Maximum output data generation delay from internal functional clock Maximum input data capture delay by internal functional clock Maximum device select generation delay from internal functional clock 1.8V, 3.3V MAX 6.5 4 6.5
UNIT ns ns ns
Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field. Internal parameters are referred to the GPMC functional internal clock which is not provided externally. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 125
AM3517, AM3505
Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters(1) (2) (continued)
NO. GNFI4 GNFI5 GNFI6 GNFI7 GNFI8 PARAMETER MIN Maximum address latch enable generation delay from internal functional clock Maximum command latch enable generation delay from internal functional clock Maximum output enable generation delay from internal functional clock Maximum write enable generation delay from internal functional clock Maximum functional clock skew 1.8V, 3.3V MAX 6.5 6.5 6.5 6.5 100 ns ns ns ns ps UNIT
Table 6-11. GPMC/NAND Flash Interface Timing Requirements

NO. GNF12 (1) (1) (2) tacc(DAT) PARAMETER MIN Data maximum access time 1.8V, 3.3V MAX J (2) GPMC_FCLK cycles UNIT
The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. J = AccessTime * (TimeParaGranularity + 1)
Table 6-12. GPMC/NAND Flash Interface Switching Characteristics

NO. tR(DO) tF(DO) GNF0 GNF1 GNF2 GNF3 GNF4 GNF5 GNF6 GNF7 GNF8 GNF9 GNF10 GNF13 GN F14 GNF15 tw(nWEV) td(nCSV-nWEV) tw(CLEH-nWEV) tw(nWEV-DV) tw(nWEIV-DIV) tw(nWEIV-CLEIV) tw(nWEIV-nCSIV) tw(ALEH-nWEV) tw(nWEIV-ALEIV) tc(nWE) td(nCSV-nOEV) tw(nOEV) tc(nOE) tw(nOEIV-nCSIV) PARAMETER MIN Rise time, output data Fall time, output data Pulse duration, gpmc_nwe valid time Delay time, gpmc_ncsx(13) valid to gpmc_nwe valid Delay time, gpmc_nbe0_cle high to gpmc_nwe valid Delay time, gpmc_d[15:0] valid to gpmc_nwe valid Delay time, gpmc_nwe invalid to gpmc_d[15:0] invalid Delay time, gpmc_nwe invalid to gpmc_nbe0_cle invalid Delay time, gpmc_nwe invalid to gpmc_ncsx(13) invalid Delay time, gpmc_nadv_ale High to gpmc_nwe valid Delay time, gpmc_nwe invalid to gpmc_nadv_ale invalid Cycle time, Write cycle time Delay time, gpmc_ncsx(13) valid to gpmc_noe valid Pulse duration, gpmc_noe valid time Cycle time, Read cycle time Delay time, gpmc_noe invalid to gpmc_ncsx(13) invalid M(12) - 0.2 I(9) - 0.2 K(10) L(11) M(12) + 2.0 B(2) - 0.2 C(3) - 0.2 D(4) - 0.2 E(5) - 0.2 F(6) - 0.2 G(7) - 0.2 C(3) - 0.2 F(6) - 0.2 H(8) I(9) + 2.0 A(1) B(2) + 2.0 C(3) + 2.0 D(4) + 2.0 E(5) + 2.0 F(6) + 2.0 G(7) + 2.0 C(3) + 2.0 F(6) + 2.0 1.8V, 3.3V MAX 2.0 2.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
126
AM3517, AM3505
(1) A = (WEOffTime WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK (2) B = ((WEOnTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay CSExtraDelay)) * GPMC_FCLK (3) C = ((WEOnTime ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay ADVExtraDelay)) * GPMC_FCLK (4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK (5) E = (WrCycleTime WEOffTime * (TimeParaGranularity + 1) 0.5 * WEExtraDelay ) * GPMC_FCLK (6) F = (ADVWrOffTime WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay WEExtraDelay ) * GPMC_FCLK (7) G = (CSWrOffTime WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay WEExtraDelay ) * GPMC_FCLK (8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (9) I = ((OEOnTime CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay CSExtraDelay)) * GPMC_FCLK (10) K = (OEOffTime OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK (11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK (12) M = (CSRdOffTime OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay OEExtraDelay ) * GPMC_FCLK (13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
GPMC_FCLK GNF1 gpmc_ncsx GNF2 gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF0 gpmc_nwe GNF3 gpmc_a[16:1]_d[15:0] Command
030-032
GNF6 GNF5
GNF4
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-13. GPMC/NAND Flash Command Latch Cycle Timing

GPMC_FCLK GNF1 gpmc_ncsx gpmc_nbe0_cle GNF7 gpmc_nadv_ale gpmc_noe GNF9 GNF0 gpmc_nwe GNF3 gpmc_a[16:1]_d[15:0] Address
030-033
GNF6
GNF8
GNF4
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-14. GPMC/NAND Flash Address Latch Cycle Timing
127
AM3517, AM3505
GPMC_FCLK GNF12 GNF10 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale GNF14 GNF13 gpmc_noe gpmc_a[16:1]_d[15:0] gpmc_waitx
030-034
GNF15
DATA
Figure 6-15. GPMC/NAND Flash Data Read Cycle Timing(1) (2) (3)
(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field. (2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally. (3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.
GPMC_FCLK GNF1 gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe GNF9 GNF0 gpmc_nwe GNF3 gpmc_a[16:1]_d[15:0] DATA
030-035
GNF6
GNF4
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.
Figure 6-16. GPMC/NAND Flash Data Write Cycle Timing
128
AM3517, AM3505
6.4.2
SDRAM Controller (SDRC)

The SDRC is a dedicated interface to DDR2/LPDDR1 SDRAM that performs the following functions: Buffering of input image data from sensors or video sources Intermediate buffering for processing/resizing of image data in the VPFE Numerous OSD display buffers Intermediate buffering for large raw Bayer data image files while performing image processing functions Buffering for intermediate data while performing video encode and decode functions Storage of executable code for the ARM The main features of the controller are: Open Core Protocol 2.2 (OCP) compliant [7]. Supports JEDEC standard compliant DDR2 [2] and LPDDR1 [4] devices. SDRAM address range over 2 chip selects. Supports following data bus widths:
OCP Data Bus Width SDRAM Data Bus Width 64 and 128-Bit 16, 32, and 64-Bit
Supports following CAS latencies:

SDRAM Type DDR2 LPDDR1 CAS Latencies 2, 3, 4, 5, and 6 2 and 3
Supports following number of internal banks:

SDRAM Type DDR2 LPDDR1 Internal Banks 1, 2, 4, and 8 1, 2, and 4
Supports 256, 512, 1024, and 2048-word page sizes. Supports following burst lengths:
SDRAM Type DDR2 LPDDR1 Burst Length 8 (4 not supported) 8 (2 and 4 not supported)
Supports sequential burst type. SDRAM auto initialization from reset or configuration change. Supports Bank Interleaving across both the chip selects. Supports Clock Stop mode for LPDDR1 for low power. Supports Self Refresh and Precharge Power-Down modes for low power. Supports Partial Array Self Refresh and Temperature Controlled Self Refresh modes for low power in LPDDR1. Temperature Controlled Self Refresh is only supported for mobile SDRAM having on-chip temperature sensor. Supports ODT on DDR2. Supports prioritized refresh. Programmable SDRAM refresh rate and backlog counter. Programmable SDRAM timing parameters. Supports only little endian.
129
AM3517, AM3505
6.4.2.1
LPDDR Interface
This section provides the timing specification for the LPDDR interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory system without the need for a complex timing closure process. For more information regarding guidelines for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing Specification Application Report (literature number SPRAAV0). 6.4.2.1.1 LPDDR Interface Schematic Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1 x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is deleted.
Microprocessor sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0p sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1p sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2p sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3p sdrc_ba0 sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_clk sdrc_nclk
T T
LPDDR DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS
T T T T
T T T
LPDDR DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS BA0 BA1 A0 A14 CS CAS RAS WE CKE CK CK
T T T T
T T T T T T
BA0 BA1 A0 A14 CS CAS RAS WE CKE CK CK
T T T T T T T T
Figure 6-17. AM3517/05 LPDDR High Level Schematic (x16 memories)
130
AM3517, AM3505
Microprocessor sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0 sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncs1 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_cke1 sdrc_clk sdrc_nclk
T
LPDDR DQ0 DQ7 DM0 DQS0 DQ8 DQ15 DM1 DQS1 DQ16 DQ23 DM2 DQS2 DQ24 DQ31 DM3 DQS3 BA0 BA1 A0 A14 CS N/C
T T T T
T T T T
T T T T
T T T T
T T T T T T
T T
CAS RAS WE CKE N/C CK CK
T T
Figure 6-18. AM3517/05 LPDDR High Level Schematic (x32 memory) 6.4.2.1.2 Compatible JEDEC LPDDR Devices Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface. Generally, the LPDDR interface is compatible with x16 and x32 LPDDR333 speed grade LPDDR devices. Table 6-13. Compatible JEDEC LPDDR Devices
NO. 1 2 3 4 (1) (2) PARAMETER JEDEC LPDDR Device Speed Grade JEDEC LPDDR Device Bit Width JEDEC LPDDR Device Count JEDEC LPDDR Device Ball Count MIN LPDDR333 16 1 60 32 2 90 Bits Devices Balls See Note
(2)
MAX
UNIT
NOTES See Note

(1)
Higher LPDDR speed grades operating at the specified speeds are supported due to inherent JEDEC LPDDR backwards compatibility. 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory system.
131
AM3517, AM3505
6.4.2.1.3 PCB Stackup The minimum stackup required for routing the microprocessor is a six layer stack as shown in Table 6-14. Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size of the PCB footprint. Table 6-14. Minimum PCB Stack Up
LAYER 1 2 3 4 5 6 TYPE Signal Plane Plane Signal Plane Signal DESCRIPTION Top Routing Mostly Horizontal Ground Power Internal Routing Ground Bottom Routing Mostly Vertical
Table 6-15. PCB Stack Up Specifications

NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (1) (2) (3) PARAMETER PCB Routing/Plane Layers Signal Routing Layers Full ground layers under LPDDR routing region Number of ground plane cuts allowed within LPDDR routing region Number of ground reference planes required for each LPDDR routing 1 layer Number of layers between LPDDR routing layer and reference ground 0 plane PCB Routing Feature Size PCB Trace Width w PCB BGA escape via pad size PCB BGA escape via hole size Device BGA Pad Size LPDDR Device BGA Pad Size Single Ended Impedance, ZO Impedance Control 50 Z-5 Z 75 Z+5 See Note (3) 4 4 18 8 1 0 Mils Mils Mils Mils See Note (1) See Note (2) MIN 6 3 2 0 TYP MAX UNIT NOTES
Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size. Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size. Z is the nominal singled ended impedance selected for the PCB specified by item 12.
6.4.2.1.4 Placement Figure 6-19 shows the required placement for the microprocessor as well as the LPDDR devices. The dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second LPDDR device is omitted from the placement.
132
AM3517, AM3505
X A1 Y OFFSET Y LPDDR Device Y OFFSET A1 Recommended LPDDR Device Orientation
Microprocessor
Figure 6-19. AM3517/05 and LPDDR Device Placement Table 6-16. Placement Specifications
NO. 1 2 3 4 5 (1) (2) (3) (4) (5) PARAMETER X Y Y Offset LPDDR Keepout Region Clearance from non-LPDDR signal to LPDDR Keepout Region 4 w MIN MAX 1440 1030 525 UNIT Mils Mils Mils NOTES See Notes (1), See Notes (1), See Notes See Note (4) See Note (5)
(2) (2)
LPDDR Controller
(1) (2) (3)
, ,
See Figure 6-19 for dimension definitions. Measurements from center of device to center of LPDDR device. For 16 bit memory systems it is recommended that Y Offset be as small as possible. LPDDR keepout region to encompass entire LPDDR routing area. Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.
6.4.2.1.5 LPDDR Keep Out Region The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with the placement and LPDDR routing. Additional clearances required for the keep out region are shown in Table 6-16.
133
AM3517, AM3505
A1
LPDDR Controller
LPDDR Device
A1
Region should encompass all LPDDR circuitry and varies depending on placement. Non-LPDDR signals should not be routed on the LPDDR signal layers within the LPDDR keep out region. Non-LPDDR signals may be routed in the region provided they are routed on layers separated from LPDDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.8 V power plane should cover the entire keep out region.
Figure 6-20. LPDDR Keepout Region 6.4.2.1.6 Net Classes Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the termination and routing rules that follow. Table 6-17. Clock Net Class Definitions
CLOCK NET CLASS CK DQS0 DQS1 DQS2 DQS3 PIN NAMES sdrc_clk/sdrc_nclk sdrc_dqs0 sdrc_dqs1 sdrc_dqs2 sdrc_dqs3
Table 6-18. Signal Net Class Definitions

CLOCK NET CLASS ADDR_CTRL DQ0 DQ1 DQ2 DQ3 ASSOCIATED CLOCK NET CLASS CK DQS0 DQS1 DQS2 DQS3 PIN NAMES sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas, sdrc_nras, sdrc_nwe, sdrc_cke0 sdrc_d, sdrc_dm0 sdrc_d, sdrc_dm1 sdrc_d, sdrc_dm2 sdrc_d, sdrc_dm3
6.4.2.1.7 LPDDR Signal Termination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-19 shows the specifications for the series terminators.
134
AM3517, AM3505
Table 6-19. LPDDR Signal Terminations

NO. 1 2 3 (1) (2) (3) PARAMETER CK Net Class ADDR_CTRL Net Class Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3) MIN 0 0 0 22 22 TYP MAX 10 Zo Zo UNIT NOTES See Note (1) See Notes (1), (2), (3) See Notes (1), (2), (3)
Only series termination is permitted, parallel or SST specifically disallowed. Terminator values larger than typical only recommended to address EMI issues. Termination value should be uniform across net class.
6.4.2.1.8 LPDDR CK and ADDR_CTRL Routing Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.
A1
T A C
A1
Figure 6-21. CK and ADDR_CTRL Routing and Topology Table 6-20. CK and ADDR_CTRL Routing Specification
NO. 1 2 3 4 5 6 7 8 9 10 11 (1) (2) (3) PARAMETER Center to Center CK-CK spacing CK A to B/A to C Skew Length Mismatch CK B to C Skew Length Mismatch Center to Center CK to other LPDDR trace spacing CK/ADDR_CTRL nominal trace length ADDR_CTRL to CK Skew Length Mismatch ADDR_CTRL to ADDR_CTRL Skew Length Mismatch Center to Center ADDR_CTRL to other LPDDR trace 4w spacing Center to Center ADDR_CTRL to other ADDR_CTRL 3w trace spacing ADDR_CTRL A to B/A to C Skew Length Mismatch ADDR_CTRL B to C Skew Length Mismatch 4w 3w 100 100 Mils Mils 4w CACLM-50 CACLM CACLM+50 100 100 Mils Mils Mils See Note (2) See Note (2) See Note (1) MIN TYP MAX 2w 25 25 Mils Mils See Note (2) See Note (3) See Note (1) UNIT NOTES
Series terminator, if used, should be located closest to device. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
LPDDR Controller
Microprocessor
135
AM3517, AM3505
Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.
T A1 T E0 E1
T A1 E2 T E3
Figure 6-22. DQS and DQ Routing and Topology Table 6-21. DQS and DQ Routing Specification (1)
NO. 2 3 4 5 6 7 8 9 (1) (2) (3) (4) PARAMETER DQS E Skew Length Mismatch Center to Center DQS to other LPDDR trace spacing DQS/DQ nominal trace length DQ to DQS Skew Length Mismatch DQ to DQ Skew Length Mismatch Center to Center DQ to other LPDDR trace spacing Center to Center DQ to other DQ trace spacing DQ E Skew Length Mismatch 4w 3w 100 Mils 4w DQLM - 50 DQLM DQLM + 50 100 100 Mils Mils Mils See Note (2) See Note (2), (4) MIN TYP MAX 25 UNIT Mils See Note (2) See Note (3) NOTES
Series terminator, if used, should be located closest to LPDDR. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. DQLM is the longest Manhattan distance of the DQS and DQ net classes.
136
LPDDR Controller
Microprocessor
AM3517, AM3505
6.4.2.2
DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need for a complex timing closure process. For more information regarding guidelines for using this DDR2 specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0). 6.4.2.2.1 DDR2 Interface Schematic Figure 6-23 shows the DDR2 interface schematic for a dual-memory DDR2 system. The single-memory system is shown in Figure 6-24. Pin numbers for the AM3517/05 can be obtained from the pin description section. 6.4.2.2.2 Compatible JEDEC DDR2 Devices Table 6-22 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface. Generally, the DDR2 interface is compatible with x16 or x32 DDR2 speed grade DDR2-333 devices. Table 6-22. Compatible JEDEC DDR2 Devices
No. 1 2 3 4 (1) (2) (3) Parameter JEDEC DDR2 Device Speed Grade JEDEC DDR2 Device Bit Width JEDEC DDR2 Device Count JEDEC DDR2 Device Ball Count Min DDR2-333 MHz x16 1 84 x32 2 92 Bits Devices Balls See Note See Note
(2) (3)
Max
Unit
Notes See Note

(1)
Higher DDR2 speed grades operating at the specified speeds are supported due to inherent JEDEC DDR2 backwards compatibility. Device count indicates number of dies. If a package contains 2 dies, that is the maximum number of devices that can be connected. 92 ball devices retained for legacy support. New designs should use 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2 devices are the same.
137
AM3517, AM3505
6.4.2.2.3 PCB Stackup The minimum stackup required for routing the AM3517/05 is a six layer stack as shown in Table 6-23. Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size of the PCB footprint. Table 6-23. Minimum PCB Stack Up
Layer 1 2 3 4 5 6 Type Signal Plane Plane Signal Plane Signal Description Top Routing Mostly Horizontal Ground Power Internal Routing Ground Bottom Routing Mostly Vertical
138
AM3517, AM3505
Complete stack up specifications are provided in Table 6-24.
Microprocessor
SDRC_D0 SDRC_D7 SDRC_DM0 SDRC_DQS0P SDRC_DQS0N SDRC_D8 SDRC_D15 SDRC_DM1 SDRC_DQS1P SDRC_DQS1N SDRC_STRBEN0
SDRC_STRBEN_DLY0
T
DQ0 DQ7 LDM LDQS LDQS# LQ8 LQ15 UDM UDQS UDQS#
Length = avg DQS0-1 length+CLK
T T T T T
T T T T T
x16 DDR2
DQ0 DQ7 LDM LDQS LDQS# DQ8 DQ15 UDM UDQS UDQS#
SDRC_STRBEN_DLY1
T T T T T
T T T T T
Length = avg DQS2-3 length+CLK

T T T T
SDRC_BA0 SDRC_BA1 SDRC_BA2 SDRC_A0 SDRC_A14 SDRC_nCS0 SDRC_nCS1 SDRC_nCAS SDRC_nRAS SDRC_nWE SDRC_nCKE0 SDRC_CLK SDRC_nCLK SDRC_ODT VREFSSTL DDR_PADREF
BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CLK CLK# ODT* VREF
BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CLK CLK# ODT* VREF
T T T T T T T T T T
Vio1.8 0.1F
1K 1%
0.1F(A)
0.1F(A)
0.1F
(A)
0.1F
1K 1%
50
1%
A. See VREF Routing and Topology figure for information on capacitor placement.
Figure 6-23. DDR2 Dual-Memory High Level Schematic
139
AM3517, AM3505
Microprocessor
SDRC_STRBEN_DLY0
T
DDR2
DQ0 DQ7 DM0 DQS0 DQS0# DQ8 DQ15 DM1 DQS1 DQS1#
Length = avg D0-D15 length+CLK
T T T T T
T T T T T T
SDRC_STRBEN_DLY1
DQ16 DQ23 DM2 DQS2 DQS2# DQ24 DQ31 DM3 DQS3 DQS3#
Length = avg D16-D31 length+CLK
T T T T T
T T T T T T T T T
SDRC_BA0 SDRC_BA1 SDRC_BA2 SDRC_A0 SDRC_A14 SDRC_nCS0 SDRC_nCS1 SDRC_nCAS SDRC_nRAS SDRC_nWE SDRC_nCKE0 SDRC_CLK SDRC_nCLK SDRC_ODT0 VREFSSTL DDR_PADREF
BA0 BA1 BA2* A0 A14* CS1 CS2* CAS# RAS# WE# CKE CLK CLK# ODT* VREF
T T T T T T T T T T
Vio1.8
0.1F
1K 1%
0.1F
(A)
0.1F
(A)
0.1F
(A)
0.1F
1K 1%
50 1%
A. See VREF Routing and Topology figure for information on capacitor placement.
Figure 6-24. DDR2 Single-Memory High Level Schematic
140
AM3517, AM3505
Table 6-24. PCB Stack Up Specifications

No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (1) (2) (3) Parameter PCB Routing/Plane Layers Signal Routing Layers Full ground layers under DDR2 routing Region Number of ground plane cuts allowed within DDR routing region Number of ground reference planes required for each DDR2 routing layer Number of layers between DDR2 routing layer and ground plane PCB Routing Feature Size PCB Trace Width w PCB BGA escape via pad size PCB BGA escape via hole size AM3517/05 BGA pad size DDR2 Device BGA pad size Single Ended Impedance, Zo Impedance Control 50 Z-5 Z 75 Z+5 See Note
(3)
Min 6 3 2
Typ
Max
Unit
Notes
0 1 0 4 4 20 10 12 Mils Mils Mils Mils See Note See Note

(1) (2)
The recommended pad size is 0.3 mm per IPC-7351 specification. Please refer to IPC standard IPC-7351 or manufacturer's recommendations for correct BGA pad size. Z is the nominal singled ended impedance selected for the PCB specified by item 12.
6.4.2.2.4 Placement Figure 6-24 shows the required placement for the DDR2 devices. The dimensions for Figure 6-25 are defined in Table 6-25. The placement does not restrict the side of the PCB that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space. For single-memory DDR2 systems, the second DDR2 device is omitted from the placement.
X A1 Y OFFSET Y DDR2 Device Y OFFSET A1 Recommended DDR2 Device Orientation
Figure 6-25. DDR2 Device Placement
DDR2 Controller
Microprocessor
141
AM3517, AM3505
Table 6-25. Placement Specifications

No. 1 2 3 4 5 (1) (2) (3) (4) (5) Parameter X Y Y Offset DDR2 Keepout Region Clearance from non-DDR2 signal to DDR2 Keepout Region 4 w Min Max 1750 1280 650 Unit Mils Mils Mils Notes See Notes See Notes See Notes
(3) (1) (2)
(1) (2)
(1) (2)
See Note See Note
(4) (5)
See Figure 6-23 for dimension definitions. Measurements from center of AM3517/05 device to center of DDR2 device. For single memory systems it is recommended that Y Offset be as small as possible. DDR2 Keepout region to encompass entire DDR2 routing area Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
6.4.2.2.5 DDR2 Keep Out Region The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep out region is defined for this purpose and is shown in Figure 6-26. The size of this region varies with the placement and DDR routing. Additional clearances required for the keep out region are shown in Table 6-25.
A1
DDR2 Device
A1
Region should encompass all DDR2 circuitry and varies depending on placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region. In addition, the 1.8 V power plane should cover the entire keep out region.
Figure 6-26. DDR2 Keepout Region
142
DDR2 Controller
AM3517, AM3505
6.4.2.2.6 Bulk Bypass Capacitors Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry. Table 6-26 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the AM3517/05 and DDR2 interfaces. Additional bulk bypass capacitance may be needed for other circuitry. Table 6-26. Bulk Bypass Capacitors
No. 1 2 3 4 5 6 (1) (2) Parameter VDDS Bulk Bypass Capacitor Count VDDS Bulk Bypass Total Capacitance DDR#1 Bulk Bypass Capacitor Count DDR#1 Bulk Bypass Total Capacitance DDR#2 Bulk Bypass Capacitor Count DDR#2 Bulk Bypass Total Capacitance Min 3 30 1 22 1 22 Max Unit Devices uF Devices uF Devices uF See Notes (1) (2) , See Note
(2)
Notes See Note

(1)
See Note
(1)
These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps. Only used on dual-memory systems
143
AM3517, AM3505
6.4.2.2.7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, AM3517/05 DDR2 power, and AM3517/05 DDR2 ground connections. Table 6-27 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. 6.4.2.2.8 Net Classes Table 6-28 lists the clock net classes for the DDR2 interface. Table 6-29 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the termination and routing rules that follow. Table 6-27. High-Speed Bypass Capacitors
No. 1 2 3 4 5 6 7 8 9 10 11 12 (1) (2) (3) (4) Parameter HS Bypass Capacitor Package Size Distance from HS bypass capacitor to device being bypassed Number of connection vias for each HS bypass capacitor Trace length from bypass capacitor contact to connection via Number of connection vias for each DDR2 device power or ground balls Trace length from DDR2 device power ball to connection via VDDS HS Bypass Capacitor Count VDDS HS Bypass Capacitor Total Capacitance DDR#1 HS Bypass Capacitor Count DDR#1 HS Bypass Capacitor Total Capacitance DDR#2 HS Bypass Capacitor Count DDR#2 HS Bypass Capacitor Total Capacitance 20 1.2 8 0.4 8 0.4 2 1 1 35 30 Min Max 0402 250 Unit 10 Mils Mils Vias Mils Vias Mils Devices F Devices F Devices F See Notes (3) (4) , See Note
(4)
Notes See Note See Note

(1)
(2)
See Note See Note
(3)
(3)
LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. These devices should be placed as close as possible to the device being bypassed. Only used on dual-memory systems
144
AM3517, AM3505
Table 6-28. Clock Net Class Definitions

Clock Net Class CK DQS0 DQS1 DQS2 DQS3 AM3517/05 Device Pin Names sdrc_clk/sdrc_nclk sdrc_dqs0p /sdrc_dqs0n sdrc_dqs1p /sdrc_dqs1n sdrc_dqs2p/sdrc_dqs2n sdrc_dqs3p/sdrc_dqs3n
Table 6-29. Signal Net Class Definitions

Clock Net Class ADDR_CTRL DQ0 DQ1 DQ2 DQ3 SDRC_STRBEN0 SDRC_STRBEN1 Associated Clock Net Class CK DQS0 DQS1 DQS2 DQS3 CK,DQS0,DQS1 CK,DQS2,DQS3 AM3517/05 Device Pin Names sdrc_ba[2:0], sdrc_ncs1, sdrc_a[14:0], sdrc_ncs0 , sdrc_ncas, sdrc_nras, sdrc_nwe, sdrc_cke0 sdrc_d[7:0], sdrc_dm0 sdrc_d[15:8], sdrc_dm1 sdrc_d[23:16],sdrc_dm2 sdrc_d[31:24],sdrc_dm3 sdrc_strben0, sdrc_strben_dly0 sdrc_strben1, sdrc_strben_dly1
6.4.2.2.9 DDR2 Signal Termination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-30 shows the specifications for the series terminators. Table 6-30. DDR2 Signal Terminations
No. 1 2 3 4 (1) (2) (3) Parameter CLK Net Class ADDR_CTRL Net Class Data Byte Net Classes (DQS0-DQS1, D0-D31) SDRC_STRBENx Net Class (SDRC_STRBENx) Only series termination is permitted, parallel or SST specifically disallowed. Terminator values larger than typical only recommended to address EMI issues. Termination value should be uniform across net class. Min 0 0 0 0 22 22 10 Typ Max 10 Zo Zo Zo Unit Notes See Note See Notes (2) (3) , See Notes (2) (3) , See Notes (2) (3) ,
(1) (1)
, , ,
(1)
(1)
145
AM3517, AM3505
6.4.2.2.10 VREF Routing VREF is used as a reference by the input buffers of the DDR2 memories as well as the AM3517/05 . VREF is intended to be half of the DDR2 power supply voltage and should be created using a resistive divider as shown in Figure 6-23. Other methods of creating VREF are not recommended. Figure 6-27 shows the layout guidelines for VREF.
VREF Bypass Capacitor DDR2 Device A1 VREF Nominal Minimum Trace Width is 20 Mils Microprocessor
A1
Neck down to minimum in BGA escape regions is acceptable. Narrowing to accomodate via congestion for short distances is also acceptable. Best performance is obtained if the width of VREF is maximized.
Figure 6-27. VREF Routing and Topology 6.4.2.2.11 DDR2 CLK and ADDR_CTRL Routing Figure 6-28 shows the topology of the routing for the CLK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.
A1
T A C
A1
Figure 6-28. CLK and ADDR_CTRL Routing and Topology
146
DDR2 Controller
Microprocessor
AM3517, AM3505
Table 6-31. CLK and ADDR_CTRL Routing Specification

No 1 2 3 4 5 6 7 8 9 10 11 Parameter Center to center DQS-DQSN spacing CK differential pair Skew Length Mismatch (2) CLKB to CLKC Skew Length Mismatch Center to center CLK to other DDR2 trace spacing CK/ADDR_CTRL nominal trace length ADDR_CTRL to CLK Skew Length Mismatch ADDR_CTRL to ADDR_CTRL Skew Length Mismatch Center to center ADDR_CTRL to other DDR2 trace spacing Center to center ADDR_CTRL to other ADDR_CTRL trace spacing ADDR_CTRL A to B, ADDR_CTRL A to C, Skew Length Mismatch ADDR_CTRL B to C Skew Length Mismatch 4w 3w 100 100 4w CACLM-50 CACLM Min Typ Max 2w 25 25
(1) Unit Notes

(1)
Mils Mils
See Note
See Note CACLM+50 100 100 Mils Mils Mils See Note See Note Mils Mils See Note See Note
(3) (4)
(3)
(3)
(1)
(1) (2) (3) (4)
Series terminator, if used, should be located closest to AM3517/05 . Differential impedance should be 100-ohms. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. CACLM is the longest Manhattan distance of the CLK and ADDR_CTRL net classes.
Figure 6-29 shows the topology and routing for the DQS and Dx net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended.
T A1 T E0 E1
T A1 E2 T E3
Figure 6-29. DQS and Dx Routing and Topology
DDR2 Controller
Microprocessor
147
AM3517, AM3505
SPRS550C OCTOBER 2009 REVISED MARCH 2011 www.ti.com (2)
Table 6-32. DQS and Dx Routing Specification (1)

No. 1 2 3 4 5 6 7 8 (1) (2) (3) (4) (5) (6) (7) Parameter Center to center DQS-DQSN spacing DQS E differential pair Skew Length Mismatch (3) Center to center DQS to other DDR2 trace spacing DQS/Dx nominal trace length Dx to DQS Skew Length Mismatch Dx to Dx Skew Length Mismatch Center to center Dx to other DDR2 trace spacing Center to Center Dx to other Dx trace spacing 4w 3w 4w Min Typ
Max 2w 25
Unit Mils
Notes
See Note Mils Mils Mils See Notes

(5)
(4) (2)
DQLM-50 DQLM DQLM+ 50 100 100
See Note See Note See Notes

(6)
(5) (5) (4)
, ,
See Notes
(4)
(7)
"Dx" indicates a data line. E indicates length of DQS differential pair or Dx signal. Series terminator, if used, should be located closest to DDR. Differential impedance should be 100-ohms. Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion. There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1. Dx's from other DQS domains are considered other DDR2 trace. DQLM is the longest Manhattan distance of each of the DQS and Dx net classes.
Figure 6-30 shows the routing for the SDRC_STRBENx net classes. Table 6-33 contains the routing specification. SDRC_STRBENx net classes should be shielded from or routed on different layers than the DQx net classes.
FL
T
A1
Figure 6-30. SDRC_STRBENx Routing
148
FH
A1
DDR2 Controller
Microprocessor
AM3517, AM3505
Table 6-33. SDRC_STRBENx Routing Specification (1) (2)

No. 1 3 4 5 (1) (2) (3) (4) (5) Parameter SDRC_STRBEN0 Length F SDRC_STRBEN1 Length F Center to center SDRC_STRBENx to any other trace spacing DQS/Dx nominal trace length SDRC_STRBENx Skew 4w DQLM-50 DQLM DQLM+50 100 Mils Mils See Note
(5)
Min
Typ CKB0B1 CKB0B2
Max
Unit
Notes See Note See Note

(3) (4)
STRBENx termination resistors should be placed close to AM3517/05 STRBENx signal (not close to STRBEN_DLYx signal). Ensure signal velocities across different layers are taken into account when calculating STRBENx length. For example, if DQS0 and DSQ1 are 1inch each, and DQS0 is on a layer that is 10% faster, use 1.1inch as the length for DQS0. CKB0B1 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS0 and DQS1) plus the average length of the DQS0 and DQS1 differential pairs. CKB0B2 is the sum of the length of the CLK (the portion that goes to the memory associated with DQS2 and DQS3) plus the average length of the DQS2 and DQS3 differential pairs. Skew from CKB0B1 or CKB0B2.
6.4.2.2.12 On Die Termination (ODT) ODT should only be used with 1 chip select as shown in Figure 6-31. If using sdrc_cs0 and sdrc_cs1, sdrc_odt should not be used. ODT signals should be tied off at the memory.
sdrc_cs0 sdrc_odt CS# DDR2 ODT
Microprocessor
CS# ODT DDR2
vo DDR2 on One Chip Select
Figure 6-31. ODT Connection Using One Chip select (sdrc_cs0)
149
AM3517, AM3505
6.5 6.5.1
Video Interfaces Video Processing Subsystem (VPSS)

The Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input interface for external imaging peripherals (i.e., image sensors, video decoders, etc.).
6.5.1.1
Video Processing Front End (VPFE)
The Video Processing Front-End (VPFE) controller receives input video/image data from external capture devices and stores it to external memory which is transferred into the external memory via a built in DMA engine. An internal buffer block provides a high bandwidth path between the VPSS module and the external memory. The Cortex-A8 will process the image data based on application requirements.
150
AM3517, AM3505
6.5.1.1.1 Video Processing Front End (VPFE) Timing The following tables assume testing over recommended operating conditions. Table 6-34. VPFE Timing Requirements
NO. VF1 VF2 VF3 VF4 VF5 VF6 VF7 VF8 VF9 VF10 VF11 tc(VDIN_CLK) tsu(VDIN_D-VDIN_CLK) tsu(VDIN_HD-VDIN_CLK) tsu(VDIN_VD-VDIN_CLK) tsu(VDIN_WEN-VDIN_CLK) tsu(C_FLD-VDIN_CLK) th(VDIN_CLK-VDIN_D) th(VDIN-HD-VDIN_CLK) th(VDIN_VD-VDIN_CLK) th(VDIN_WEN-VDIN_CLK) th(C_FLD-VDIN_CLK) PARAMETER Cycle time, pixel clock input, VDIN_CLK Setup time, VDIN_D to VDIN_CLK rising edge Setup time, VDIN_HD to VDIN_CLK rising edge Setup time, VDIN_VD to VDIN_CLK rising edge Setup time, VDIN_WEN to VDIN_CLK rising edge Setup time, VDIN_FIELD to VDIN_CLK rising edge Hold time, VDIN_D valid after VDIN_CLK rising edge Hold time, VDIN_HD to VDIN_CLK rising edge Hold time, VDIN_VD to VDIN_CLK rising edge Hold time, VDIN_WEN to VDIN_CLK rising edge Hold time, VDIN_FIELD to VDIN_CLK rising edge 1.8V, 3.3V MIN 13.33 3.5 3.5 3.5 3.5 3.5 2.5 2.5 2.5 2.5 2.5 MAX 100 UNIT ns ns ns ns ns ns ns ns ns ns ns
Table 6-35. VPFE Output Switching Characteristics

NO. VF12 VF13 VF14 VF15 VF16 VF17 td(VDIN_HD-VDIN_CLK) td(VDIN_VD-VDIN_CLK) td(VDIN_WEN-VDIN_CLK) toh(VDIN_HD-VDIN_CLK) toh(VDIN_VD-VDIN_CLK) toh(C_FLD-VDIN_CLK) PARAMETER Output delay time, VDIN_HD to CLK rising edge Output delay time, VDIN_VD to CLK rising edge Output delay time, VDIN_WEN to CLK rising edge Output hold time, VDIN_HD to CLK rising edge Output hold time, VDIN_VD to CLK rising edge Output hold time, VDIN_FLD to CLK rising edge
VF1 VDIN_CLK (Falling Edge) VDIN_CLK (Rising Edge) VF2 VDIN_D[xx] VDIN_HD, VDIN_VD, VDIN_FIELD VDIN_WEN
SPRS550-001
1.8V, 3.3V MIN MAX 10 10 10 0.5 0.5 0.5 UNIT ns ns ns ns ns ns
VF7
VF7
VF3, VF4, VF6 VF5
VF8, VF9, VF11 VF10
Figure 6-32. VPFE0 Input Timings
151
AM3517, AM3505
VDIN_CLK (Falling Edge) VDIN_CLK (Rising Edge) VF12, VF13, VF14 VDIN_HD, VDIN_VD, VDIN_FIELD VF15, VF16, VF17 VF12, VF13, VF14 VF15, VF16, VF17
SPRS550-002
Figure 6-33. VPFE Output Timings

VF18 VDIN_HD (Falling Edge) VDIN_HD (Rising Edge) VF19
VDIN_D[xx]
SPRS550-003
VF20
Figure 6-34. VPFE Input Timings With VDIN0_HD as Pixel Clock
6.5.2
Display Subsystem (DSS)

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller. It can be used in two configurations: LCD display support in: Bypass mode (RFBI module bypassed) RFBI mode (through RFBI module) TV display support (not discussed in this document because of its analog IO signals) The two display supports can be active at the same time.
6.5.2.1
LCD Display Support in Bypass Mode
Two types of LCD panel are supported: Thin film transistor (TFT) or active matrix technology Supertwisted nematic (STN) or passive matrix technology Both configurations are discussed in the following paragraphs. 6.5.2.1.1 LCD Display in TFT Mode Table 6-36 assumes testing over the recommended operating conditions (see Figure 6-35). Table 6-36. LCD Display Interface Switching Characteristics in TFT Mode (1)
NO. DL0 DL1 DL2 DL3 td(PCLKA-HSYNCT) td(PCLKA-VSYNCT) td(PCLKA-ACBIASA) td(PCLKA-DATAV) PARAMETER Delay time, dss_pclk active edge to dss_hsync transition Delay time, dss_pclk active edge to dss_vsync transition Delay time, dss_pclk active edge to dss_acbias active level Delay time, dss_pclk active edge to dss_data bus valid 1.8V, 3.3V MIN -4.215 -4.215 -4.215 -4.215 MAX 4.215 4.215 4.215 4.215 ns ns ns ns UNIT
(1) 152
The capacitive load is equivalent to 25 pF. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Table 6-36. LCD Display Interface Switching Characteristics in TFT Mode(1) (continued)
NO. DL4 DL5 tc(PCLK) tw(PCLK) cload (2) PARAMETER Cycle time (2), dss_pclk Pulse duration, dss_pclk low or high Load capacitance 1.8V, 3.3V MIN 13.468 6.06 7.46 25 MAX ns ns pF UNIT
The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register.
DL5 DL4 dss_pclk DL1 dss_vsync DL0 dss_hsync DL2 dss_acbias DL3 dss_data[23:0]
030-061
Figure 6-35. LCD Display in TFT Mode(1) (2) (3) (4)

(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) The pixel clock frequency is programmable. (3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. (4) For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0].
6.5.2.1.2 LCD Display in STN Mode Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-36). Table 6-37. LCD Display Interface Switching Characteristics in STN Mode (1)
NO. DL3 DL4 DL5 td(PCLKA-DATAV) tc(PCLK) tw(PCLK) cload (1) (2) (3) (4) PARAMETER MIN Delay time, dss_pclk active edge to dss_data bus valid Cycle time (4), dss_pclk Pulse duration, dss_pclk low or high Load capacitance -4.21 22.73 10.23 12.5 40 1.8V, 3.3V MAX 6.9 ns ns ns pF
(2) (3)
UNIT
The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low. The capacitive load is equivalent to 40 pF. For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0]. The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the DISPC_DIVISOR register.
153
AM3517, AM3505
DL5 DL4 dss_pclk
dss_vsync
dss_hsync
dss_acbias DL3 dss_data[23:0]

030-062
Figure 6-36. LCD Display in STN Mode(1) (2) (3) (4) (5)
(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins. (2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk. (3) dss_vsync width must be programmed to be as small as possible. (4) The pixel clock frequency is programmable. (5) For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0].
154
AM3517, AM3505
6.6 6.6.1
Serial Communications Interfaces Multichannel Buffered Serial Port (McBSP) Timing

There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct serial interface between the AM3517/05 device and other devices in a system such as other application devices or codecs. It can accommodate a wide range of peripherals and clocked frame-oriented protocols (I2S, PCM, and TDM) due to its high level of versatility. The McBSP1-5 modules may support two types of data transfer at the system level: The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge and captured on the same edge (one clock period later). The half-cycle mode, for which one half clock period is used to transfer the data, generated on one edge and captured on the opposite edge (one half clock period later). Note that a new data is generated only every clock period, which secures the required hold time. The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be configured accordingly with the external peripheral (activation edge capability) and the type of data transfer required at the system level. The AM3517/05 McBSP1-5 timing characteristics are described for both rising and falling activation edges. McBSP1 supports: 6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins. 4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are internally looped back via software configuration, respectively, to the clkr and fsr internal signals for data receive. McBSP2, 3, 4, and 5 support only the 4-pin mode. The following sections describe the timing characteristics for applications in normal mode (that is, AM3517/05 McBSPx connected to one peripheral) and TDM applications in multipoint mode.
6.6.1.1
McBSP in Normal Mode
The following tables assume=testing over the recommended operating conditions. Table 6-38. McBSP Timing Conditions
TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD (1) Maximum value. Output load capacitance 10 pF Input signal rise time Input signal fall time 1.8V, 3.3 V VALUE 2 (1) 2 ns ns UNIT
Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration

PARAMETER MIN tC(CLK) Cycle Time, mcbsp1_clkr/mcbspx_clkx
(1)
VDDSHV = 1.8V, 3.3V MAX 20.83
UNIT ns
tW(CLKH)
Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high (1)
0.5*P (2)
0.5*P (2)
ns
(1) (2)
In mcbspx, x identifies the McBSP number; 1, 2, 4, or 5. P = mcbsp1_clkr / mcbspx_clkx clock period. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 155
AM3517, AM3505
Table 6-39. McBSP1,2,4,5 Output Clock Pulse Duration (continued)

PARAMETER tW(CLKL) Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low (1) Duty cycle error, mcbsp1_clkr / mcbspx_clkx (1) VDDSHV = 1.8V, 3.3V 0.5*P (2) 0.5*P (2) UNIT ns
tdc(CLK)
-0.75
0.75
ns
Table 6-40. McBSP3 Output Clock Pulse Duration

PARAMETER MIN tC(CLK) tW(CLKH) tW(CLKL) tdc(CLK) (1) Cycle time, mcbsp3_clkx Typical pulse duration, mcbsp3_clkx high Typical pulse duration, mcbsp3_clkx low Duty cycle error, mcbsp3_clkx 31.25 0.5*P
(1)
VDDSHV = 1.8V, 3.3V MAX
UNIT ns
0.5*P
(1)
ns ns ns
0.5*P (1) -0.75
0.5*P (1) 0.75
P = mcbsp3_clkx clock period
6.6.1.1.1 McBSP1 The following tables show the timing requirements and switching characteristics for McBSP1. Table 6-41. McBSP1 Timing Requirements - Rising Edge and Receive Mode
No. PARAMETER MIN B3 tsu(DRVCLKAE) Setup time, mcbsp1_dr valid before mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKAEDRV) Hold time, mcbsp1_dr valid after mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FSVCLKAE) Setup time, mcbsp1_fsr / mcbsp1_fsx valid before mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Slave Full Cycle Slave 5.0 5.2 4.0 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV=3.3V MAX MIN 5.0 5.2 4.0 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV=1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
B6
th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbsp1_fsx valid after mcbsp1_clkr / mcbsp1_clkx active edge
Half Cycle Slave Full Cycle Slave
0.5 1.0
0.5 1.0
ns ns
156
AM3517, AM3505
Table 6-42. McBSP1 Switching Characteristics - Rising Edge and Receive Mode
No. PARAMETER MIN B2 td(CLKAE-FSV) Delay time, mcbsp1_clkr active edge to mcbsp1_fsr / mcbsp1_fsx valid 0.2 VDDSHV=3.3V MAX 14.8 MIN 0.2 VDDSHV=1.8V MAX 14.8 ns UNIT
Table 6-43. McBSP1 Timing Requirements - Rising Edge and Transmit Mode
No. PARAMETER MIN B5 tsu(FSXVCLKXAE) Setup time, mcbsp1_fsx valid before mcbsp1_clkx active edge Hold time, mcbsp1_fsx valid after mcbsp1_clkx active edge Full Cycle Slave Half Cycle Slave Full Cycle Slave Half Cycle Slave 5.2 4.2 VDDSHV = 3.3V MAX MIN 4.7 3.7 VDDSHV = 1.8V MAX ns ns UNIT
B6
th(CLKXAEFSXV)
5.2 1.0
4.7 0.5
ns ns
Table 6-44. McBSP1 Switching Characteristics - Rising Edge and Transmit Mode
No. PARAMETER MIN B2 td(CLKXAEFSXV) Delay time, mcbsp1_clkx active edge to mcbsp1_fsx valid Delay time, mcbsp1_clkx active edge to mcbsp1_dx valid Master Slave 0.2 VDDSHV = 3.3V MAX 14.8 MIN 0.7 VDDSHV = 1.8V MAX 14.8 ns UNIT
B8
td(CLKXAEDXV)
0.6 0.6
14.8 14.8
0.6 0.6
14.8 14.8
ns ns
Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER MIN B3 tsu(DRVCLKAE) Setup time, mcbsp1_dr valid before mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKAEDRV) Hold time, mcbsp1_dr valid after mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FSVCLKAE) Setup time, mcbsp1_fsr / mcbsp1_fsx valid before mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Slave Full Cycle Slave 5.0 5.2 4.0 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 3.3V MAX MIN 5.0 5.2 4.0 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
157
AM3517, AM3505
Table 6-45. McBSP1 Timing Requirements - Falling Edge and Receive Mode (continued)
No. B6 PARAMETER th(CLKAE-FSV) Hold time, mcbsp1_fsr / mcbsp1_fsx valid after mcbsp1_clkr / mcbsp1_clkx active edge Half Cycle Slave Full Cycle Slave 0.5 1.0 VDDSHV = 3.3V 0.5 1.0 VDDSHV = 1.8V UNIT ns ns
Table 6-46. McBSP1 Switching Characteristics - Falling Edge and Receive Mode
No. PARAMETER MIN B2 td(CLKAE-FSV) Delay time, mcbsp1_clkr / mcbsp1_clkx active edge to mcbsp1_fsr / mcbsp1_fsx valid 0.2 VDDSHV = 3.3V MAX 14.8 MIN 0.7 VDDSHV = 1.8V MAX 14.8 ns UNIT
Table 6-47. McBSP1 Timing Requirements - Falling Edge and Transmit Mode
No. PARAMETER MIN B5 tsu(FSXVCLKXAE) Setup time, mcbsp1_fsx valid before mcbsp1_clkx active edge Hold time, mcbsp1_fsx valid after mcbsp1_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave Full Cycle Slave 5.2 4.2 VDDSHV = 3.3V MAX MIN 5.2 4.2 VDDSHV = 1.8V MAX ns ns UNIT
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
Table 6-48. McBSP1 Switching Characteristics - Falling Edge and Transmit Mode
B8
td(CLKXAEDXV)
0.6 0.6
14.8 14.8
0.6 0.6
14.8 14.8
ns ns
158
AM3517, AM3505
No. PARAMETER MIN B3 tsu(DRVCLKXAE) Setup time, mcbsp2_dr valid before mcbsp2_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKXAEDRV) Hold time, mcbsp2_dr valid after mcbsp2_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FSVCLKXAE) Setup time, mcbsp2_fsx valid before mcbsp2_clkx active edge Hold time, mcbsp2_fsx valid after mcbsp2_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave Full Cycle Slave 5.0 5.2 4.2 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 3.3V MAX MIN 5.0 5.2 4.2 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
B6
th(CLKXAEFSV)
5.2 1.0
5.2 1.0
ns ns
No. PARAMETER MIN B2 td(CLKXAEFSXV) Delay time, mcbsp2_clkx active edge to mcbsp2_fsx valid 0.2 VDDSHV = 3.3V MAX 14.8 MIN 0.2 VDDSHV = 1.8V MAX 14.8 ns UNIT
B6
th(CLKXAEFSXV)
5.2 1.0
4.7 0.5
ns ns
159
AM3517, AM3505
B8
td(CLKXAEDXV)
0.6 0.6
14.8 14.8
0.6 0.6
14.8 14.8
ns ns
No. PARAMETER MIN B3 tsu(DRVCLKXAE) Setup time, mcbsp2_dr valid before mcbsp2_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKXAEDRV) Hold time, mcbsp2_dr valid after mcbsp2_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FSXVCLKXAE) Setup time, mcbsp2_fsx valid before mcbsp2_clkx active edge Hold time, mcbsp2_fsx valid after mcbsp2_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave Full Cycle Slave 5.0 5.2 4.2 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 3.3V MAX MIN 5.0 5.2 4.2 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
160
AM3517, AM3505
No. PARAMETER MIN B2 B8 td(CLKXAEFSXV) td(CLKXAEDXV) Delay time, mcbsp2_clkx active edge to mcbsp2_fsx valid Delay time, mcbsp2_clkx active edge to mcbsp2_dx valid Master Slave 0.2 0.6 0.6 VDDSHV = 3.3V MAX 14.8 14.8 14.8 MIN 0.2 0.6 0.6 VDDSHV = 1.8V MAX 14.8 14.8 14.8 ns ns ns UNIT
6.6.1.1.3 McBSP3 6.6.1.1.3.1 McBSP3 Multiplexed on McBSP3 Pins The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on McBSP3 pins. Note: All timings apply only to Set #1- multiplexing on mcbsp3 pins. Table 6-57. McBSP3 (Set #1) Timing Requirements - Rising Edge and Receive Mode
B6
th(CLKXAEFSV)
7.7 1.0
7.7 1.0
ns ns
Table 6-58. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Receive Mode
161
AM3517, AM3505
Table 6-59. McBSP3 (Set #1) Timing Requirements - Rising Edge and Transmit Mode
B6
th(CLKXAEFSXV)
7.7 1
7.7 1
ns ns
Table 6-60. McBSP3 (Set #1) Switching Characteristics - Rising Edge and Transmit Mode
Table 6-61. McBSP3 (Set #1) Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER MIN tsu(DRVCLKXAE) Setup time, mcbsp3_dr valid before mcbsp3_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave th(CLKXAEDRV) Hold time, mcbsp3_dr valid after mcbsp3_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FXSVCLKXAE) Setup time, mcbsp3_fsx valid before mcbsp3_clkx active edge Hold time, mcbsp3_fsx valid after mcbsp3_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave Full Cycle Slave 7.5 7.7 5.6 5.8 8.3 7.7 1.5 0.9 7.7 5.8 VDDSHV = 3.3V MAX MIN 7.5 7.7 5.6 5.8 8.3 7.7 1.5 0.9 7.7 5.8 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
B6
th(CLKXAEFSXV)
7.7 1.0
7.7 1.0
ns ns
Table 6-62. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Receive Mode
162
AM3517, AM3505
Table 6-63. McBSP3 (Set #1) Timing Requirements - Falling Edge and Transmit Mode
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
Table 6-64. McBSP3 (Set #1) Switching Characteristics - Falling Edge and Transmit Mode
6.6.1.1.3.2 McBSP3 Multiplexed on UART2 or McBSP1 Pins The following tables show the timing conditions and switching characteristics for McBSP3 multiplexed on UART2 or McBSP1 pins. Note: These timings only apply to Set #2 (multiplexing mode on uart2 pins) and Set #3 (multiplexing on mcbsp1 pins). Table 6-65. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Receive Mode
B6
th(CLKXAEFSV)
5.2 1.0
5.2 1.0
ns ns
163
AM3517, AM3505
Table 6-66. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Receive Mode
Table 6-67. McBSP3 (Sets #2 and #3) Timing Requirements - Rising Edge and Transmit Mode
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
Table 6-68. McBSP3 (Sets #2 and #3) Switching Characteristics - Rising Edge and Transmit Mode
Table 6-69. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Receive Mode
No. PARAMETER MIN B3 tsu(DRVCLKXAE) Setup time, mcbsp3_dr valid before mcbsp3_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKXAEDRV) Hold time, mcbsp3_dr valid after mcbsp3_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FXSVCLKXAE) Setup time, mcbsp3_fsx valid before mcbsp3_clkx active edge Hold time, mcbsp3_fsx valid after mcbsp3_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave Full Cycle Slave 5.0 5.2 4.2 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 3.3V MAX MIN 5.0 5.2 4.2 4.2 5.8 5.2 1.5 0.9 5.2 4.2 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
164
AM3517, AM3505
Table 6-70. McBSP3 (Sets #2 and #3) Switching Characteristics - Falling Edge and Receive Mode
Table 6-71. McBSP3 (Sets #2 and #3) Timing Requirements - Falling Edge and Transmit Mode
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
Table 6-72. McBSP3 (Sets #2 and #3) Switching Characteristics - Falling Edge and Transmit Mode
No. PARAMETER MIN B2 B8 td(CLKXAEFSXV) td(CLKXAEDXV) Delay time, mcbsp3_clkx active edge to mcbsp3_fsx valid Delay time, mcbsp3_clkx active edge to mcbsp3_dx valid Master 0.2 0.6 VDDSHV = 3.3V MAX 14.8 14.8 MIN 0.2 0.6 VDDSHV = 1 .8V MAX 14.8 14.8 ns ns UNIT
Slave
0.6
14.8
0.6
14.8
ns
No. PARAMETER MIN B3 tsu(DRVCLKXAE) Setup time, mcbsp4_dr valid before mcbsp4_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKXAEDRV) Hold time, mcbsp4_dr valid after mcbsp4_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FSVCLKXAE) Setup time, mcbsp4_fsx valid before mcbsp4_clkx active edge Half Cycle Slave Full Cycle Slave 7.5 7.7 3.2 4.2 7.7 5.2 1.5 0.9 7.7 4.2 VDDSHV = 3.3V MAX MIN 7.5 7.7 3.2 4.2 7.7 5.2 1.5 0.9 7.7 4.2 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
165
AM3517, AM3505
Table 6-73. McBSP4 Timing Requirements - Rising Edge and Receive Mode (continued)
No. B6 th(CLKXAEFSV) PARAMETER Hold time, mcbsp4_fsx valid after mcbsp4_clkx active edge Half Cycle Slave Full Cycle Slave 5.2 1.0 VDDSHV = 3.3V 5.2 1.0 VDDSHV = 1.8V UNIT ns ns
B6
th(CLKXAEFSXV)
1.0 1.0
1.0 1.0
ns ns
B8
td(CLKXAEDXV)
0.6 0.6
16.6 17.3
0.6 0.6
16.6 17.3
ns ns
No. PARAMETER MIN B3 tsu(DRVCLKXAE) Setup time, mcbsp4_dr valid before mcbsp4_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave 7.5 7.7 5.6 5.8 VDDSHV = 3.3V MAX MIN 7.5 7.7 5.6 5.8 VDDSHV = 1.8V MAX ns ns ns ns UNIT
166
AM3517, AM3505
Table 6-77. McBSP4 Timing Requirements - Falling Edge and Receive Mode (continued)
No. B4 th(CLKXAEDRV) PARAMETER Hold time, mcbsp4_dr valid after mcbsp4_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FXSVCLKXAE) Setup time, mcbsp4_fsx valid before mcbsp4_clkx active edge Hold time, mcbsp4_fsx valid after mcbsp4_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave 7.7 5.2 1.5 0.9 7.7 5.8 VDDSHV = 3.3V 7.7 5.2 1.5 0.9 7.7 5.8 VDDSHV = 1.8V UNIT ns ns ns ns ns ns
B6
th(CLKXAEFSXV)
5.2
5.2
ns
Full Cycle Slave
1.0
1.0
ns
B6
th(CLKXAEFSXV)
5.2 1.0
5.2 1.0
ns ns
167
AM3517, AM3505
6.6.1.1.5 McBSP5 The following tables show the timing conditions and switching characteristics for McBSP5. Table 6-81. McBSP5 Timing Requirements - Rising Edge and Receive Mode
B6
th(CLKXAEFSV)
7.7 1.0
7.7 1.0
ns ns
B6
th(CLKXAEFSXV)
7.7 1.0
7.7 1.0
ns ns
168
AM3517, AM3505
Table 6-84. McBSP5 Switching Characteristics - Rising Edge and Transmit Mode (continued)
No. B8 td(CLKXAEDXV) PARAMETER Delay time, mcbsp5_clkx active edge to mcbsp5_dx valid Master Slave 0.6 0.6 VDDSHV = 3.3V 14.8 14.8 0.6 0.6 VDDSHV = 1.8V 14.8 14.8 UNIT ns ns
No. PARAMETER MIN B3 tsu(DRVCLKXAE) Setup time, mcbsp5_dr valid before mcbsp5_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B4 th(CLKXAEDRV) Hold time, mcbsp5_dr valid after mcbsp5_clkx active edge Half Cycle Master Half Cycle Slave Full Cycle Master Full Cycle Slave B5 tsu(FXSVCLKXAE) Setup time, mcbsp5_fsx valid before mcbsp5_clkx active edge Hold time, mcbsp5_fsx valid after mcbsp5_clkx active edge Half Cycle Slave Full Cycle Slave Half Cycle Slave Full Cycle Slave 7.5 7.7 5.6 5.8 8.3 7.7 1.5 0.9 7.7 5.8 VDDSHV = 3.3V MAX MIN 7.5 7.7 5.6 5.8 8.3 7.7 1.5 0.9 7.7 5.8 VDDSHV = 1.8V MAX ns ns ns ns ns ns ns ns ns ns UNIT
B6
th(CLKXAEFSXV)
7.7 1.0
7.7 1.0
ns ns
B6
th(CLKXAEFSXV)
7.7 1.0
7.7 1.0
ns ns
169
AM3517, AM3505
B8
td(CLKXAEDXV)
0.6 0.6
22.2 22.2
0.6 0.6
22.2 22.2
ns ns
6.6.1.1.6 McBSP in TDM Mode The following tables assume=testing over the recommended operating conditions. Table 6-89. McBSP Timing Conditions TDM in Multipoint Mode
PARAMETER DESCRIPTION MIN tr tf Cload Input signal rise time Input signal fall time Output load capacitance 1 1 VDDSHV = 1.8V or 3.3V MAX 8.5 8.5 40 ns ns pf UNIT
Table 6-90. McBSP Timing Requirements TDM in Multipoint Mode

INDEX PARAMETER DESCRIPTION MIN tw(CLKH) tw(CLKH) tw(CLKL) tdc(CLK) B3 B4 B5 B6 tsu(DRV-CLKAE) th(CLKAE-DRV) tsu(FSV-CLKAE) th(CLKAE-FSV) Cycle Time, mcbspx_clkx Typical Pulse duration, mcbspx_clkx high Typical Pulse duration, mcbspx_clkx low Duty cycle error, mcbspx_clkx Setup time, mcbspx_dr valid before mcbspx_clkx active edge Hold time, mcbspx_dr valid after mcbspx_clkx active edge Setup time, mcbspx_fsx valid before mcbspx_clkx active edge Hold time, mcbspx_fsx valid after mcbspx_clkx active edge 162.8 81.4 81.4 -8.14 9 2.4 9 2.4 8.14 VDDSHV = 1.8V or 3.3V MAX ns ns ns ns ns ns ns ns UNIT
Table 6-91. McBSP Switching Characteristics TDM in Multipoint Mode

INDEX PARAMETER DESCRIPTION MIN B8 td(CLKXAE-DXV) Delay time, mcbspx_clkx active edge to mcbspx_dx valid 0.6 VDDSHV = 1.8V or 3.3V MAX 16.8 ns UNIT
6.6.1.1.7 McBSP Timing Diagrams

mcbspx_clkr B2 mcbspx_fsr B3 mcbspx_dr D7 B4 D6 D5
030-068
B2
Figure 6-37. McBSP Rising Edge Receive Timing in Master Mode

170 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505

030-069
B6
Figure 6-38. McBSP Rising Edge Receive Timing in Slave Mode

mcbspx_clkx B2 mcbspx_fsx B8 mcbspx_dx D7 D6 D5
030-070
B2
Figure 6-39. McBSP Rising Edge Transmit Timing in Master Mode

030-071
B6
Figure 6-40. McBSP Rising Edge Transmit Timing in Slave Mode

030-072
B2
Figure 6-41. McBSP Falling Edge Receive Timing in Master Mode

030-073
B6
Figure 6-42. McBSP Falling Edge Receive Timing in Slave Mode

030-074
B2
Figure 6-43. McBSP Falling Edge Transmit Timing in Master Mode

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 171
AM3517, AM3505

030-075
B6
Figure 6-44. McBSP Falling Edge Transmit Timing in Slave Mode
172
AM3517, AM3505
6.6.2
Multichannel Serial Port Interface (McSPI) Timing

The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and any channel (n).
6.6.2.1
McSPI in Slave Mode
The following tables assume testing over the recommended operating conditions. Table 6-92. McSPI Interface Timing Requirements Slave Mode
NO. SS0 SS1 SS2 SS3 SS4 SS5 tc(CLK) tw(CLK) tsu(SIMOV-CLKAE) th(SIMOV-CLKAE) tsu(CS0V-CLKFE) th(CS0I-CLKLE) PARAMETER MIN Cycle time, mcspix_clk Pulse duration, mcspix_clk high or low Setup time, mcspix_simo valid before mcspix_clk active edge Hold time, mcspix_simo valid after mcspix_clk active edge Setup time, mcspix_cs0 valid before mcspix_clk first edge Hold time, mcspix_cs0 invalid after mcspix_clk last edge 41.67 18.75 4.2 4.6 13.8 13.8 22.92 1.8 V MAX MIN 41.67 11.25 4 3 7 9.17 3.3 V MAX ns ns ns ns ns ns UNIT
Table 6-93. McSPI Interface Switching Characteristics (1)

NO. SS6 SS7 (1) (2) (3) (4) td(CLKAE-SOMIV) td(CS0AE-SOMIV) PARAMETER MIN Delay time, mcspix_clk active edge to mcspix_somi shifted Delay time, mcspix_cs0 active edge to Modes 0 and 2 mcspix_somi shifted 1.8 1.8 V MAX 15.9 16.38
(2) (3) (4)
3.3 V MIN 2 MAX 16.5 15.9
UNIT ns ns
The capacitive load is equivalent to 20 pF. In mcspix, x is equal to 1, 2, 3, or 4. The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and capture input data.
173
AM3517, AM3505
Mode 0 & 2 mcspix_cs0(EPOL=1) SS0 SS4 mcspix_clk(POL=0) SS0 SS1 mcspix_clk(POL=1) SS2 SS3 mcspix_simo mcspix_somi Bit n-1 SS7 Bit n-1 Bit n-2 SS6 Bit n-2 Bit n-3 Bit n-4 Bit 0 Bit n-3 Bit n-4 Bit 0 SS1 SS5
Mode 1 & 3 mcspix_cs0(EPOL=1) SS0 SS1 mcspix_clk(POL=0) SS0 SS4 mcspix_clk(POL=1) SS3 SS2 mcspix_simo mcspix_somi Bit n-1 SS6 Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
030-076
SS1
SS5
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 6-45. McSPI Interface Transmit and Receive in Slave Mode(1) (2)
(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL. (2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.
6.6.2.2
McSPI in Master Mode
The following tables assume testing over the recommended operating conditions. Table 6-94. McSPI1, 2, and 4 Interface Timing Requirements Master Mode (1)
NO. SM2 SM3 (1) (2) tsu(SOMIV-CLKAE) th(SOMIV-CLKAE) PARAMETER MIN Setup time, mcspix_somi valid before mcspix_clk active edge Hold time, mcspix_somi valid after mcspix_clk active edge 2.56 2.93 1.8 V MAX MIN 4 4 3.3 V MAX ns ns
(2)
UNIT
The input timing requirements are given by considering a rise time and a fall time of 4 ns. In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3. n is equal to 0 for x equal to 4.
174
AM3517, AM3505
Table 6-95. McSPI1, 2, and 4 Interface Switching Characteristics Master Mode (1)
NO. SM0 SM1 SM4 SM5 tc(CLK) tj(CLK) tw(CLK) td(CLKAE-SIMOV) td(CSnA-CLKFE) PARAMETER MIN Cycle time, mcspix_clk Cycle jitter (4), mcspix_clk Pulse duration, mcspix_clk high or low Delay time, mcspix_clk active edge to mcspix_simo shifted Delay time, mcspix_csi active to mcspix_clk first edge Modes 1 and 3 Modes 0 and 2 SM6 td(CLKLE-CSnI) Delay time, mcspix_clk last edge to mcspix_csi inactive Modes 1 and 3 Modes 0 and 2 SM7 (1) (2) (3) (4) (5) (6) (7) td(CSnAE-SIMOV) Delay time, mcspix_csi active edge to mcspix_simo shifted Modes 0 and 2 20.83 -200 0.45P -2.1 A (6) - 3.2 B (7) - 3.2 B (7) - 3.2 A (6) - 3.2 5
(5)
(2) (3)
1.8 V MAX 200 0.55P 5

(5)
3.3 V MIN 20.83 -200 0.45P -3 A (6) - 3.0 B (7) -3.0 B (7) - 3.0 A (6) - 3.0 5
(5)
UNIT MAX ns 200 ps

(5)
0.55P 6 6 6
ns ns ns ns ns ns ns
Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or 2, and 20 pF for spi4_clk and spi4_simo signals. In mcspix, x is equal to 1, 2, 3, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 3. n is equal to 0 for x equal to 4. The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all software configurable. Maximum cycle jitter supported by mcspix_clk input clock. P = mcspix_clk clock period Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bitfield of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference Guide [literature number SPRUFV6]. B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference Guide [literature number SPRUFV6].
The following tables assume testing over the recommended operating conditions. Table 6-96. McSPI 3 Interface Timing Requirements Master Mode (1)
NO. SM2 SM3 (1) (2) tsu(SOMIV-CLKAE) th(SOMIV-CLKAE) PARAMETER MIN Setup time, mcspi3_somi valid before mcspi3_clk active edge Hold time, mcspi3_somi valid after mcspi3_clk active edge 2.5 2.89 1.8 V MAX MIN 4 4 3.3 V MAX ns ns
(2)
UNIT
The input timing requirements are given by considering a rise time and a fall time of 4 ns. In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched is all software configurable.
175
AM3517, AM3505
SPRS550C OCTOBER 2009 REVISED MARCH 2011 www.ti.com (2) (3)
Table 6-97. McSPI3 Interface Switching Characteristics Master Mode (1)

NO. SM0 SM1 SM4 SM5 tc(CLK) tj(CLK) tw(CLK) td(CLKAE-SIMOV) td(CSnA-CLKFE) PARAMETER MIN Cycle time, mcspix_clk Cycle jitter (4) Pulse duration, mcspix_clk high or low Delay time, mcspix_clk active edge to mcspix_simo shifted Delay time, mcspix_csi active Modes 1 to mcspix_clk first edge and 3 Modes 0 and 2 SM6 td(CLKLE-CSnI) Delay time, mcspix_clk last edge to mcspix_csi inactive Modes 1 and 3 Modes 0 and 2 SM7 (1) (2) (3) (4) (5) (6) (7) td(CSnAE-SIMOV) Delay time, mcspix_csi active Modes 0 edge to mcspix_simo shifted and 2 41.67 -200 0.45P -2.1 A (6) - 4.4 B (7) - 4.4 B (7) - 4.4 A (6) - 4.4 11.3
(5)
1.8 V MAX 200 0.55P

(5)
3.3 V MIN 41.67 -200 0.45P -3 A (6) - 3.0 B (7) - 3.0 B (7) - 3.0 A (6) - 3.0 5 6 6
(5)
UNIT MAX ns 200 0.55P

(5)
ps ns ns ns ns ns ns ns
11.3
The capacitive load is equivalent to 20 pF. In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and mcspi3_somi is latched are all software configurable. This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and capture input data. Maximum cycle jitter supported by mcspix_clk input clock. P = mcspix_clk clock period. Case P = 20.8 ns, A = (TCS + 0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference Guide [literature number SPRUFV6]. B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the Device Multichannel Serial Port Interface (McSPI) Reference Guide [literature number SPRUFV6].
176
AM3517, AM3505
mcspix_csn(EPOL=1)
Mode 0 & 2 SM0 SM5 SM1 SM0 SM1 SM6
mcspix_clk(POL=0)
mcspix_clk(POL=1) SM7 mcspix_simo Bit n-1 SM2 SM3 mcspix_somi Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0 SM4 Bit n-2 Bit n-3 Bit n-4 Bit 0
Mode 1 & 3 mcspix_csn(EPOL=1) SM0 SM1 mcspix_clk(POL=0) SM0 SM5 mcspix_clk(POL=1) SM4 mcspix_simo Bit n-1 SM2 SM3 mcspix_somi Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
030-077
SM1
SM6
Bit n-2
Bit n-3
Bit 1
Bit 0
Figure 6-46. McSPI Interface Transmit and Receive in Master Mode(1) (2) (3)
(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL. (2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL. (3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.
177
AM3517, AM3505
6.6.3
Multiport Full-Speed Universal Serial Bus (USB) Interface

The AM3517/05 microprocessor provides three USB ports working in full- and low-speed data transactions (up to 12Mbit/s). Connected to either a serial link controller or a serial PHY (PHY interface modes) it supports: 6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode 4-pin bidirectional mode 3-pin bidirectional mode
6.6.3.1
Multiport Full-Speed Universal Serial Bus (USB) Unidirectional Standard 6-pin Mode
The following tables assume testing over the recommended operating conditions. Table 6-98. Low-/Full-Speed USB Timing Conditions Unidirectional Standard 6-pin Mode
TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD Output load capacitance 15.0 pF Input signal rise time Input signal fall time 2.0 2.0 ns ns 1.8V, 3.3V UNIT
Table 6-99. Low-/Full-Speed USB Timing Requirements Unidirectional Standard 6-pin Mode
NO. FSU1 FSU2 FSU3 FSU4 td(Vp,Vm) td(Vp,Vm) td(RCVU0) td(RCVU1) PARAMETER Time duration, mmx_rxdp and mmx_rxdm low together during transition Time duration, mmx_rxdp and mmx_rxdm high together during transition Time duration, mmx_rrxcv undefine during a single end 0 (mmx_rxdp and mmx_rxdm low together) Time duration, mmx_rxrcv undefine during a single end 1 (mmx_rxdp and mmx_rxdm high together) 1.8V, 3.3V MIN MAX 14.0 8.0 14.0 8.0 ns ns ns ns UNIT
Table 6-100. Low-/Full-Speed USB Switching Characteristics Unidirectional Standard 6-pin Mode
NO. FSU5 FSU6 FSU7 FSU8 FSU9 td(TXENL-DATV) td(TXENL-SE0V) ts(DAT-SE0) td(DATI-TXENH) td(SE0I-TXENH) tR(do) tF(do) tR(do) tF(do) tR(do) tF(do) PARAMETER Delay time, mmx_txen_n low to mmx_txdat valid Delay time, mmx_txen_n low to mmx_txse0 valid Skew between mmx_txdat and mmx_txse0 transition Delay time, mmx_txdat invalid to mmx_txen_n high Delay time, mmx_txse0 invalid to mmx_txen_n high Rise time, mmx_txen_n Fall time, mmx_txen_n Rise time, mmx_txdat Fall time, mmx_txdat Rise time, mmx_txse0 Fall time, mmx_txse0 81.8 81.8 4.0 4.0 4.0 4.0 4.0 4.0 1.8V, 3.3V MIN 81.8 81.8 MAX 84.8 84.8 1.5 ns ns ns ns ns ns ns ns ns ns ns UNIT
178
AM3517, AM3505
mmx_txen_n FSU5 mmx_txdat FSU6 mmx_txse0
Transmit FSU8
Receive
FSU7
FSU9
FSU1 mmx_rxdp FSU1 mmx_rxdm FSU3 mmx_rxrcv
FSU2
FSU2
FSU4
030-080
In mmx, x is equal to 0, 1, or 2.
Figure 6-47. Low-/Full-Speed USB Unidirectional Standard 6-pin Mode 6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) Bidirectional Standard 4-pin Mode
The following tables assume testing over the recommended operating conditions. Table 6-101. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 4-pin Mode
Table 6-102. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 4-pin Mode
NO. FSU10 FSU11 FSU12 FSU13 td(DAT,SE0) td(DAT,SE0) td(RCVU0) td(RCVU1) PARAMETER Time duration, mmx_txdat and mmx_txse0 low together during transition Time duration, mmx_txdat and mmx_txse0 high together during transition Time duration, mmx_rrxcv undefine during a single end 0 (mmx_txdat and mmx_txse0 low together) Time duration, mmx_rxrcv undefine during a single end 1 (mmx_txdat and mmx_txse0 high together) 1.8V, 3.3V MIN MAX 14.0 8.0 14.0 8.0 ns ns ns ns UNIT
Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode
NO. FSU14 FSU15 FSU16 FSU17 FSU18 td(TXENL-DATV) td(TXENL-SE0V) ts(DAT-SE0) td(DATV-TXENH) td(SE0V-TXENH) tR(txen) PARAMETER Delay time, mmx_txen_n low to mmx_txdat valid Delay time, mmx_txen_n low to mmx_txse0 valid Skew between mmx_txdat and mmx_txse0 transition Delay time, mmx_txdat invalid before mmx_txen_n high Delay time, mmx_txse0 invalid before mmx_txen_n high Rise time, mmx_txen_n 81.8 81.8 4.0 1.8V, 3.3V MIN 81.8 81.8 MAX 84.8 84.8 1.5 ns ns ns ns ns ns UNIT
179
AM3517, AM3505
Table 6-103. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 4-pin Mode (continued)
NO. tF(txen) tR(dat) tF(dat) tR(se0) tF(se0) PARAMETER Fall time, mmx_txen_n Rise time, mmx_txdat Fall time, mmx_txdat Rise time, mmx_txse0 Fall time, mmx_txse0 1.8V, 3.3V MIN MAX 4.0 4.0 4.0 4.0 4.0 ns ns ns ns ns UNIT
Transmit FSU17 FSU16 FSU18
Receive FSU10 FSU10 FSU12
FSU11 FSU11 FSU13

030-081
mmx_rxrcv
Figure 6-48. Low-/Full-Speed USB Bidirectional Standard 4-pin Mode 6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) Bidirectional Standard 3-pin Mode
The following tables assume testing over the recommended operating conditions. Table 6-104. Low-/Full-Speed USB Timing Conditions Bidirectional Standard 3-pin Mode
Table 6-105. Low-/Full-Speed USB Timing Requirements Bidirectional Standard 3-pin Mode
NO. FSU19 FSU20 td(DAT,SE0) td(DAT,SE0) PARAMETER Time duration, mmx_txdat and mmx_txse0 low together during transition Time duration, mmx_tsdat and mmx_txse0 high together during transition 1.8V, 3.3V MIN MAX 14.0 8.0 ns ns UNIT
Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode
NO. FSU21 FSU22 FSU23 td(TXENL-DATV) td(TXENL-SE0V) ts(DAT-SE0) PARAMETER Delay time, mmx_txen_n low to mmx_txdat valid Delay time, mmx_txen_n low to mmx_txse0 valid Skew between mmx_txdat and mmx_txse0 transition 1.8V, 3.3V MIN 81.8 81.8 MAX 84.8 84.8 1.5 ns ns ns UNIT
180
AM3517, AM3505
Table 6-106. Low-/Full-Speed USB Switching Characteristics Bidirectional Standard 3-pin Mode (continued)
NO. FSU24 FSU25 td(DATI-TXENH) td(SE0I-TXENH) tR(do) tF(do) tR(do) tF(do) tR(do) tF(do) PARAMETER Delay time, mmx_txdat invalid to mmx_txen_n high Delay time, mmx_txse0 invalid to mmx_txen_n high Rise time, mmx_txen_n Fall time, mmx_txen_n Rise time, mmx_txdat Fall time, mmx_txdat Rise time, mmx_txse0 Fall time, mmx_txse0 1.8V, 3.3V MIN 81.8 81.8 4.0 4.0 4.0 4.0 4.0 4.0 MAX ns ns ns ns ns ns ns ns UNIT
Transmit FSU24 FSU23 FSU25
Receive FSU19 FSU19 FSU20 FSU20

030-082
Figure 6-49. Low-/Full-Speed USB Bidirectional Standard 3-pin Mode
6.6.4
Multiport High-Speed Universal Serial Bus (USB) Timing

In addition to the full-speed USB controller, a high-speed (HS) USB controller is instantiated inside the AM3517/05 . It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 1 and 2. Port 1 and port 2: 12-bit master mode (SDR)
6.6.4.1
High-Speed Universal Serial Bus (USB) on Ports 1 and 2 12-bit Master Mode
The following tables assume testing over the recommended operating conditions. Table 6-107. High-Speed USB Timing Conditions 12-bit Master Mode
TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD Output load capacitance 3 pF Input signal rise time Input signal fall time 2 2 ns ns 1.8V, 3.3V UNIT
Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode (1)
NO. HSU3 ts(DIRV-CLKH) ts(NXTV-CLKH) (1) PARAMETER Setup time, hsusbx_dir valid before hsusbx_clk rising edge Setup time, hsusbx_nxt valid before hsusbx_clk rising edge 1.8V, 3.3V MIN 7.5 7.5 MAX ns ns UNIT
In hsusbx, x is equal to 1 or 2. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 181
AM3517, AM3505
Table 6-108. High-Speed USB Timing Requirements 12-bit Master Mode(1) (continued)
NO. HSU4 HSU5 HSU6 th(CLKH-DIRIV) th(CLKH-NXT/IV) ts(DATAV-CLKH) th(CLKH-DATIV) PARAMETER Hold time, hsusbx_dir valid after hsusbx_clk rising edge Hold time, hsusbx_nxt valid after hsusbx_clk rising edge Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge 1.8V, 3.3V MIN 0.2 0.2 7.5 0.2 MAX ns ns ns ns UNIT
Table 6-109. High-Speed USB Switching Characteristics 12-bit Master Mode (1)
N O. HSU0 HSU1 HSU2 fp(CLK) tj(CLK) td(CLKH-STPV) td(CLKH-STPIV) td(CLKH-DV) td(CLKH-DIV) tR(do) tF(do) (1) (2) PARAMETER hsusbx_clk clock frequency Jitter standard deviation (2), hsusbx_clk Delay time, hsusbx_clk high to output hsusbx_stp valid Delay time, hsusbx_clk high to output hsusbx_stp invalid Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid Rise time, output signals Fall time, output signals 2 2 2 2 13 1.8V, 3.3V MIN MAX 60 200 13 MHz ps ns ns ns ns ns ns UNIT
In hsusbx, x is equal to 1 or 2. The jitter probability density can be approximated by a Gaussian function.
HSU0
hsusbx_clk HSU1 hsusbx_stp HSU3 HSU4 hsusbx_dir_&_nxt HSU5 HSU2 hsusbx_data[7:0] Data_OUT HSU2 Data_IN
030-087
HSU1
HSU6
In hsusbx, x is equal to 1 or 2.
Figure 6-50. High-Speed USB 12-bit Master Mode
182
AM3517, AM3505
6.6.5
USB0 OTG (USB2.0 OTG)

The AM3517/05 USB2.0 peripheral supports the following features: USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s) USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s) All transfer modes (control, bulk, interrupt, and isochronous) 16 Transmit (TX) and 16 Receive (RX) endpoints in addition to endpoint 0 FIFO RAM 32K endpoint Programmable size Integrated USB 2.0 High Speed PHY Connects to a standard Charge Pump for VBUS 5 V generation RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
6.6.5.1
USB OTG Electrical Parameters
The USB OTG electrical parameters meet or exceed those specified in the following documents which can be obtained from the USB Implementers Forum: Universal Serial Bus Specification, Revision 2.0, April 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3, December 5, 2006 Engineering Change Notice Pull-up/pull-down resistors, Universal Serial Bus Specification Revision 2.0 For additional information related to USB OTG electrical parameters, please see the respective documents on the USB Implementers Forum web site (http://www.usb.org).
183
AM3517, AM3505
6.6.6
High-End Controller Area Network Controller (HECC) Timing

The AM3517/05 device has a High-End Controller Area Network Controller (HECC). The HECC uses established protocol to communicate serially with other controllers in harsh environments. The HECC is fully compliant with the Controller Area Network (CAN) protocol, version 2.0B. Key features of the HECC include the following: CAN, version 2.0B compliant 32 RX/TX message objects 32 receive identifier masks Programmable wake-up on bus activity Programmable interrupt scheme Automatic reply to a remote request Automatic re-transmission in case of error or loss of arbitration Protection against reception of a new message 32-bit time stamp Local network time counter Programmable priority register for each message Programmable transmission and reception time-out HECC/SCC mode of operation Standard-Extended Identifier Self-test mode
6.6.6.1
HECC Timing Requirements Table 6-110. Timing Requirements for HECC Receive (see Figure 6-51)
NO. 1 2 (1) f(baud) tw(HECC_RX) Maximum programmable baud rate Pulse duration, receive data bit
1.8 V, 3.3 V MIN H-1 (1) MAX 1 H+3 (1)
UNIT Mbps ns
These values are relative to H (where H = 1/(baud rate).
6.6.6.2
HECC Switching Characteristics
Table 6-111. Switching Characteristics Over Recommended Operating Conditions for HECC Transmit (see Figure 6-51)
NO. 3 4 (1) f(baud) tw(HECC_TX) PARAMETER Maximum programmable baud rate Pulse duration, transmit data bit H-1 (1) 1.8 V, 3.3 V MIN MAX 1 H+3 (1) UNIT Mbps ns
These values are relative to H (where H = 1/(baud rate).

2 HECCx_RX
4 HECCx_TX
Figure 6-51. HECC Transmit/Receive Timing

184 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
6.6.7
Ethernet Media Access Controller (EMAC)

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the AM3517/05 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The EMAC controls the flow of packet data from the AM3517/05 device to the PHY. The MDIO module controls PHY configuration and status monitoring. Both the EMAC and the MDIO modules interface to the AM3517/05 device through a custom interface that allows efficient data transmission and reception. This custom interface is referred to as the EMAC control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to multiplex and control interrupts.
6.6.7.1
EMAC Electrical Data/ Timing
The following tables assume testing over the recommended operating conditions. Table 6-112. RMII Input Timing Requirements
NO. fc(REFCLK) ft (REFCLK) 1 2 3 6 7 8 9 10 11 tc(REFCLK) tw(REFCLKH) tw(REFCLKL) tsu(RXD-REFCLK) th(REFCLK-RXD) tsu(CRSDV-REFCLK) th(REFCLK-CRSDV) tsu(RXER-REFCLK) th(REFCLKR-RXER) PARAMETER Frequency, REF_CLK Frequency stability, REF_CLK Cycle Time, REF_CLK Pulse Width, REF_CLK High Pulse Width, REF_CLK Low Input Setup Time, RXD Valid before REF_CLK High Input Hold Time, RXD Valid after REF_CLK High Input Setup Time, CRSDV Valid before REF_CLK High Input Hold Time, CRSDV Valid after REF_CLK High Input Setup Time, RXER Valid before REF_CLK High Input Hold Time, RXER Valid after REF_CLK High 7 7 4 2 4 2 4 2 20 13 13 1.8V, 3.3V MIN TYP 50 +/-50 MAX UNIT MHz ppm ns ns ns ns ns ns ns ns ns
Table 6-113. RMII Timing Conditions

TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD Output load capacitance 5.5 pF Input signal rise time Input signal fall time MIN 1 1 1.8V, 3.3V MAX 5 5 ns ns UNIT
Table 6-114. RMII Output Switching Characteristics

NO. 4 5 td(REFCLK-TXD) td(REFCLK-TXEN) PARAMETER Output Delay Time, REF_CLK High to TXD Valid Output Delay Time, REF_CLK High to TXEN Valid 1.8V, 3.3V MIN 2.5 2.5 TYP MAX 13 13 UNIT ns ns
185
AM3517, AM3505
2 REF_CLK
5 TXEN 4 TXD[1:0] 6 7 RXD[1:0] 8 CRS_DV 10 11 RXER_IN 9
SPRS550-004
Figure 6-52. RMII Timing Diagram
186
AM3517, AM3505
6.6.8
Management Data Input/Output (MDIO)

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. Only one PHY may be connected at any given time.
6.6.8.1
Management Data Input/Output (MDIO) Electrical Data/Timing Table 6-115. Timing Requirements for MDIO Input (see Figure 6-53 and Figure 6-54)
No. 1 4 5 tc(MD_CLK) tsu(MDIO-MDCLKH) th(MDCLKH-MDIO) Cycle time, MD_CLK
PARAMETER
MIN 400 20 2.8
MAX
UNIT ns ns ns
Setup time, MDIO data input valid before MD_CLK high Hold time, MDIO data input valid after MDCLK high
1
MD_CLK 4 5 MDIO_D (input)
Figure 6-53. MDIO Input Timing Table 6-116. Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see Figure 6-54)
No. 7 td(MDCLKL-MDIO) PARAMETER Delay time, MDCLK low to MDIO data output valid
1
MIN 0
MAX 100
UNIT ns
MD_CLK 7
MDIO_D (output)
Figure 6-54. MDIO Output Timing
6.6.9
Universal Asynchronous Receiver/Transmitter (UART)

The AM3517/05 has four UARTs (one with Infrared Data Association [IrDA] and Consumer Infrared [CIR] modes).
187
AM3517, AM3505
Table 6-117. Timing Requirements for UARTx Receive (1)

NO. 4 5 (1) tw(URXDB) tw(URXSB) Pulse duration, receive data bit (RXDn) Pulse duration, receive start bit 1.8V, 3.3V MIN .96U .96U MAX 1.05U 1.05U UNIT ns ns
U = UART baud time = 1/programmed baud rate.
Table 6-118. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (1)
NO. PARAMETER UART0 Maximum programmable baud rate f(baud_15) 1 2 3 (1) f(baud) tw(UTXDB) tw(UTXSB) UART0 Maximum programmable baud rate f(baud_30) UART0 Maximum programmable baud rate f(baud_100) Pulse duration, transmit data bit, 15/30/100 pF Pulse duration, transmit start bit, 15/30/100 pF U-2 U-2 1.8V, 3.3V MIN MAX 5 0.23 0.115 U+2 U+2 ns ns mbps UNIT
U = UART baud time = 1/programmed baud rate.

3 2 UART_TXDn Start Bit Data Bits 5 4 UART_RXDn Start Bit Data Bits
Figure 6-55. UART Transmit/Receive Timing 6.6.9.1 UART IrDA Interface
The IrDA module can operate in three different modes: Slow infrared (SIR) (115.2 Kbits/s) Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s) Fast infrared (FIR) (4 Mbits/s)
188
AM3517, AM3505
Pulse duration
90%
90%
50%
50%
10% tr tf
10%
030-118
Figure 6-56. UART IrDA Pulse Parameters 6.6.9.1.1 IrDAReceive Mode
Table 6-119. UART IrDASignaling Rate and Pulse DurationReceive Mode

SIGNALING RATE ELECTRICAL PULSE DURATION MIN 1.41 1.41 1.41 1.41 1.41 1.41 MIR 0.576 Mbit/s 1.152 Mbit/s 4.0 Mbit/s (Single pulse) 4.0 Mbit/s (Double pulse) 297.2 149.6 FIR 67 190 125 250 164 289 ns ns 416 208 518.8 258.4 ns ns NOMINAL SIR 2.4 Kbit/s 9.6 Kbit/s 19.2 Kbit/s 38.4 Kbit/s 57.6 Kbit/s 115.2 Kbit/s 78.1 19.5 9.75 4.87 3.25 1.62 88.55 22.13 11.07 5.96 4.34 2.23 s s s s s s MAX UNIT
Table 6-120. UART IrDARise and Fall TimeReceive Mode

PARAMETER tR tF Rising time, uart3_rx_irrx Falling time, uart3_rx_irrx MAX 200 200 UNIT ns ns
6.6.9.1.2 IrDATransmit Mode
189
AM3517, AM3505
Table 6-121. UART IrDASignaling Rate and Pulse DurationTransmit Mode

SIGNALING RATE MIN 2.4 Kbit/s 9.6 Kbit/s 19.2 Kbit/s 38.4 Kbit/s 57.6 Kbit/s 115.2 Kbit/s 0.576 Mbit/s 1.152 Mbit/s 4.0 Mbit/s (Single pulse) 4.0 Mbit/s (Double pulse) 78.1 19.5 9.75 4.87 3.25 1.62 MIR 414 206 FIR 123 248 125 250 128 253 ns ns 416 208 419 211 ns ns ELECTRICAL PULSE DURATION NOMINAL SIR 78.1 19.5 9.75 4.87 3.25 1.62 78.1 19.5 9.75 4.87 3.25 1.62 s s s s s s MAX UNIT
6.6.10 HDQ / 1-Wire Interfaces

This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single wire to communicate between the master and the slave. The protocols employ an asynchronous return to 1 mechanism where, after any command, the line is pulled high. 6.6.10.1 HDQ Protocol Table 6-122 and Table 6-123 assume testing over the recommended operating conditions (see Figure 6-57 through Figure 6-60). Table 6-122. HDQ Timing Requirements
PARAMETER tCYCD tHW1 tHW0 tRSPS (1) Defined by software. DESCRIPTION Bit window Reads 1 Reads 0 Command to host respond time (1) 180 MIN 253 68 MAX UNIT s
Table 6-123. HDQ Switching Characteristics

PARAMETER tB tBR tCYCH tDW1 tDW0 DESCRIPTION Break timing Break recovery Bit window Sends1 (write) Sends0 (write) MIN TYP 193 63 253 1.3 101 MAX UNIT s
tB HDQ
tBR
030-095
Figure 6-57. HDQ Break (Reset) Timing
190
AM3517, AM3505
tCYCH tHW0 tHW1 HDQ

030-096
Figure 6-58. HDQ Read Bit Timing (Data)

tCYCD tDW0 tDW1 HDQ
030-097
Figure 6-59. HDQ Write Bit Timing (Command/Address or Data)

Command _byte_written 0_(LSB ) Break HDQ
030-098
Data_byte_received tRSPS 1 0_(LSB) 6
7_(MSB)
Figure 6-60. HDQ Communication Timing 6.6.10.2 1-Wire Protocol Table 6-124 and Table 6-125 assume testing over the recommended operating conditions (see Figure 6-61 through Figure 6-63). Table 6-124. 1-Wire Timing Requirements
PARAMETER tPDH tPDL tRDV + tREL DESCRIPTION Presence pulse delay high Presence pulse delay low Read bit-zero time 68 tPDH 102 MIN MAX 68 UNIT s
Table 6-125. 1-Wire Switching Characteristics

PARAMETER tRSTL tRSTH tSLOT tLOW1 tLOW0 tREC tLOWR DESCRIPTION Reset time low Reset time high Write bit cycle time Write bit-one time Write bit-zero time Recovery time Read bit strobe time MIN TYP 484 484 102 1.3 101 134 13 MAX UNIT s
tRSTH 1-WIRE tRTSL tPDH tPDL
030-099
Figure 6-61. 1-Wire Break (Reset) Timing

191
AM3517, AM3505
tSLOT_and_ tREC tRDV_and_ tREL 1-WIRE tLOWR
030-100
Figure 6-62. 1-Wire Read Bit Timing (Data)

tSLOT_and_tREC tLOW0 1-WIRE tLOW1
030-101
Figure 6-63. 1-Wire Write Bit Timing (Command/Address or Data)
192
AM3517, AM3505
6.6.11 I2C Interface

The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus. The I2C controller supports the multimaster mode which allows more than one device capable of controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can operate as either transmitter or receiver, according to the function of the device. In addition to being a transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when performing data transfers. This data transfer is carried out via two serial bidirectional wires: An SDA data line An SCL clock line The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) . 6.6.11.1 I2C Standard/Fast-Speed Mode Table 6-126. I2C Standard/Fast-Speed Mode Timings
1.8V, 3.3-V NO. PARAMETER (1) STANDARD MODE MIN fSCL I1 I2 I3 I4 I5 I6 I7 I8 tw(SCLH) tw(SCLL) tsu(SDAV-SCLH) th(SCLHSDAV) tsu(SDAL-SCLH) th(SCLHSDAH) th(SCLHRSTART) tw(SDAH) tR(SCL) tF(SCL) tR(SDA) tF(SDA) CB (1) (2) Clock Frequency, i2cX_scl Pulse Duration, i2cX_scl high Pulse Duration, i2cX_scl low Setup time, i2cX_sda valid before i2cX_scl active level Hold time, i2cX_sda valid after i2cX_scl active level Setup time, i2cX_scl high after i2cX_sda low (for a START (4) condition or a repeated START condition) Hold time, i2cX_sda low level after i2cX_scl high level (STOP condition) Hold time, i2cX_sda low level after i2cX_scl high level (for a repeated START condition) Pulse duration, i2cX_sda high between STOP and START conditions Rise time, i2cX_scl Fall time, i2cX_scl Rise time, i2cX_sda Fall time, i2cX_sda Capacitive load for each bus line 4.7 4 4 4.7 1000 300 1000 300 60 4 4.7 250 3.45 (3) 0.6 0.6 0.6 1.3 300 300 300 300 60 MAX 100 0.6 1.3 100 (2) 0.9 (3) FAST MODE MIN MAX 400 kHz s s ns s s s s s ns ns ns ns pF UNIT
(3) (4)
In i2cX, X is equal to 1, 2, or 3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) 250 ns must then be met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the i2cx_scl line is released. The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal. After this time, the first clock is generated.
193
AM3517, AM3505
START REPEAT START i2cX_sda I2 I6 i2cX_scl I1 I3 I4 I5 I6 I8 I7 STOP
START
030-093
Figure 6-64. I C Standard/Fast Mode
194
AM3517, AM3505
6.6.11.2 I2C High-Speed Mode Table 6-127. I2C High-Speed Mode Timings (1)
NO. fSCL I1 I2 I3 I4 I5 tw(SCLH) tw(SCLL) tsu(SDAV-SCLH) th(SCLHSDAV) tsu(SDAL-SCLH) PARAMETER MIN Clock frequency, i2cX_scl Pulse duration, i2cX_scl high Pulse duration, i2cX_scl low Setup time, i2cX_sda valid before i2cX_scl active level Hold time, i2cX_sda valid after i2cX_scl active level Setup time, i2cX_scl high after i2cX_sda low (for a START (4) condition or a repeated START condition) Hold time, i2cX_sda low level after i2cX_scl high level (STOP condition) Hold time, i2cX_sda low level after i2cX_scl high level (for a repeated START condition) Rise time, i2cX_scl Rise time, i2cX_scl after a repeated START condition and after a bit acknowledge Fall time, i2cX_scl Rise time, i2cX_sda Fall time, i2cX_sda 160 60 (3) 160
(3)
(2)
1.8V, 3.3V UNIT MAX 3.4 MHz s s ns 70 s s
10
I6 I7
th(SCLHSDAH) th(SCLHRSTART) tR(SCL) tR(SCL) tF(SCL) tR(SDA) tF(SDA)
160 160 10 10 10 10 10 40 80 40 80 80
s ns ns ns ns ns ns
(1) (2) (3) (4)
In i2cX, X is equal to 1, 2, or 3. The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to bridge the undefined region of the falling edge of i2cx_scl. HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(SCLL) > 2 tw(SCLH). After this time, the first clock is generated.
START REPEAT i2cX_sda I5 i2cX_scl
030-094
STOP
I6
I1
I2
I3
I4
I7
Figure 6-65. I C High-Speed Mode(1) (2) (3)

(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. tw(SCLL) > 2 x tw(SCLH). (2) In i2cX, X is equal to 1, 2, or 3. (3) After this time, the first clock is generated.
Table 6-128. Correspondence Standard vs. TI Timing References

AM3517/05 S/F Mode fSCL I1 I2 I3 I4 I5 I6 I7 I8 tw(SCLH) tw(SCLL) tsu(SDAV-SCLH) th(SCLH-SDAV) tsu(SDAL-SCLH) th(SCLH-SDAH) th(SCLH-RSTART) tw(SDAH) FSCL THIGH TLOW TSU;DAT TSU;DAT TSU;STA THD;STA TSU;STO TBUF 195 STANDARD-I2C HS Mode FSCLH THIGH TLOW TSU;DAT TSU;DAT TSU;STA THD;STA TSU;STO
AM3517, AM3505
6.7 6.7.1
Removable Media Interfaces High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing
The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding CRC, start/end bit, and checking for syntactical correctness. There are three MMC interfaces on the AM3517/05 : MMC/SD/SDIO Interface 1 : 1.8-V/3.3-V support 8 bits MMC/SD/SDIO Interface 2 : 1.8-V/3.3-V support 8 bits 4 bits with external transceiver allowing to support 1.8-V/3.3-V peripherals in 1.8-V mode operation. Transceiver direction control signals are multiplexed with the upper four data bits. MMC/SD/SDIO Interface 3 : 1.8-V/3.3-V support 8 bits
6.7.1.1
MMC/SD/SDIO in SD Identification Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-129. MMC/SD/SDIO Timing Conditions SD Identification Mode
TIMING CONDITION PARAMETER MIN SD Identification Mode Input Conditions tr tf Output Conditions CLOAD Output load capacitance 30
(2) (3) (4)
1.8V, 3.3V MAX
UNIT
Input signal rise time Input signal fall time
10 10
ns ns pF
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode (1)

NO. SD Identification Mode MMC/SD/SDIO Interface 1 HSSD3/SD3 HSSD4/SD4 tsu(CMDV-CLKIH) tsu(CLKIH-CMDIV) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 1198.4 1249.2 PARAMETER 1.8V, 3.3V MIN
UNIT
MAX
ns ns
MMC/SD/SDIO Interface 2 HSSD3/SD3 tsu(CMDV-CLKIH) 1198.4 ns
(1) (2) (3) (4) 196
Timing parameters refer to output clock specified in Table 6-131. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-131. Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes). For more information, see the AM35x Technical Reference Manual (TRM) [literature number SPRUGR0]. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
www.ti.com SPRS550C OCTOBER 2009 REVISED MARCH 2011 (3)(4)
Table 6-130. MMC/SD/SDIO Timing Requirements SD Identification Mode(1) (2)

NO. HSSD4/SD4 tsu(CLKIH-CMDIV) PARAMETER Hold time, mmc2_cmd valid after mmc2_clk rising clock edge Setup time, mmc3_cmd valid before mmc3_clk rising clock edge Hold time, mmc3_cmd valid after mmc3_clk rising clock edge MIN 1249.2
(continued)
UNIT ns
1.8V, 3.3V MAX
MMC/SD/SDIO Interface 3 HSSD3/SD3 HSSD4/SD4 tsu(CMDV-CLKIH) tsu(CLKIH-CMDIV) 1198.4 1249.2 ns ns
Table 6-131. MMC/SD/SDIO Switching Characteristics SD Identification Mode (1) (2)

NO. SD Identification Mode HSSD1/SD1 HSSD2/SD2 HSSD2/SD2 tc(clk) tW(clkH) tW(clkL) tdc(clk) tj(clk) MMC/SD/SDIO Interface 1 tr(clk) tf(clkH) tr(clkL) tf(clk) HSSD5/SD5 td(CLKOH-CMD) Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc1_clk rising clock edge to mmc1_cmd transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc2_clk rising clock edge to mmc2_cmd transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc3_clk rising clock edge to mmc3_cmd transition 6.3 6.3 6.3 10 10 10 10 2492.7 ns ns ns ns ns Cycle time, output clk period Typical pulse duration, output clk high Typical pulse duration, output clk low Duty cycle error, output clk Jitter standard deviation, output clk X
(3)
PARAMETER
1.8V, 3.3V MIN MAX 2500 *PO

(4)
UNIT
ns ns ns
Y (5)*PO (4) 125 200
ns ps
MMC/SD/SDIO Interface 2 tr(clk) tf(clkH) tr(clkL) tf(clk) HSSD5/SD5 td(CLKOH-CMD) 10 10 10 10 2492.7 ns ns ns ns ns
MMC/SD/SDIO Interface 3 tr(clk) tf(clkH) tr(clkL) tf(clk) HSSD5/SD5 (1) (2) (3) (4) (5) td(CLKOH-CMD) 10 10 10 10 2492.7 ns ns ns ns ns
Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes). The jitter probability density can be approximated by a Gaussian function. The X parameter is defined as shown below. PO = output clk period in ns. The Y parameter is defined as shown below.
Table 6-132. X Parameter

CLKD 1 or Even Odd X 0.5 (trunc[CLKD/2]+1)/CLKD
197
AM3517, AM3505
Table 6-133. Y Parameter

CLKD 1 or Even Odd Y 0.5 (trunc[CLKD/2])/CLKD
6.7.1.2
MMC/SD/SDIO in High-Speed MMC Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-134. MMC/SD/SDIO Timing Conditions High-Speed MMC Mode
TIMING CONDITION PARAMETER MIN High-Speed MMC Mode Input Conditions tr tf Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 0.19 0.19 3 3 ns ns 1.8V, 3.3V MAX UNIT
Table 6-135. MMC/SD/SDIO Timing Requirements High-Speed MMC Mode (1) (2) (3) (4)
NO. High-Speed MMC Mode MMC/SD/SDIO Interface 1 MMC3 tsu(CMDV-CLKIH) MMC4 th(CLKIH-CMDIV) MMC7 tsu(DATxV-CLKIH) MMC8 th(CLKIH-DATxIV) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Setup time, mmc1_datx valid before mmc1_clk rising clock edge Hold time, mmc1_datx valid after mmc1_clk rising clock edge Setup time, mmc2_cmd valid before mmc2_clk rising clock edge Hold time, mmc2_cmd valid after mmc2_clk rising clock edge Setup time, mmc2_datx valid before mmc2_clk rising clock edge Hold time, mmc2_datx valid after mmc2_clk rising clock edge Setup time, mmc3_cmd valid before mmc3_clk rising clock edge Hold time, mmc3_cmd valid after mmc3_clk rising clock edge Setup time, mmc3_datx valid before mmc3_clk rising clock edge Hold time, mmc3_datx valid after mmc3_clk rising clock edge 2.13 3.47 2.13 3.47 2.41 2.09 2.41 2.09 ns ns ns ns PARAMETER MIN 1.8 V MAX MIN 3.3V MAX UNIT
MMC/SD/SDIO Interface 2 MMC3 tsu(CMDV-CLKIH) MMC4 th(CLKIH-CMDIV) MMC7 tsu(DATxV-CLKIH) MMC8 th(CLKIH-DATxIV) 2.88 2.90 2.88 2.90 3.23 1.46 3.23 1.46 ns ns ns ns
MMC/SD/SDIO Interface 3 MMC3 tsu(CMDV-CLKIH) MMC4 th(CLKIH-CMDIV) MMC7 tsu(DATxV-CLKIH) MMC8 th(CLKIH-DATxIV) (1) (2) (3) (4) 198 3.38 2.83 3.38 2.83 3.41 1.46 3.41 1.46 ns ns ns ns
In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Timing parameters refer to output clock specified in Table 6-136. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-136. Corresponding figures showing timing parameters are common with Standard MMC mode. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Table 6-136. MMC/SD/SDIO Switching Characteristics High-Speed MMC Mode (1) (2)
N O. High-Speed MMC Mode MMC1 MMC2 MMC2 tc(clk) tW(clkH) tW(clkL) tdc(clk) tj(clk) MMC/SD/SDIO Interface 1 tc(clk) tW(clkH) tW(clkL) tdc(clk) MMC5 MMC6 td(CLKOH-CMD) td(CLKOH-DATx) Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc1_clk rising clock edge to mmc1_cmd transition Delay time, mmc1_clk rising clock edge to mmc1_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc2_clk rising clock edge to mmc2_cmd transition Delay time, mmc2_clk rising clock edge to mmc2_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc3_clk rising clock edge to mmc3_cmd transition Delay time, mmc3_clk rising clock edge to mmc3_datx transition 3.7 3.7 3.7 3.7 3.7 3.7 3 3 3 3 14.11 16.50 ns ns ns ns ns ns Cycle time, output clk period Typical pulse duration, output clk high Typical pulse duration, output clk low Duty cycle error, output clk Jitter standard deviation, output clk X
(3)
PARAMETER MIN
1.8V, 3.3V MAX 20.83 *PO

(4)
UNIT
ns ns ns
Y (5)*PO (4) 1041.67 200
ps ps
MMC/SD/SDIO Interface 2 tc(clk) tW(clkH) tW(clkL) tdc(clk) MMC5 MMC6 td(CLKOH-CMD) td(CLKOH-DATx) 3 3 3 3 14.11 16.50 ns ns ns ns ns ns
MMC/SD/SDIO Interface 3 tc(clk) tW(clkH) tW(clkL) tdc(clk) MMC5 MMC6 (1) (2) (3) (4) (5) td(CLKOH-CMD) td(CLKOH-DATx) 3 3 3 3 14.11 14.11 ns ns ns ns ns ns
In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. The jitter probability density can be approximated by a Gaussian function. The X parameter is defined as shown below. PO = output clk period in ns. The Y parameter is defined as shown below.


199
AM3517, AM3505
For details about clock division factor CLKD, see the AM35x Technical Reference Manual. 6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-139. MMC/SD/SDIO Timing Conditions Standard MMC Mode and MMC Identification Mode
TIMING CONDITION PARAMETER MIN Standard MMC Mode and MMC Identification Mode Input Conditions tr tf Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 0.19 0.19 10 10 ns ns 1.8-V,3.3-V MAX UNIT
200
AM3517, AM3505
Table 6-140. MMC/SD/SDIO Timing Requirements Standard MMC Mode and MMC Identification Mode (1) (2)
(3)
NO.
PARAMETER MIN
1.8 V MAX MIN
3.3V MAX
UNIT
Standard MMC Mode and MMC Identification Mode MMC/SD/SDIO Interface 1 MMC3 tsu(CMDV-CLKIH) MMC4 th(CLKIH-CMDIV) MMC7 tsu(DATxV-CLKIH) MMC8 th(CLKIH-DATxIV) MMC/SD/SDIO Interface 2 MMC3 tsu(CMDV-CLKIH) MMC4 th(CLKIH-CMDIV) MMC7 tsu(DATxV-CLKIH) MMC8 th(CLKIH-DATxIV) MMC/SD/SDIO Interface 3 MMC3 tsu(CMDV-CLKIH) MMC4 th(CLKIH-CMDIV) MMC7 tsu(DATxV-CLKIH) MMC8 th(CLKIH-DATxIV) (1) (2) (3) Setup time, mmc3_cmd valid before mmc3_clk rising clock edge Hold time, mmc3_cmd valid after mmc3_clk rising clock edge Setup time, mmc3_datx valid before mmc3_clk rising clock edge Hold time, mmc3_datx valid after mmc3_clk rising clock edge 3.38 2.83 3.38 2.83 3.41 1.46 3.41 1.46 ns ns ns ns Setup time, mmc2_cmd valid before mmc2_clk rising clock edge Hold time, mmc2_cmd valid after mmc2_clk rising clock edge Setup time, mmc2_datx valid before mmc2_clk rising clock edge Hold time, mmc2_datx valid after mmc2_clk rising clock edge 2.88 2.90 2.88 2.90 3.23 1.46 3.23 1.46 ns ns ns ns Setup time, mmc1_cmd valid before mmc1_clk rising clock edge Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Setup time, mmc1_datx valid before mmc1_clk rising clock edge Hold time, mmc1_datx valid after mmc1_clk rising clock edge 2.13 3.47 2.13 3.47 2.41 2.09 2.41 2.09 ns ns ns ns
Timing parameters are referred to output clock specified in Table 6-141. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-141. In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification Mode (1) (2)
NO. MMC Identification Mode MMC1 MMC2 MMC2 tc(clk) tW(clkH) tW(clkL) tdc(clk) tj(clk) Standard MMC Mode MMC1 MMC2 MMC2 (1) (2) (3) (4) (5) tc(clk) tW(clkH) tW(clkL) Cycle time Typical pulse duration, output clk high Typical pulse duration, output clk low X *PO
(3) (4)
PARAMETER MIN Cycle time Typical pulse duration, output clk high Typical pulse duration, output clk low Duty cycle error, output clk Jitter standard deviation
1.8V, 3.3V MAX 2500 X (3)*PO (4) Y (5)*PO (4) 2604.17 200 2500 Y (5)*PO (4)
UNIT
ns ns ns ns ps ns ns ns
In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. The jitter probability density can be approximated by a Gaussian function. The X parameter is defined as shown below. PO = output clk period in ns. The Y parameter is defined as shown below. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 201
AM3517, AM3505
Table 6-141. MMC/SD/SDIO Switching Characteristics Standard MMC Mode and MMC Identification Mode(1)(2) (continued)
NO. tdc(clk) tj(clk) MMC/SD/SDIO Interface 1 tr(clk) tf(clkH) tr(clkL) tf(clk) MMC5 MMC6 td(CLKOH-CMD) td(CLKOH-DATx) Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc1_clk rising clock edge to mmc1_cmd transition Delay time, mmc1_clk rising clock edge to mmc1_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc2_clk rising clock edge to mmc2_cmd transition Delay time, mmc2_clk rising clock edge to mmc2_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc3_clk rising clock edge to mmc3_cmd transition Delay time, mmc3_clk rising clock edge to mmc3_datx transition 4.3 4.3 4.3 4.3 4.3 4.3 10 10 10 10 47.78 47.78 ns ns ns ns ns ns PARAMETER MIN Duty cycle error, output clk Jitter standard deviation 1.8V, 3.3V MAX 2604.17 200 ps ps UNIT
MMC/SD/SDIO Interface 2 tr(clk) tf(clkH) tr(clkL) tf(clk) MMC5 MMC6 td(CLKOH-CMD) td(CLKOH-DATx) 10 10 10 10 47.78 47.78 ns ns ns ns ns ns
MMC/SD/SDIO Interface 3 tr(clk) tf(clkH) tr(clkL) tf(clk) MMC5 MMC6 td(CLKOH-CMD) td(CLKOH-DATx) 10 10 10 10 47.78 47.78 ns ns ns ns ns ns


202
AM3517, AM3505
For details about clock division factor CLKD, see the AM35x Technical Reference Manual.
MMC1 mmcx_clk MMC3 mmcx_cmd MMC7 mmcx_dat[3:0]
030-104
MMC2
MMC4
MMC8
In mmcx, x is equal to 1, 2, or 3.
Figure 6-66. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Receive
MMC1 mmcx_clk MMC5 mmcx_cmd MMC6 mmcx_dat[3:0]
030-105
MMC2
MMC5
MMC6
Figure 6-67. MMC/SD/SDIO High-Speed and Standard MMC Modes Data/Command Transmit 6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-144. MMC/SD/SDIO Timing Conditions High-Speed SD Mode
TIMING CONDITION PARAMETER MIN High-Speed SD Mode Input Conditions tR tF Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 0.19 0.19 3 3 ns ns 1.8V, 3.3V MAX UNIT
Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode (1) (2) (3)
NO. High-Speed SD Mode MMC/SD/SDIO Interface 1 HSSD3 HSSD4 tsu(CMDV-CLKIH) th(CLKIH-CMDIV) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 5.61 2.28 ns ns PARAMETER MIN 1.8V, 3.3V MAX UNIT
(1) (2) (3)
In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-146. Timing Parameters refer to output clock specified in Table 6-146. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 203
AM3517, AM3505
Table 6-145. MMC/SD/SDIO Timing Requirements High-Speed SD Mode(1)(2)(3) (continued)

NO. HSSD7 HSSD8 tsu(DATxV-CLKIH) th(CLKIH-DATxIV) PARAMETER MIN Setup time, mmc1_datx valid before mmc1_clk rising clock edge Hold time, mmc1_datx valid after mmc1_clk rising clock edge Setup time, mmc2_cmd valid before mmc2_clk rising clock edge Hold time, mmc2_cmd valid after mmc2_clk rising clock edge Setup time, mmc2_datx valid before mmc2_clk rising clock edge Hold time, mmc2_datx valid after mmc2_clk rising clock edge Setup time, mmc3_cmd valid before mmc3_clk rising clock edge Hold time, mmc3_cmd valid after mmc3_clk rising clock edge Setup time, mmc3_datx valid before mmc3_clk rising clock edge Hold time, mmc3_datx valid after mmc3_clk rising clock edge 5.61 2.28 1.8V, 3.3V MAX ns ns UNIT
MMC/SD/SDIO Interface 2 HSSD3 HSSD4 HSSD7 HSSD8 tsu(CMDV-CLKIH) th(CLKIH-CMDIV) tsu(DATxV-CLKIH) th(CLKIH-DATxIV) 5.61 2.28 5.61 2.28 ns ns ns ns
MMC/SD/SDIO Interface 3 HSSD3 HSSD4 HSSD7 HSSD8 tsu(CMDV-CLKIH) th(CLKIH-CMDIV) tsu(DATxV-CLKIH) th(CLKIH-DATxIV) 5.61 2.28 5.61 2.28 ns ns ns ns
Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode (1) (2)

NO. High-Speed SD Mode HSSD1 HSSD2 HSSD2 tc(clk) tW(clkH) tW(clkL) tdc(clk) tj(clk) MMC/SD/SDIO Interface 1 tr(clk) tf(clkH) tr(clkL) tf(clk) HSSD5 HSSD6 td(CLKOH-CMD) td(CLKOH-DATx) Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc1_clk rising clock edge to mmc1_cmd transition Delay time, mmc1_clk rising clock edge to mmc1_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data 3.72 3.72 3 3 3 3 14.11 14.11 ns ns ns ns ns ns Cycle time Typical pulse duration, output clk high Typical pulse duration, output clk low Duty cycle error, output clk Jitter standard deviation X
(3)
PARAMETER
1.8 V, 3.3 V MIN MAX 20.83 *PO

(4)
UNIT
ns ns ns
Y (5)*PO (4) 1041.67 200
ps ps
MMC/SD/SDIO Interface 2 tr(clk) tf(clkH) tr(clkL) tf(clk) (1) (2) (3) (4) (5) 204 3 3 3 3 ns ns ns ns
In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. The jitter probability density can be approximated by a Gaussian function. The X parameter is defined as shown in Table 6-147. PO = output clk period in ns. The Y parameter is defined as shown in Table 6-148. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright 20092011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
Table 6-146. MMC/SD/SDIO Switching Characteristics High-Speed SD Mode(1)(2) (continued)

NO. HSSD5 HSSD6 td(CLKOH-CMD) td(CLKOH-DATx) PARAMETER Delay time, mmc2_clk rising clock edge to mmc2_cmd transition Delay time, mmc2_clk rising clock edge to mmc2_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc3_clk rising clock edge to mmc3_cmd transition Delay time, mmc3_clk rising clock edge to mmc3_datx transition 3.72 3.72 1.8 V, 3.3 V MIN 3.72 3.72 MAX 14.11 14.11 ns ns UNIT
MMC/SD/SDIO Interface 3 tr(clk) tf(clkH) tr(clkL) tf(clk) HSSD5 HSSD6 td(CLKOH-CMD) td(CLKOH-DATx) 3 3 3 3 14.11 14.11 ns ns ns ns ns ns
Table 6-147. X Parameters

Table 6-148. Y Parameters

HSSD1 mmcx_clk HSSD3 mmcx_cmd HSSD7 mmcx_dat[3:0]
030-106
HSSD2
HSSD4
HSSD8
Figure 6-68. MMC/SD/SDIO High-Speed SD Mode Data/Command Receive

HSSD1 mmcx_clk HSSD5 mmcx_cmd HSSD6 mmcx_dat[3:0]
030-107
HSSD2
HSSD5
HSSD6
Figure 6-69. MMC/SD/SDIO High-Speed SD Mode Data/Command Transmit

205
AM3517, AM3505
6.7.1.5
MMC/SD/SDIO in Standard SD Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-149. MMC/SD/SDIO Timing Conditions Standard SD Mode
TIMING CONDITION PARAMETER MIN Standard SD Mode Input Conditions tR tF Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 0.19 0.19 10 10 ns ns 1.8V, 3.3V MAX UNIT
206
AM3517, AM3505
Table 6-150. MMC/SD/SDIO Timing Requirements Standard SD Mode (1) (2) (3)
NO. Standard SD Mode MMC/SD/SDIO Interface 1 SD3 SD4 SD7 SD8 tsu(CMDV-CLKIH) th(CLKIH-CMDIV) tsu(DATxV-CLKIH) th(CLKIH-DATxIV) Setup time, mmc1_cmd valid before mmc1_clk rising clock edge Hold time, mmc1_cmd valid after mmc1_clk rising clock edge Setup time, mmc1_datx valid before mmc1_clk rising clock edge Hold time, mmc1_datx valid after mmc1_clk rising clock edge Setup time, mmc2_cmd valid before mmc2_clk rising clock edge Hold time, mmc2_cmd valid after mmc2_clk rising clock edge Setup time, mmc2_datx valid before mmc2_clk rising clock edge Hold time, mmc2_datx valid after mmc2_clk rising clock edge Setup time, mmc3_cmd valid before mmc3_clk rising clock edge Hold time, mmc3_cmd valid after mmc3_clk rising clock edge Setup time, mmc3_datx valid before mmc3_clk rising clock edge Hold time, mmc3_datx valid after mmc3_clk rising clock edge 6.23 19.37 6.23 19.37 ns ns ns ns PARAMETER MIN 1.8 V, 3.3V MAX UNIT
MMC/SD/SDIO Interface 2 SD3 SD4 SD7 SD8 tsu(CMDV-CLKIH) th(CLKIH-CMDIV) tsu(DATxV-CLKIH) th(CLKIH-DATxIV) 6.23 19.37 6.23 19.37 ns ns ns ns
MMC/SD/SDIO Interface 3 SD3 SD4 SD7 SD8 (1) (2) (3) tsu(CMDV-CLKIH) th(CLKIH-CMDIV) tsu(DATxV-CLKIH) th(CLKIH-DATxIV) 6.23 19.37 6.23 19.37 ns ns ns ns
Timing parameters refer to output clock specified in Table 6-151. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-151. In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode (1) (2)

NO. Standard SD Mode SD1 SD2 SD2 tc(clk) tW(clkH) tW(clkL) tdc(clk) tj(clk) MMC/SD/SDIO Interface 1 tr(clk) tf(clkH) tr(clkL) tf(clk) Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data 10 10 10 10 ns ns ns ns Cycle time Typical pulse duration, output clk high Typical pulse duration, output clk low Duty cycle error, output clk Jitter standard deviation X (3)*PO (4) Y (5)*PO (4) 2083.33 200 41.67 ns ns ns ps ps PARAMETER MIN 1.8V, 3.3V MAX UNIT
(1) (2) (3) (4) (5)
The jitter probability density can be approximated by a Gaussian function. In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. The X parameter is defined as shown in Table 6-152. PO = output clk period in ns. The Y parameter is defined as shown in Table 6-153. TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 207
AM3517, AM3505
Table 6-151. MMC/SD/SDIO Switching Characteristics Standard SD Mode(1)(2) (continued)

NO. SD5 SD6 td(CLKOH-CMD) td(CLKOH-DATx) PARAMETER MIN Delay time, mmc1_clk rising clock edge to mmc1_cmd transition Delay time, mmc1_clk rising clock edge to mmc1_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc2_clk rising clock edge to mmc2_cmd transition Delay time, mmc2_clk rising clock edge to mmc2_datx transition Rise time, output clk Fall time, output clk Rise time, output data Fall time, output data Delay time, mmc3_clk rising clock edge to mmc3_cmd transition Delay time, mmc3_clk rising clock edge to mmc3_datx transition 6.13 6.13 6.13 6.13 6.13 6.13 1.8V, 3.3V MAX 35.53 35.53 ns ns UNIT
MMC/SD/SDIO Interface 2 tr(clk) tf(clkH) tr(clkL) tf(clk) SD5 SD6 td(CLKOH-CMD) td(CLKOH-DATx) 10 10 10 10 35.53 35.53 ns ns ns ns ns ns
MMC/SD/SDIO Interface 3 tr(clk) tf(clkH) tr(clkL) tf(clk) SD5 SD6 td(CLKOH-CMD) td(CLKOH-DATx) 10 10 10 10 35.53 35.53 ns ns ns ns ns ns


SD1 mmcx_clk SD3 mmcx_cmd SD7 mmcx_dat[3:0]
030-108
SD2
SD4
SD8
Figure 6-70. MMC/SD/SDIO Standard SD Mode Data/Command Receive
208
AM3517, AM3505
SD1 mmcx_clk SD5 mmcx_cmd SD6 mmcx_dat[3:0]
SD2
SD5
SD6
030-109
Figure 6-71. MMC/SD/SDIO Standard SD Mode Data/Command Transmit
209
AM3517, AM3505
6.8
Test Interfaces
The emulation and trace interfaces allow tracing activities of the following CPUs: ARM CortexTM-A8 through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time trace of the ARM subsystem operations. All processors can be emulated via JTAG ports.
6.8.1
Embedded Trace Macro Interface (ETM)

The following tables assume testing over the recommended operating conditions. Table 6-154. Embedded Trace Macro Interface Switching Characteristics
NO. f ETM0 ETM1 ETM2 ETM3 1/tc(CLK) tc(CLK) tW(CLK) td(CLK-CTL) td(CLK-D)
PARAMETER Frequency, etk_clk Cycle time Clock pulse width, etk_clk Delay time, etk_clk clock edge to etk_ctl transition Delay time, etk_clk clock high to etk_d[15:0] transition
MIN
MAX 166
UNIT MHz ns ns
6.02 3.01 -0.5 -0.5 0.5 0.5
ns ns
ETM0 ETM1 etk_clk ETM2 etk_ctl ETM3 etk_d[15:0]

030-110
ETM2
ETM3
Figure 6-72. Embedded Trace Macro Interface
6.8.2
JTAG Interfaces
AM3517/05 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections define the timing requirements for several tools used to test the AM3517/05 processors as: Free running clock tool, like XDS560 and XDS510 tools Adaptive clock tool, like RealView ICE tool and Lauterbach tool
6.8.2.1
JTAG Free Running Clock Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-155. JTAG Timing Conditions Free Running Clock Mode
TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 5 5 3 3 ns ns 1.8 V MAX 3.3 V MAX UNIT
210
AM3517, AM3505
Table 6-156. JTAG Timing Requirements Free Running Clock Mode (1) (2) (3)
NO. JT4 JT5 JT6 tc(tck) tw(tckL) tw(tckH) tdc(tck) tj(tck) JT7 JT8 JT9 JT10 JT12 JT13 (1) (2) (3) tsu(tdiV-rtckH) th(tdiV-rtckH) tsu(tmsV-rtckH) th(tmsV-rtckH) tsu(emuxV-rtckH) th(emuxV-rtckH) PARAMETER MIN Cycle time Typical pulse duration, jtag_tck low Typical pulse duration, jtag_tck high Duty cycle error, jtag_tck Cycle jitter Setup time, jtag_tdi valid before jtag_rtck high Hold time, jtag_tdi valid after jtag_rtck high Setup time, jtag_tms valid before jtag_rtck high Hold time, jtag_tms valid after jtag_rtck high Setup time, jtag_emux Hold time,jtag_emux 20 10 10 -1250 -1250 1.8 0.7 1.8 0.7 14.6 2 1250 1250 1.8V MAX MIN 20 10 10 -1250 -1250 3.8 2.7 3.8 2.7 14.6 2 1250 1250 3.3V MAX ns ns ns ps ps ns ns ns ns ns ns UNIT
Maximum cycle jitter supported by jtag _tck input clock. x = 0 to 1 The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-157. JTAG Switching Characteristics Free Running Clock Mode (1) (2)
1.8 V NO. JT1 JT2 JT3 tc(rtck) tw(rtckL) tw(rtckH) tdc(rtck) tj(rtck) tR(rtck) tF(rtck) JT11 td(rtckL-tdoV) tR(tdo) tF(tdo) JT14 td(rtckH-emuxV) tR(emux) tF(emux) (1) (2) PARAMETER Cycle time
(1)
3.3 V MAX MIN 20 10 10 1250 33.33 4 4 -1250 1250 33.33 4 4 -8 8 4 4 2.7 15.1 6 6 MAX UNIT ns ns ns ps ps ns ns ns ns ns ns ns ns
MIN 20 10 10 -1250
, jtag_rtck period
Typical pulse duration, jtag_rtck low Typical pulse duration, jtag_rtck high Duty cycle error, jtag_rtck Jitter standard deviation (2), jtag_rtck Rise time, jtag_rtck Fall time, jtag_rtck Delay time, jtag_rtck low to jtag_tdo valid Rise time, jtag_tdo Fall time, jtag_tdo Delay time, jtag_rtck high to ,jtag_emux Rise time, jtag_emux Fall time, jtag_emux
-5.8
5.8 4 4
2.7
15.1 6 6
Related with the jtag_rtck maximum frequency. The jitter probability density can be approximated by a Gaussian function.
211
AM3517, AM3505
JT4 JT5 jtag_tck JT1 JT2 jtag_rtck JT7 jtag_tdi JT9 jtag_tms JT12 jtag_emux(IN) JT11 jtag_tdo JT14 jtag_emux(OUT)
030-113
JT6
JT3 JT8 JT10 JT13
In jtag_emux, x is equal to 0 to 1.
Figure 6-73. JTAG Interface Timing Free Running Clock Mode 6.8.2.2 JTAG Adaptive Clock Mode
The following tables assume testing over the recommended operating conditions and electrical characteristic conditions. Table 6-158. JTAG Timing Conditions Adaptive Clock Mode
TIMING CONDITION PARAMETER Input Conditions tR tF Output Conditions CLOAD Output load capacitance 30 pF Input signal rise time Input signal fall time 5 5 3 3 ns ns 1.8 V MAX 3.3 V UNIT
Table 6-159. JTAG Timing Requirements Adaptive Clock Mode (1) (2)
1.8 V NO. JA4 JA5 JA6 tc(tck) tw(tckL) tw(tckH) tdc(lclk) tj(lclk) JA7 JA8 JA9 JA10 (1) (2) tsu(tdiV-tckH) th(tdiV-tckH) tsu(tmsV-tckH) th(tmsV-tckH) PARAMETER Cycle time Typical pulse duration, jtag_tck low Typical pulse duration, jtag_tck high Duty cycle error, jtag_tck Cycle jitter Setup time, jtag_tdi valid before jtag_tck high Hold time, jtag_tdi valid after jtag_tck high Setup time, jtag_tms valid before jtag_tck high Hold time, jtag_tms valid after jtag_tck high MIN 20 10 10 -2500 -1500 13.8 13.8 13.8 13.8 2500 1500 MAX MIN 20 10 10 -2500 -1500 13.8 13.8 13.8 13.8 2500 1500 3.3 V MAX UNIT ns ns ns ps ps ns ns ns ns
Maximum cycle jitter supported by jtag _tck input clock. The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
212
AM3517, AM3505
Table 6-160. JTAG Switching Characteristics Adaptive Clock Mode (1)

1.8 V NO. JA1 JA2 JA3 PARAMETER tc(rtck) tw(rtckL) tw(rtckH) tdc(rtck) tj(rtck) tR(rtck) tF(rtck) JA11 td(rtckL-tdoV) tR(tdo) tF(tdo) (1) Cycle time Typical pulse duration, jtag_rtck low Typical pulse duration, jtag_rtck high Duty cycle error, jtag_rtck Jitter standard deviation Rise time, jtag_rtck Fall time, jtag_rtck Delay time, jtag_rtck low to jtag_tdo valid Rise time, jtag_tdo, Fall time, jtag_tdo -14.6 MIN 20 10 10 -2500 2500 33.33 4 4 14.6 4 4 -14.6 MAX MIN 20 10 10 -2500 2500 33.33 4 4 14.6 4 4 3.3 V MAX UNIT ns ns ns ps ps ns ns ns ns ns
The jitter probability density can be approximated by a Gaussian function.

JA4 JA5 jtag_tck JA7 jtag_tdi JA9 jtag_tms JA1 JA2 jtag_rtck JA11 jtag_tdo
030-114
JA6 JA8 JA10
JA3
Figure 6-74. JTAG Interface Timing Adaptive Clock Mode
213
AM3517, AM3505
7 PACKAGE CHARACTERISTICS
7.1 Package Thermal Resistance
Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the AM3517/05 . Table 7-1. AM3517/05 Thermal Resistance Characteristics (1)
PACKAGE ZCN Pkg. ZER Pkg. (1) POWER (W) 1.6 1.6 RJA(C/W) 24.58 15.8 RJB(C/W) 10.81 6 RJC(C/W) 6 BOARD TYPE Figure 6-31 2S2P 2S2P
RJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, C/W RJB (Theta-JB) = Thermal Resistance Junction-to-Board, C/W RJC (Theta-JC) = Thermal Resistance Junction-to-Case, C/W
7.2 7.2.1
Device Support Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all AM3517/05 microprocessors and support tools. Each device has one of three prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS). Device development evolutionary flow: X P null Experimental device that is not necessarily representative of the final devices electrical specifications and may not use production assembly flow. (TMX definition) Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. (TMP definition) Production version of the silicon die that is fully qualified. (TMS definition) Support tool development evolutionary flow: TMDX TMDS Development support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: Developmental product is intended for internal evaluation purposes. Production devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TIs standard warranty applies. Predictions show that prototype devices (X or P), have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. For additional description of the device nomenclature markings, see the AM35x Processor Silicon Errata (literature number SPRZ306).
214
PACKAGE CHARACTERISTICS Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505
AM3517, AM3505
X PREFIX X = Experimental Device P = Prototype Device blank = Production Device DEVICE SILICON REVISION
AM3517
ZCN
( )
( ) blank = no security C = crypto enabled blank = commercial temperature A = extended temperature
PACKAGE TYPE ZCN = 491-pin sPBGA ZER = 484-pin sPBGA
Figure 7-1. Device Nomenclature
7.2.2
7.2.2.1
Documentation Support
Related Documentation from Texas Instruments
The following documents describe the AM3517/05 . Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com. The current documentation that describes the AM3517/05 ARM Microprocessor, related peripherals, and other technical collateral, is available in the product folder at: www.ti.com. SPRUGR0 AM35x ARM Microprocessor Technical Reference Manual. Collection of documents providing detailed information on the SitaraTM architecture including power, reset, and clock control, interrupts, memory map, and switch fabric interconnect. Detailed information on the microprocessor unit (MPU) subsystem as well a functional description of the peripherals supported on AM3517/05 devices is also included.
7.3
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
7.3.0.2
Related Documentation from Other Sources
The following documents are related to the AM3517/05 . Copies of these documents can be obtained directly from the internet or from your Texas Instruments representative. Cortex-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8 processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. Please see the AM3517/05 ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the revision of the Cortex-A8 core used on your device. ARM Core CortexTM-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. Please see the AM3517/05 ARM Microprocessor Silicon Errata (literature number SPRZ306) to determine the revision of the Cortex-A8 core used on your device.
215
AM3517, AM3505
7.4
Mechanical Data
216
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2011
PACKAGING INFORMATION
Orderable Device AM3505AZCN AM3505AZCNA AM3505AZCNAC AM3505AZCNC AM3505AZER AM3505AZERA AM3505AZERAC AM3505AZERC AM3517AZCN AM3517AZCNA AM3517AZCNAC AM3517AZCNC AM3517AZER AM3517AZERA AM3517AZERAC AM3517AZERC Status
(1)
Package Type Package Drawing NFBGA NFBGA NFBGA NFBGA BGA BGA BGA BGA NFBGA NFBGA NFBGA NFBGA BGA BGA BGA BGA ZCN ZCN ZCN ZCN ZER ZER ZER ZER ZCN ZCN ZCN ZCN ZER ZER ZER ZER
Pins 491 491 491 491 484 484 484 484 491 491 491 491 484 484 484 484
Package Qty 90 1 90 450 60 60 300 300 1 90 90 90 60 60 300 300
Eco Plan
(2)
Lead/ Ball Finish SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU SNAGCU
MSL Peak Temp
(3)
Samples (Requires Login)
ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2011
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. 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AM3517, AM3505

www.ti.com SPRS550C OCTOBER 2009 REVISED MARCH 2011

AM3517/05 Sitara ARM Microprocessors

1 AM3517/05 Sitara ARM Microprocessor

Copyright 20092011, Texas Instruments Incorporated

Copyright 20092011, Texas Instruments Incorporated

Functional Block Diagram

USB transceivers / device ports [3]

L2$ 256K 64 HECC EMAC Async 64 64 64

POWERVR TM SGX Graphics Accelerator (AM3517 only)

32 Channel System DMA

HS/FS/ LS USB Host

USB PHY USB OTG Controller

64K On-Chip RAM

132K On-Chip BOOT ROM

System Controls PRCM

External Peripherals Interfaces

External DDR2/ mDDR

NAND/NOR/ FLASH, SRAM

Emulation Debug: ETM, JTAG

Figure 1-1. AM3517/05 Functional Block Diagram

Copyright 20092011, Texas Instruments Incorporated

ZCN and ZER Package Differences

Copyright 20092011, Texas Instruments Incorporated

VIDEO DAC SPECIFICATIONS

................................ 97 .................... 100 Interface Description .............................. 101

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS ................................. 106

106 106 107 108 150 155 196 210

Contents Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505

Copyright 20092011, Texas Instruments Incorporated

Timing Requirements and Switching Characteristics

Copyright 20092011, Texas Instruments Incorporated

Contents Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505

Copyright 20092011, Texas Instruments Incorporated

SPRS550C OCTOBER 2009 REVISED MARCH 2011

VDDS_ DPLL_MPU _USBHOST

DSS_DATA13 DSS_DATA12 DSS_DATA11 DSS_DATA10

DSS_DATA18 DSS_DATA17 DSS_DATA16 DSS_DATA15 DSS_DATA14

Figure 2-1. ZCN Pin Map [Quadrant A]

Copyright 20092011, Texas Instruments Incorporated

VDDS_SRAM CAP_VDD_ _MPU SRAM_MPU

SYS _NRES WARM

SYS _NRES PWRON

UART3_RTS UART3_CTS GPMC_CLK _SD _RCTX

Figure 2-2. ZCN Pin Map [Quadrant B]

Copyright 20092011, Texas Instruments Incorporated

CAP_ VDDA1P2LDO _USBPHY

VDDS_SRAM CAP_VDD_ _CORE_BG SRAM_CORE

SDRC_ STRBEN _DLY0

Figure 2-3. ZCN Pin Map [Quadrant C]

Copyright 20092011, Texas Instruments Incorporated

SDRC_ STRBEN _DLY1

Figure 2-4. ZCN Pin Map [Quadrant D]

Copyright 20092011, Texas Instruments Incorporated

SPRS550C OCTOBER 2009 REVISED MARCH 2011

MCSPI2_CS1 MCSPI1_CS2 MCSPI1_SIMO MMC2_DAT1

VDDS_DPLL_ MPU_ USBHOST

DSS_DATA16 DSS_DATA15 DSS_DATA19 DSS_DATA14

DSS_DATA17 DSS_DATA23 DSS_DATA22 DSS_DATA12

DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0