SAVITRIBAI PHULE PUNE UNIVERSITY

Book let of Practical Skeleton Papers

For

F. Y. B. Sc (Computer Science), Semester – II

ELC-152-P: Electronics Practical Course - II

Structure of UG Program as per NEP - 2020

(From June 2024 - 2025)

1
 Index

Sr. Page
Title of the Experiment
No No.

GROUP A

A1 Realization of basic gates using discrete components

A2 Verification of logic gates by using digital ICs.

A3 Realization of basic gates using universal logic gates.

A4 Verification of De Morgan’s theorems.

A5 Study of half adder and full adder using logic gates.

A6 Study of half subtractor and full subtractor using logic gates.

A7 4-bit binary parallel adder and subtractor using IC7483.

A8 3-bit binary to Gray conversion using logic gates.

A9 3-bit Gray to Binary conversion using logic gates.

A10 Study of EX-OR gate as a 4-bit parity generator.

A11 Study of EX-OR gate as a 4-bit parity checker.

A12 Study of 1-bit digital comparator.

A13 Study of ALU using IC 74181.

A14 Study of multiplexer and de-multiplexer.

A15 Study of Decimal to BCD/Binary encoder.

A16 Study of Priority Encoder IC 74148

A17 Study of BCD to seven segment decoder using IC 7447

2
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester - II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A1: Realization of basic gates using discrete components.

1. Draw the circuit diagram of Basic logic gates and derived gates using discrete component.
2. Draw the Truth Table and Boolean equation of each gate.
3. Check circuit diagram from examiners and connect the circuit as per circuit diagram.
4. Check the connections from examiners.
5. Observe the output conditions for different combination of inputs.
6. Similarly verify the Truth table of different gates.
7. Write down Result and conclusions.
8. What do you mean by logic gate?
9. Draw symbol, truth table & Boolean equation of EX-OR gate.

3
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A2: Verification of Logic Gates using digital IC’s

1. Draw the Logic diagram of Basic/ Derived gates using digital IC’s.
2. Draw pin diagram of digital logic IC’s.
3. Draw the Truth Table and Boolean equation of each gate.
4. Check the diagrams from examiners and connect the circuit as per circuit diagram.
5. Check the connections from examiners.
6. Observe the output conditions for different combination of inputs.
7. Similarly, verify the truth tables of different gates.
8. Write down the result and conclusion.
9. Explain what is Truth Table?
10. Draw the symbol, truth table and Boolean equation of EX-NOR gate.
4
 Savitribai Phule Pune University
F.Y.B. Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A3: Realization of basic gates using Universal Gates.

1. Draw the circuit diagram of AND/ OR/ NOT/ NAND/ NOR logic gates using NAND/ NOR gates.
2. Draw the Truth Table and Boolean equation of each gate.
3. Check circuit diagram from examiners and connect the circuit as per circuit diagram.
4. Check the connections from examiners.
5. Observe the output conditions for different combination of inputs.
6. Similarly, verify the truth tables of different gates.
7. Write down Result and conclusions.
8. Why NAND and NOR gates are called as Universal gates?
9. Which logic gate is also called as Inverter? Draw its symbol.

5
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A4: Verification of De-Morgan’s Theorems.

1. State De-Morgan’s First and Second Theorem.
2. Draw the circuit/ logic diagram of De-Morgan’s First and Second Theorem.
3. Draw the Truth Table and Boolean equation of each Theorem.
4. Check circuit diagram from examiners and connect the circuit as per circuit diagram.
5. Check the connections from examiners.
6. Observe the output conditions for different combination of inputs.
7. Verify the LHS and RHS output logic according to truth table.
8. Write down Result and conclusions.
9. What do you mean by bubbled AND / OR gate?
10. What is the significance of De-Morgan’s Theorems?

6
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A5: Study of Half Adder and Full Adder using Logic gates.
1. Draw the circuit diagram of half adder and full adder logic circuit using logic gates.
2. Draw the observation table for half adder and full adder logic circuit.
3. Check circuit diagram from examiners and connect the circuit as per circuit diagram.
4. Check the connections from examiners.
5. Observe the output conditions for different combination of inputs.
6. Write down Result and conclusions.
7. Write down statements of half adder and full adder?
8. What is the use of EX-OR gate as controlled inverter?
9. Solve the following: 11011 + 10101 = ?

7
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A8: 4-bit binary to Gray conversion using logic gates.

1) Draw the truth table of 4 – Bit Binary to Gray code converter.
2) Draw 4 variable K-Map for Gray outputs of G0, G1, G2 and G3 with Boolean equations.
3) Draw Logic diagram according to Boolean equations.
4) Check the diagram from examiners and connect the circuit.
5) Check the connections from examiners.
6) Observe the output conditions for different combination of inputs.
7) Write down Result and Conclusion.
8) What is the significance of Gray code.
9) Convert Gray code into its Binary equivalent of 1101001.

8
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A9: 4-bit Gray to binary conversion using logic gates.

1) Draw the truth table of 4 – Bit Gray To Binary code converter.
2) Draw 4 variable K-Map for Binary outputs of B0, B1, B2 and B3 with Boolean equations.
3) Draw Logic diagram according to Boolean equations.
4) Check the diagram from examiners and connect the circuit.
5) Check the connections from examiners.
6) Observe the output conditions for different combination of inputs.
7) Write down Result and Conclusion.
8) What is K-Map? Which code is used to represent k-Map.
9) Convert Binary code into its Gray equivalent of 1001001.

9
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A10. Study of EX-OR gate as a 3-bit parity Generator.

1) Draw the circuit diagram of 3 - Bit parity Generator circuit.

2) Draw the observation table.
3) Check the diagram from examiners and connect the circuit.
4) Check the connections from examiners.
5) Observe the output for Even and Odd Parity conditions for different combination of inputs.
6) Write down Result and Conclusion.
7) What do you mean by Parity?
8) What is the odd parity bit for the data 110.

10
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A11. Study of EX-OR gate as a 3-bit parity Checker.

1) Draw the circuit diagram of 3 - Bit parity Checker circuit.

2) Draw the observation table.
3) Check the diagram from examiners and connect the circuit.
4) Check the connections from examiners.
5) Observe the output Error for Even and Odd Parity conditions for different combination of Data.
6) Write down Result and Conclusion.
7) What are the disadvantages of Parity checker circuit?
8) List the application of parity generator and checker circuit.

11
 Savitribai Phule Pune University
F.Y.B.Sc (Computer Sc.), Semester II
Electronics Practical Examination
(Pattern – NEP 2020)
Time Duration: 3 Hours Max. Marks: 35
Distribution of Marks

Circuit Diagram
Observations, Oral
OR Truth
Calculations,
Table/Boolean
Result & Preparatory
Equations, Logic Connections Experiment Total
Conclusion Experiment
Diagram
08 05 12 05 05 35

INSTRUCTIONS TO THE STUDENTS:

1. Read the Slip carefully and perform the experiment accordingly.
2. Do not Switch ON any Instruments/Circuit Board without prior permission of the Examiner.
3. Before taking observations, get the circuit connections checked from the Examiner.
4. Show at least one observation to the Examiner.
5. IC manual will be provided on demand.
6. Use of Non-programmable calculators is allowed.

A15: Study of Decimal to BCD/Binary encoder.

1) Draw the circuit diagram of Decimal to BCD Encoder circuit.
2) Draw the observation table and give its output equations.
3) Check the diagram from examiners and connect the circuit.
4) Check the connections from examiners.
5) Observe the output for different combination of Decimal inputs.
6) Write down Result and Conclusion.
7) Define Encoder and Decoder?
8) Write the output equations of Decimal to BCD Encoder circuit using OR gate.

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