Advanced Devices

By
Wael Fikry
Professor of Solid State Electronics
Eng. Physics Dept. – Faculty of Engineering
waelfikry@yahoo.com
Room 223

10/2/2023 Modern VLSI Devices 1

 COURSE OUTLINE
• Semiconductors Review
Energy Bands and Carrier Concentration in Thermal Equilibrium
Carrier Transport Phenomena
pn Junction

• MOS Capacitor
• Basic MOSFET
Long Channel Characteristics
MOSFET Mobility
Threshold Voltage and Ion Implantation
MOSFET Small Signal Equivalent Circuit

• Short channel devices

Boundary between long-channel and short channel devices
Channel Length Modulation
Geometry Effect on Threshold Voltage

10/2/2023 Modern VLSI Devices 2

Basic MOSFET
 Punchthrough
Reverse Short Channel Effect
Velocity Saturation
Drain Induced Barrier Lowering (DIBL)
Series Resistance

• High Field Effects

• SOI Devices
Partially and Fully depleted SOI MOSFET
Double and Multi Gates MOSFET

• Other FET Devices

10/2/2023 Modern VLSI Devices 3

Basic MOSFET
 Basic MOSFET
Long channel Characteristics

• Energy-Band Diagram

• Regions of Operation
Linear
saturation
Subthreshold

• Subthreshold Swing

10/2/2023 Modern VLSI Devices 4

 (a) Device configuration

(b) Flat-band zero-bias equilibrium

condition.

(c) Equilibrium condition under a

gate bias.

(d) Nonequilibrium condition under

both gate and drain biases.

10/2/2023 Modern VLSI Devices 5

 Current Voltage Characteristics
• Triode region:
– For long channel devices we can assume that electric field components
are independent of each other:
• Electric field in the y direction only produces depletion and inversion layers
• Electric field in the x direction drives drain current
– Let us consider a small section at a point x in the channel with a gate
voltage well above threshold and small Vd. As a result of the drain bias,
the inversion charge will be :
Qinv = −Cox (Vg − Vth − ) Vg Vd

– Where  is the channel potential component

due to drain bias. The channel current is a drift
current and can be written as :

Equation valid below I d = nevdrift A

saturation regime
= W nQinv

10/2/2023 Modern VLSI Devices 6

• Substituting x = -d/dx, we get I d dx = W nCox (Vg − Vth − )d
• Integrating from x = 0 to x = L and from  = 0 to  = Vd , we get

W
I d = Cox n (Vg − Vth )Vd − 12 Vd2  (1) Simplified mostly used for digital design
L
• In the above derivation, it has been assumed that Vth is independent of , this is
only valid for small values of Vd. In case of large Vd, Vth depends on  as it
affects QB. Without such assumption, the drain current becomes:

Vg = -12 V
I d = n Cox (Vg − ms − 2 B + ox − d )Vd
W Q V Eq.(1)
L Cox 2
(2)

Id (mA)
Eq.(2)
2 2q si N a
− [(Vd + 2 B )3/ 2 − (2 B )3/ 2 ] Eq.(1)
3 Cox
Vg = -8 V

Accurate for linear & triode regions Eq.(2)

Vd (V)

10/2/2023 Modern VLSI Devices 7

• Saturation region:
– As Vd increases, it neutralizes the effect of Vg the inversion layer starts to
disappear near the drain. The channel becomes pinched off at a voltage
Vd =Vdsat beyond which the drain current saturates with Vd.
– The condition for onset of current saturation is given by setting Qinv = 0,
hence:
 = Vg − Vth = Vdsat

– Where Vdsat is the “Drain Saturation Voltage” which is equal to at the drain end
of the channel. Substituting the above expression into the approximate Id-Vd
relationship yields:
nCoxW
I dsat = (Vg − Vth )2
2L
– This eqn is valid at the onset of saturation, beyond that, Id saturates at a constant
value. Therefore, this eqn also predicts Id for higher Vd values.

10/2/2023 Modern VLSI Devices 8

 Long channel Characteristics
1- Linear Region (small Vd)
The strong inversion drift drain
current of an n-channel MOSFET

 C (V −V ) V
W
I d
= ox g th d
L

2- Saturation Region
The well known quadratic relation

W  C (V − V )
2

=
ox g th
I dsat
2L

10/2/2023 Modern VLSI Devices 9

 3- Subthreshold region
weak inversion region Vg <Vt

• Subthreshold behavior is of particular

of low power-low voltage applications

• Subthreshold conduction is dominated

by Diffusion current

Subthreshold Swing
dV g
S=
d log( I d )

KT  C d _ max +C it 
= ln(10) 1+  Slope = 1/S
q  C ox 
Cit  interface charge capacitance
Insensitive to device parameter

10/2/2023 Modern VLSI Devices 10

 x
n n(0) − n(L)
I d = AqDn  AqDn
x L y

where n(0) and n(L) are the electron densities

in the channel at the source and drain. 1.E-02 1.4

1.E-03
The above equation leads to 1.2
Vd = 1V
1.E-04
2
 kT 
 C ox  1−e−qV d / kT 
W 1

Id = 1.E-05
L  q   

 eq(V g − V th ) / kT
0.8
1.E-06

Id(mA)
Id(A)
Vd = .5V
1.E-07
0.6

For Vd > 3kT/q 1.E-08

 q (V g − V th ) / KT 0.4

I d e 1.E-09

I d =  C ox (V g − V t )V d0.2
W
1.E-10 L

Independent of Vd
1.E-11 0
0 0.5 1 1.5 2
Vg(v)

10/2/2023 Modern VLSI Devices 11

 Definitions & Helpful Remarks
• Effective Electric Field eff Per
unit
eff is the average vertical electric field experienced by the carrier in the area

inversion Layer

 q
A=
 q
 =
 Q

s s
From Gauss’s law .d A =

y
 si o y
 si o
QB Qinv + QB
Qinv  si o  si o
Qy Ey
x
y

QB

y y
=
(Q B
+ Q inv
) where  = 1/2 for electron
eff
 si o
= 1/3 for holes

10/2/2023 Modern VLSI Devices 12

 Definitions & Helpful Remarks
• Effective Electric Field eff
eff is the average electric field experienced by the carrier in the inversion Layer

=
(Q B
+ Q inv
) where  = 1/2 for electron
eff
 si o
= 1/3 for holes
In strong inversion

Qinv = C ox (V g − V th )   QB
C ox
= ox o
V th = V FB + 2 B −
T ox C ox

(elec.) =
(V th
+ V FB + 2
B
) + (V g
− V th )
eff
3T ox 6T ox

For n-channel MOSFET V FB + 2 B  0

(elec.) =
(V +V ) g th strong inversion
eff
6T ox only

10/2/2023 Modern VLSI Devices 13

MOSFET Mobility
Four types of charges densities
exist at or near the interface:
1- Inversion layer charge Qinv,

2- Bulk ionized impurity charge QB,

3- Fixed positive charge Qf

The Si-SiO2 interface region of an MOSFET
4- Interface state charge Qit and the charge distributions

PHYSICAL MECHANISMS INVOLVED IN MOSFET CARRIER

SCATTERING
Phonon scattering
3

 1 T 2
Surface roughness scattering Coulomb scattering
 =T ( Q + Q )
ph

Ionized Impurity Scattering

3
+
 sr
1 (Qinv+Q B) 2 +
c it f

T
 T Q
2

 I

NI c
−1
inv

10/2/2023 Modern VLSI Devices 14

 The electron and hole mobilities of
silicon at 300 K. Temperature dependence of the
electron mobility in Silicon

At low dopant concentration, the electron mobility is dominated by phonon scattering.

At high dopant concentration, it is dominated by impurity ion scattering

10/2/2023 Modern VLSI Devices 15

 Coulomb surface
• The location of the carriers at and scattering Low
Temperature
roughness
scattering
near the oxide-semiconductor Phonon
scattering

Mobility
interface introduces additional
High
scattering mechanisms like Coulomb Total Temperature
Mobility
scattering from oxide charges and
interface states as well as the surface =
(Q B
+ Q inv
)
eff

roughness scattering. si

Effective Field eff

• Each scattering mechanism is
associated with a specific mobility.
The net mobility is determined by
Mathiessen's rule :

1/ = 1/1 + 1/2 + 1/3.

The lowest mobility is the dominating

one.

10/2/2023 Modern VLSI Devices 16

• In the low-field region, the total carrier surface mobility o (low-field mobility)
is approximated by : 1 1 1
= +
 O
 B
 S

Where B is bulk carrier mobility and S is the contribution of the additional

scattering centers due to the surface boundary at low field condition

• The surface mobility depends on x

the vertical (y or  eff )and lateral
( x) electric fields in the channel. y

eff (cm2/V-s)

eff / B
y
 (V g −V t ) & x
 V d/L
<100> Si
• MOSFET (Effective) mobility due NA = 1015 cm-3
B = 1500 cm2/V-s
to the vertical and lateral fields can
be expressed as: y(V/cm)

 eff = 1 + 
O


(V g − V t ) 1 + x

c  Mobility Verses Vertical Field

10/2/2023 Modern VLSI Devices 17

 Coulomb scattering
 =T ( Q + Q
c it f
)

eff (V/cm)

Experimental variation of effective mobility as a function of

normal effective field for various values of fixed charge density

=
( Q B
+ Q inv
)
eff
 si o

where  is inversion charge weighing factor. Experimentally  is found to be in the

range from 1/3 to 1 depending on the channel type (n or p) and temperature .

10/2/2023 Modern VLSI Devices 18

 eff (V/cm)
Experimental variation of effective mobility as a function of normal
effective field for various values of doping concentrations

10/2/2023 Modern VLSI Devices 19

 Weak Inversion and Screening Effect

Theoretical
Surface roughness scattering

Screening effect

Experimental

Room-temperature effective mobility (solid curves) as a function of average inversion

charge density. The dotted lines represent the calculated microscopic mobility. (After
Wikstrom and Viswanthan)

10/2/2023 Modern VLSI Devices 20

 Temperature Effect on MOSFET Mobility

eff (V/cm)

10/2/2023 Modern VLSI Devices 21

 Threshold Voltage and Ion Implantation
• It is possible to obtain close control of Vth
by ion implantation, because very precise
quantities of impurity can be introduced.

• The Figure illustrates the result of a boron

implantation through the gate oxide of an
n-channel MOSFET such that the implant
dose peak occurs at the Si-SiO2 interface.

• The negatively charged, boron

acceptors increase the doping level of
the channel. As a result, Vth increases.

• Similarly, a shallow boron implant into

a p-channel MOSFET can reduce Vth

10/2/2023 Modern VLSI Devices 22

Substrate Sensitivity
(Body effect)
The effect of reverse substrate
bias is to:
• Widen the bulk depletion
region
Negative for
• Raise the threshold voltage. p-substrate

• Reduce the effective 14

mobility.

( )
12

V th
=V FB
+ 2 +  2 −V bs 10
B B

8 Vbs = 0V
ID (mA)

Where  is the body effect 6

-1V

coefficient -2V
4 -3V

2 si o q N A 2

 = 0
C ox 0.5 1 1.5
Vg (V)
2 2.5 3

10/2/2023 Modern VLSI Devices 23

Threshold-voltage variation with
reverse bias for two uniform substrate
doping concentration

2 si o q N A
 =
C ox

Body effect coefficient variation

with substrate doping for different
oxide thickness

10/2/2023 Modern VLSI Devices 24

 Definitions & Helpful Remarks
The unified mobility model
It is an empirical model that fits the experimental data very well in strong inversion
and based on the effective field concept

 = o

( Eo)
eff v
1+ eff
where Eo and v are parameters for electrons and holes

• The above power function expression is not suitable for circuit simulation.
• Using Taylor expansion and introducing new term to include high body bias
will lead to
o
 eff =
 (V g + V th)
2
1 + (U a + U cV bs )
V g + V th +Ub
T ox  
 T ox 
where Ua, Ub and Uc are parameters to be determined from I-V data

10/2/2023 Modern VLSI Devices 25

The following empirical mobility models are available in BSIM3.3.2
and account for he influence of the vertical electric field only

mobMod=1
o
 eff =
V gsteff + 2V th  V gsteff + 2V th 
2
1 + (U a + U c V bseff )   + Ub 
 T ox   T ox 

mobMod=2 (depletion mode devices)

o
 eff =
2
V gsteff  V gsteff 
1 + (U a + U c V bseff )  +
 Ub 
 T ox   ox 
T
mobMod=3
o
 eff =
 
 V gsteff + 2V th 
2
V gsteff + 2V th  
1 + U a 
 
 + Ub  (1 + U c V bseff )
T ox   T 
 ox 

10/2/2023 Modern VLSI Devices 26

 MOSFET Small Signal Equivalent Circuit
Simplified low frequency small signal equivalent circuit
The dc drain current (Id) of MOSFET was found to be a function of Vd and Vg
I d = f (V d ,V g )

When ac drain voltage (vd) and gate voltage (vg) are superimposed on the dc voltages
(Vd, Vg), the drain current modified to id + Id where id is the ac component.

Using Taylor expansion we obtain:

High gm
I d I d
& zero gd
id
i = v + v G D
V d V g
d d g

Vg Vd

vg gmvg rds=1/gd
or i d
= g v d
+ g v g
d m

gd is the output conductance S S

(output resistance rds= 1/ gd )

gm is the transconductance

10/2/2023 Modern VLSI Devices 27

Transconductance & Conductance

If we consider long channel MOSFETs and constant Mobility

Linear region Saturation region

 
g m (linear ) = I d g m (saturation ) = I d
V g V g
=
 W
 ( )  =
 W
 C (V −V )

2
C V −V V
V g L ox g th d
V g 2L ox g th

= W  C ox V d = W  C ox (V −V ) g th
L L

 
g d (linear ) = I d g d (saturation ) = I d
V d V d
=

 ( )  =

 ( )
2
W W
C V −V V C V −V
V d L ox g th d
V d 2L ox g th

=W  C ox (V g −V th )
= Zero
L

10/2/2023 Modern VLSI Devices 28

 Inherent Resistances and Capacitances in MOSFETs

Overlap Capacitors

gmvg

Substrate to Source
and Substrate to p-n junction depletion
Drain Resistances Gate to Source and Gate
to Drain capacitances capacitances

10/2/2023 Modern VLSI Devices 29

CGDT = CGD + COD  Total Drain to Gate Capacitor

• Provides undesirable feedback between the input and output

• In saturation region for long MOSFET, CGDT ~ COD (very small)
where CGD → 0

CGST = CGS + COS  Total Drain to Source Capacitor

• In the ideal long channel MOSFET CGST ~ CGS → Cox WL

10/2/2023 Modern VLSI Devices 30

Frequency Limitation Factors

There are two basic frequency limitation factors in the MOSFET:

1. The first factor is the channel transit time (τ) = L/vsat
If vsat = 107 cm/s and L = 0.25 m, then  = 2.5 ps, which translates into a maximum frequency of 400 GHz.

• This frequency is much larger than the typical maximum frequency response of a MOSFET.
• The transit time of carriers through the channel is usually not the limiting factor in the
frequency responses of MOSFETs

2. The second limiting factor is the gate

capacitance charging time.
For long channel MOSFETs, we can neglect RS, RD, vsat
junction capacitances and substrate resistance

10/2/2023 Modern VLSI Devices 31

Frequency Limitation Factors
There are two basic frequency limitation factors in the MOSFET:

1. The first factor is the channel transit time (τ) = L/vsat

If vsat = 107 cm/s and L = 0.25 m, then  = 2.5 ps, which translates into a maximum frequency of 400 GHz.

• This frequency is much larger than the typical maximum frequency response of a MOSFET.
• The transit time of carriers through the channel is usually not the limiting factor in the
frequency responses of MOSFETs

2. The second limiting factor is the gate CGDT id

capacitance charging time. G D

For long channel MOSFETs, we can neglect RS, RD,

vg CGST gmvg RL vd
junction capacitances and substrate resistance

Simplified high frequency small signal S S

equivalent circuit
(RL is a load resistance and rds = )

10/2/2023 Modern VLSI Devices 32

Cutoff Frequency (fT)
CGDT
G D

The cutoff frequency is defined to be the frequency at Ii Id

vg CGST gmvg RL
which the current gain of the device is unity, Id
=1
Ii
S S
For ideal long MOSFET biased in saturation region

CGDT ~ o CGST ~ Cox WL g m =W  C ox (V g −V th )

L

I i = j  C GSTV g Id = g mV g

Id gm  (V g −V th )
At cutoff frequency = =1 fT = (saturation )
Ii 2 f T C GST 2 L2

The general expression of gm

fT =
fT for the circuit 2 [C GST + C GDT (1 + g m R L )]
(Normally,  RL CGDT <<1)

10/2/2023 Modern VLSI Devices 33

Body effect due to Vds
Because of drain voltage Vds, the
depletion width along the channel
is not uniform.

The threshold voltage will be a

function of the position along the
channel:

V th ( y) = V th (0) − aV ( y) G
id
D

vg gmvg rds=1/gd RL

Where y is the distance from the source.

S S
Vth(0) means the threshold voltage at the source
V
a is a function of Vbs , S and  Voltage gain = o
Vi

10/2/2023 Modern VLSI Devices 34

 Equilibrium Case
2 si o ( 2 B )
pn Diode Gated Diode x dm =
qN A
xdm

Vox
n+ Vgs
s p

VVgsgs= Vth

V gs =V FB +V ox +  s

@ Vgs =Vth

QB = qN a X dm = 2 si o qN A ( 2 B )

QB
V ox = =  2 B 2kT  N A 
C ox  s = 2 B = ln  
kT  N A N D 
q  ni 
 bi =
q  ni2 
ln 
V gs =V FB + 2 B +  2 B

10/2/2023 Modern VLSI Devices 35

 Non-Equilibrium Case
pn Diode Gated Diode
2 si o ( 2 B − Vbs )
x dm =
qN a
xxdmdm
VVbsbs VVbsbs
Vox
VVbsbs
VRbs n+ Vgs
s p

+
Vbs
-
VVgsgs
VVgsgs
V gs −V bs =V FB +V ox + s


s
s 22 B
B

V R +  bi @ Vgs =Vth and Vbs < 0

V bs ++ bi  s (invs )s===V2Vbsbs B++2−B
2V
B bs

Q = qNV X
B
bs
a
bi
dm

= 2 si o qN a ( 2 B − Vbs )

QB
V ox = = ( 2 B −V bs )
C ox
QB
V th −V bs =V FB +
C ox
+ 2 B −V bs V th =V FB + 2 B +  ( 2 B −V bs )

10/2/2023 Modern VLSI Devices 36

 Equilibrium Non-Equilibrium

Xdm Xdm

QB QB

Qinv Qinv

q V bs

10/2/2023 Modern VLSI Devices 37

 Comments on report 1

• The electrons are distributed extremely

closed to the surface with an inversion
layer width less than 50 Ao

• It is clear that before the s = 2B

condition, the charge in the silicon is
predominantly of the depletion type

Qinv
• Almost all of the increase of Qs beyond
s = 2B is taken by Qinv with a slope
dQinv/dVg  Cox

10/2/2023 Modern VLSI Devices 38