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Plan_Verification

The document outlines a three-week training program focused on System Verilog and UVM, detailing daily topics such as data types, testbench design, and UVM components. It includes practical projects like FIFO verification and building a simple UVM testbench, along with a final project and interview preparation. The curriculum emphasizes both theoretical knowledge and hands-on experience in verification methodologies.

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nithyanand160
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9 views2 pages

Plan_Verification

The document outlines a three-week training program focused on System Verilog and UVM, detailing daily topics such as data types, testbench design, and UVM components. It includes practical projects like FIFO verification and building a simple UVM testbench, along with a final project and interview preparation. The curriculum emphasizes both theoretical knowledge and hands-on experience in verification methodologies.

Uploaded by

nithyanand160
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Week 1: System Verilog + Testbench Design

Day Topics

1 SV Data Types, Operators, Modules

2 Procedural Blocks, Initial/Always, Delays

3 Testbench Basics, Tasks, Functions

4 Interfaces, Clocking Blocks, Mod ports

5 OOP in SV (class, inheritance, polymorphism)

6 Mailbox, Semaphore, Randomization (basic)

7 Mini Project: Basic FIFO Verification TB

Week 2: UVM – Environment & Component Structure


Day Topics

8 UVM Overview, UVM Phases, UVM Macros

9 UVM Components (driver, monitor, sequencer)

10 Sequence, Sequence Item, Factory Pattern

11 Scoreboard, Coverage, TLM Ports


Day Topics

12 Build a Simple UVM TB (Adder/ALU)

13 Connect and Run UVM Test, Analysis Ports

14 UVM TB Debugging + Assertions Intro

Week 3: Assertions, Coverage, Projects & Interview


Day Topics

System Verilog Assertions:


15
Immediate/Concurrent
16 SVA: Sequences, Properties, Implication

17 Functional Coverage: coverpoint, bins, cross

18 Coverage + Assertions in UVM TB

Final Project: AXI-lite/UART/Custom FSM UVM


19
TB
20 Interview Prep (Quizzes, Mock Qs, Git upload)

21 Full-day Review + Make Portfolio Slides

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