Scribd
Upload
4 views4 pages

That's My Choice

This 6-month study plan outlines a structured approach for beginners to become job-ready in ASIC RTL design, synthesis, and static timing analysis. It covers essential topics such as digital design basics, Verilog coding, ASIC design flow, and advanced design techniques, with mini projects and practical applications throughout. The final month focuses on resume preparation, interview practice, and completing a final project to solidify learning and facilitate job applications.

Uploaded by

abhijitkarale55
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
4 views4 pages

That's My Choice

This 6-month study plan outlines a structured approach for beginners to become job-ready in ASIC RTL design, synthesis, and static timing analysis. It covers essential topics such as digital design basics, Verilog coding, ASIC design flow, and advanced design techniques, with mini projects and practical applications throughout. The final month focuses on resume preparation, interview practice, and completing a final project to solidify learning and facilitate job applications.

Uploaded by

abhijitkarale55
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

6-Month Weekly Study Plan for ASIC Design (Beginner Level)

Goal: Start from zero knowledge and become job-ready in ASIC RTL design,
synthesis, and STA.

Month 1: Digital Design Basics + Intro to Verilog


Week 1:
 Number systems, binary, hex, ASCII
 Logic gates (AND, OR, NOT, XOR)
 Boolean algebra, simplification
 Combinational circuits overview
Week 2:
 Multiplexers, Encoders, Decoders, Comparators
 Adders (half, full), Subtractor, Arithmetic circuits
 Design 4-bit adder/subtractor in theory
Week 3:
 Sequential circuits intro: Flip-Flops (D, T, JK)
 Latches vs Flip-Flops, timing diagrams
 Counters (async/sync), shift registers
Week 4:
 Finite State Machines (FSMs): Mealy vs Moore
 Basic FSM examples (elevator, vending machine)
 Introduction to Verilog: modules, ports, syntax
 Install EDA Playground / ModelSim (or similar)

Month 2: RTL Design with Verilog


Week 5:
 Data types, operators, expressions in Verilog
 Blocking vs Non-blocking
 Combinational design in Verilog: MUX, ALU, encoder
Week 6:
 Sequential design in Verilog: FFs, counters, FSMs
 Design a traffic light controller in Verilog
 Simulate using testbenches
Week 7:
 Parameterized modules
 Testbenches: initial, always, $display, $monitor
 Write testbenches for counter, mux, FSM
Week 8:
 Mini Project: UART Transmitter RTL + TB
 Code review and simulation
 Resume first Verilog project on GitHub

Month 3: ASIC Design Flow + RTL Coding Guidelines


Week 9:
 ASIC design flow: RTL -> Synthesis -> STA -> P&R -> GDSII
 Roles in front-end and back-end
 RTL coding styles for synthesis
Week 10:
 Timing violations: setup and hold
 Clocking issues: skew, jitter
 Writing SDC constraints (overview)
Week 11:
 Introduction to Synthesis
 Logic optimization basics
 Using Design Compiler (if access)
Week 12:
 Linting tools (SpyGlass concept)
 Clock domain crossing (CDC) issues
 Mini Project: ALU with Synthesis guidelines

Month 4: Static Timing Analysis (STA)


Week 13:
 Delay calculation basics
 Setup time, hold time
 Slack calculation
Week 14:
 Timing paths: launch/capture, combinational delay
 STA report reading
 Practice timing reports (sample files)
Week 15:
 False paths, multi-cycle paths
 Clock constraints and generated clocks
 Write .sdc files (basic practice)
Week 16:
 Mini Project: Timing analysis of a simple design
 Review RTL and timing
 Document findings in report

Month 5: Advanced Design Topics + Mini Projects


Week 17:
 FSM optimization
 Power-aware design basics
 Low power techniques (clock gating)
Week 18:
 Synthesis with constraints
 Run area/timing analysis
 Netlist vs RTL simulation comparison
Week 19:
 AXI-lite protocol overview (intro only)
 Memory interfacing basics (ROM, RAM, FIFO)
Week 20:
 Mini Project: UART + FIFO design with testbench
 Write report, document block diagram, flow

Month 6: Resume, Interview Prep & Final Projects


Week 21:
 Resume prep: add Verilog projects, tools
 GitHub cleanup and upload
 LinkedIn profile update
Week 22:
 Interview questions (Digital + Verilog)
 Mock interview with friends/peers
 GATE-level questions on FSM, counters
Week 23:
 Final Project: RTL + TB + STA for ALU or UART
 Full documentation with block diagram, flow
Week 24:
 Apply to internships/jobs
 Network on LinkedIn
 Review and reflect on learning journey

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy