Microelectronic Devices

(DSE – 2)
Practical File

Submitted By

Sarvesh Kumar
Roll No.: 23294917080 (Batch: ECE-B)
B. Tech Electronics and Communication Engineering
(Semester IV)

To

Mr. Khushwant Sehra

(Assistant Professor)
Department of Electronics and Communication Engineering

FACULTY OF TECHNOLOGY
UNIVERSITY OF DELHI
NEW DELHI – 110007
(2024 – 2025)
 Record of Experiments

S. No. Experiment Title Page No. Date Remarks

1 Experiment 1: Study the transfer 1
and drain characteristics of NMOS
2 Experiment 2: Study the transfer 6
and drain characteristics of PMOS

3 Experiment 3: Study the 11

characteristics of Psuedo NMOS
inverter
4 Experiment 4: Study the 17
characteristics of CMOS inverter
5 Experiment 5: To observe the 26
waveform of Ring Oscillator at
different stages
6 Experiment 6: 2:1 Multiplexer Using 34
Transmission Gates
7 Experiment 7: Half Adder Using 41
Pass Transistor Logic
Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 1

Experiment 1
NMOS

1.1 Aim
• To study ID-VDS characteristics of NMOS at constant VGS

• To study ID-VGS characteristics of NMOS at constant VDS

• Analyse the Transconductance and Transresistance

1.2 Theory
• An NMOS (N-type Metal-Oxide-Semiconductor) transistor is a type of MOSFET
where current flows through an N-type channel when a voltage is applied to the
gate terminal. It consists of three main terminals: gate (G), drain (D), and source
(S).

• An NMOS transistor, a type of MOSFET, operates by forming a conductive N-type

channel between its drain (D) and source (S) terminals when a positive voltage
exceeding the threshold is applied to its gate (G). This turns the transistor on,
allowing current to flow from drain to source. In digital logic circuits, NMOS
transistors are commonly used in pull-down networks: when the gate receives a
high input (logic 1), the transistor conducts and pulls the output to a low state
(logic 0). When the gate voltage is below the threshold (logic 0), the transistor
turns off, blocking current flow and allowing the output to be pulled high (logic 1),
often via a pull-up resistor or a complementary PMOS transistor.

• NMOS transistors are favored for their high electron mobility, which provides better
conductivity and faster switching speeds compared to PMOS transistors. However,
when used alone, they can consume static power in the on-state, as continuous
current may flow without additional control mechanisms.

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 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 1

Figure 1.1: NMOS circuit

1.3 LTspice Code

1.3.1 NMOS Characterstics Analysis

Listing 1.1: Task-1:Drain Characteristics of NMOS

1 % IV of MOSFET
2 . in clude " M od e l_ file . txt" ; Inclu de our MOSFET model file
3
4 VDS drain source DC 0 ; Vo ltag e source from drain to source
5
6 VGS gate source DC 0 ; Voltage source from gate to source
7
8 M1 drain gate source 0 NMOS_MOD W =10 u L=1 u
9
10 ; NMOS transistor instance
11
12 . no deset V( source ) =0 ; Helps DC solver at 0 V for source
13 . dc VDS 0 10 0.01 VGS 0 5 1 ; Sweep VDS from 0 to 10 in steps of Nested
sweep :
14 . print V( VDS) Id( M1 )
15 . end

Listing 1.2: Task-2 : Transfer characteristics of NMOS

1 % IV of MOSFET
2
3 . include " Mo de l_ file . txt" ; Include our MO SFET model file
4
5 VDS drain source DC 0 ; Voltag e source from drain to source
6 VGS gate source DC 0 ; Voltage source from gate to source
7
8 M1 drain gate source 0 NMOS_MOD W =10 u L=1 u
9
10 ; NMOS transistor instance
11
12 . no deset V( source ) =0 ; Helps DC solver at 0 V for source
13 . dc VGS 0 5 0.01 VDS 0 1 0.2 ; Sweep VDS from 0 to 10 in steps of
14
15 ; Nested sweep : VGS from 0 to 5 in steps of 1
16

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 Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 1

17 . print V( VDS) Id( M1 )

18 . end

1.4 Result

Listing 1.3: Task-1:Calculation of Threshold Voltage

1 Upon studyin g the transfer ch a r a c te r is itc s of our NMOS device , we
place the cursor on the point where the graph starts in cr ea sin g
ra pidly and clearly
2
3 Vth =0.75 v

Figure 1.2: Drain Characteristics

Figure 1.3: Transfer Characteristics

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Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 1

Figure 1.4: Transconductance-gm

Figure 1.5: Transresistance-gd

Figure 1.6: Threshold Voltage

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Roll No.: 23294917080 | B. Tech. ECE B--B2 Experiment 1

1.5 Observation
• Based on the SPICE simulation results depicted in the provided graphs, the NMOS
transistor’s performance was thoroughly analyzed across multiple parameters.

• The drain characteristics (Figure 1.3) illustrate how drain current (ID) increases
with VGS, transitioning from cutoff to triode and saturation regions as VDS rises,
with distinct curves for VGS values of 0.5V to 5V, peaking around 3.6mA at higher
voltages.

• The transconductance (gm) plot (Figure 1.4) shows gm peaking in the saturation
region, reaching values up to 1.2mS around 2V to 3V of VGS, reflecting the
transistor’s amplification capability, before declining as VDS increases further.

• The transresistance (gd) graph (Figure 1.5) indicates a steep initial drop from 2M to
below 0.1M as VGS rises from 0.5V to 2V, stabilizing in saturation, which highlights
the output resistance behavior.

• The threshold voltage (VTH) plot (Figure 1.6) confirms VTH at approximately 0.7V
to 1V, where ID begins to rise significantly, aligning with theoretical expectations.
These results collectively validate the NMOS’s operational behavior, showcasing its
efficiency in switching and amplification across the tested voltage ranges.

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Roll No.: 23294917070 | B. Tech. ECE Experiment 2

Experiment 2
PMOS

2.1 Aim
• To study ID-VDS characteristics of PMOS at constant VGS

• To study ID-VGS characteristics of PMOS at constant VDS

• Analyse the Transconductance and Transresistance

2.2 Theory
• A PMOS (P-type Metal-Oxide-Semiconductor) transistor, a variant of MOSFET,
conducts when a low voltage is applied to its gate terminal, featuring three essential
terminals: gate (G), drain (D), and source (S), much like its NMOS counterpart;
when the gate voltage falls below the threshold voltage (logic 0), the PMOS turns
on, forming a conductive path from source to drain that allows current to flow,
driving the output high (logic 1) in a pull-up network, whereas a high voltage at
the gate (logic 1) near the supply voltage (Vdd) turns it off, blocking current and
permitting the output to be pulled low (logic 0) by an NMOS or pull-down resistor.

• PMOS transistors are typically employed in pull-up configurations within logic

gates to deliver a strong logic ‘1’ by linking the output to VDD when active,
though they suffer from lower carrier mobility compared to NMOS, resulting in
less efficient conduction and often requiring larger sizes to match NMOS
performance in CMOS designs; while rarely used alone in complex logic due to
this limitation, their integration with NMOS in CMOS technology enables the
creation of power-efficient and rapid digital circuits.

Figure 2.1: Circuit Diagram on LTSpice

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 2

2.3 LTspice Code

2.3.1 PMOS VI characteristics

Listing 2.1: Task-1:Drain Characteristics of NMOS

1 % IV of MOSFET
2 . inc lude " Mo de l_ file . txt" ; Include our MOSFET model file
3
4 VDS drain source DC 0 ; Vo ltage source from drain to source
5
6 VGS gate source DC 0 ; Voltage source from gate to source
7
8 M1 drain gate source 0 PMOS_MOD W =10 u L=1 u
9
10 ; NMOS transistor instance
11
12 . no deset V( source ) =0 ; Helps DC solver at 0 V for source
13 . dc VDS 0 -10 0.1 VGS 0 -5 -1 ; Sweep VDS from 0 to 10 in steps of
Nested sweep :
14 . print V( VDS) Id( M1 )
15 . end

Listing 2.2: Task-2 : Transfer characteristics of PMOS

1 % IV of MOSFET
2
3 . inc lude " Mo de l_ file . txt" ; Include our MOSFET model file
4
5 VDS drain source DC 0 ; Vo ltage source from drain to source
6 VGS gate source DC 0 ; Voltage source from gate to source
7
8 M1 drain gate source 0 PMOS_MOD W =10 u L=1 u
9
10 ; NMOS transistor instance
11
12 . no deset V( source ) =0 ; Helps DC solver at 0 V for source
13 . dc VGS 0 -5 0.01 VDS 0 -5 1 ; Sweep VDS from 0 to 10 in steps of
14
15 ; Nested sweep : VGS from 0 to 5 in steps of 1
16
17 . print V( VDS) Id( M1 )
18 . end

2.4 Result

Listing 2.3: Task-1:Calculation of Threshold Voltage

1 Upon studyin g the transfer ch a r a c te r isit cs of our PMOS device , we
place the cursor on the point where the graph starts inc re as in g
ra pidly and clearly
2
3 Vth =0.801 v

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Roll No.: 23294917070 | B. Tech. ECE Experiment 2

Figure 2.2: Drain Characteristics

Figure 2.3: Transfer Characteristics

Figure 2.4: Transconductance-gm

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Roll No.: 23294917070 | B. Tech. ECE Experiment 2

Figure 2.5: Transresistance-gd

Figure 2.6: Threshold Voltage

2.5 Observation
• Based on the SPICE simulation results depicted in the provided graphs, the NMOS
transistor’s performance was thoroughly analyzed across multiple parameters.
• The drain characteristics (Figure 1.3) illustrate how drain current (ID) increases
with VGS, transitioning from cutoff to triode and saturation regions as VDS rises,
with distinct curves for VGS values of 0.5V to 5V, peaking around 3.6mA at higher
voltages.
• The transconductance (gm) plot (Figure 1.4) shows gm peaking in the saturation
region, reaching values up to 1.2mS around 2V to 3V of VGS, reflecting the
transistor’s amplification capability, before declining as VDS increases further.

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Roll No.: 23294917070 | B. Tech. ECE Experiment 2

• The transresistance (gd) plot (Figure 1.5) indicates a steep initial drop from 2M to
below 0.1M as VGS rises from 0.5V to 2V, stabilizing in saturation, which highlights
the output resistance behavior.

• The threshold voltage (VTH) plot (Figure 1.6) confirms VTH at approximately 0.7V
to 1V, where ID begins to rise significantly, aligning with theoretical expectations.
These results collectively validate the NMOS’s operational behavior, showcasing its
efficiency in switching and amplification across the tested voltage ranges.

10
Roll No.: 23294917070 | B. Tech. ECE Experiment 3

Experiment 3
To study the characteristics of resistor load
psuedo NMOS inverter

3.1 Aim
• Build psuedo NMOS inverter and initiate DC sweep.

• Noise Margin Calculation

• Effect of Supply Voltage Variation

• Effect of W/L Ratio Mismatch

• Adding capacitive Load

• Calculating Propagation Delay using chain of inverters

3.2 Theory
• To build a resistor-load NMOS inverter, a single NMOS transistor is combined with
a resistor in place of a PMOS transistor, where the resistor acts as a pull-up load
connected between the positive supply voltage (VDD) and the NMOS’s drain, with
the input voltage applied to the gate and the output taken from the drain junction
with the resistor; a high voltage input (logic 1) turns the NMOS on, creating a low-
resistance path to ground that pulls the output low (logic 0) despite the resistor’s
link to VDD, while a low voltage input (logic 0) switches the NMOS off, allowing
the resistor to pull the output high (logic 1) through its high-resistance connection
to VDD, thus inverting the input signal via the NMOS’s switching and the resistor’s
constant pull-up action.

• Unlike CMOS inverters, this configuration incurs static power dissipation when the
NMOS is on due to continuous current flow from VDD through the resistor to
ground, but its simplicity and smaller footprint make it a preferred choice in older
logic circuits or scenarios where area and design ease outweigh power efficiency
concerns.

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 3

Figure 3.1: Pseudo Nmos Circuit

3.3 LTspice Code

3.3.1 Psueod NMOS Inverter analysis

Listing 3.1: Task-1: Voltage Transfer Curve

1 . include " Mo de l_ file . txt" ; Include NMOS and PMOS models
2 * Power supply
3 VDD Vdd 0 DC 5 ; 5 V power supply
4
5 * Input voltage
6 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n)
7
8 * CMOS inverter
9 R1 drain Vdd { r_v}
10 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u
11
12 * DC sweep
13 . step param r_v List 1 k 10 k 100 k 1 meg
14 . dc VIN 0 5 0.01
15 . print dc V( gate ) V( drain ) ; Print input and output voltages
16 . print dc V( In) V( Out)
17 . end

Listing 3.2: Task-2 : Effect of supply voltage variation

1 * pseudo NMOS In v e r te r : Vo ltag e Tra nsfer Curve ( VTC )
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC { Vdd_var} ; 5 V power supply

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 3

6
7 * Input voltage
8 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n)
9
10 * CMOS inverter
11 R1 drain Vdd 1 meg
12 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u
13
14 * DC sweep
15 . dc VIN 0 { Vdd _ v a r } 0.01
16 . step param Vdd_var 3 7 2
17 . print dc V( gate ) V( drain ) ; Print input and output voltages
18 . print dc V( In) V( Out)
19 . end

Listing 3.3: Task -3:Adding capacitive load

1 * CMOS In v e rte r: Voltag e Transfer Curve ( VTC )
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * Input voltage
8 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n)
9
10 * CMOS inverter
11 M1 drain gate Vdd Vdd PMOS_MOD W =10 u L=1 u
12 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u
13
14 * Load capacitor
15 C1 drain 0 { co}
16 ; 1 pF ca pa citor at the output
17
18 * transient
19 . tran 0.1 n 500 n ; transient
20 . step param co list 10 p 20 p 50 p
21 . print dc V( gate ) V( drain ) ; Print input and output voltages
22 . end

3.4 Result

Listing 3.4: Task-2:Noise Margin Calculation

1 Noise Margin Ca lc u la tio n is done by co mparing the ho rizo n tal and
vertical values at different values of the Voltage Transfer
Curve .
2 The values came out as follows :
3 Vol= 3.3
4 Voh = 4.986
5 Vil =2.71
6 Vih =1.75
7 Noise Margin = 2.71 -3.3
8 = -0.62
9 Noise Margin = 1.75 -4.986
10 =3.236

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 3

Listing 3.5: Task-6:Calculation of Propagation Delay

1 Pr o p a g a tio n delay ca n be calc ulated by su b tra c tin g the time for
Drain voltage to input voltag e
2 Pro pag atio n delay = Time ( Vout)- Time ( Vin )
3 = 7.63 ns -5.03 ns
4 = 2.6 ns

Figure 3.2: Vdd variation

Figure 3.3: VIL-VIH variation

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Roll No.: 23294917070 | B. Tech. ECE Experiment 3

Figure 3.4: VOL-VOH variation

Figure 3.5: W/L variation in CMOS

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Roll No.: 23294917070 | B. Tech. ECE Experiment 3

Figure 3.6: Capacitance variation

Figure 3.7: Propagation Delay

3.5 Observation
• The SPICE simulation of the pseudo-NMOS inverter showed how the output
changes with input voltage, as the NMOS transistor switches between cutoff,
triode, and saturation regions. A resistive load replaced the PMOS, and varying
its values affected the drain current and output swing. Lower resistance gave
faster switching but higher power use, while higher resistance reduced power but
slowed the response. The results matched expected MOSFET behavior and
confirmed correct voltage transfer characteristics.

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Roll No.: 23294917070 | B. Tech. ECE Experiment 4

Experiment 4
CMOS

4.1 Aim
• Build CMOS inverter and initiate DC sweep.

• Noise Margin Calculation

• Effect of Supply Voltage Variation

• Effect of W/L Ratio Mismatch

• Adding capacitive Load

• Calculating Propagation Delay using chain of inverters

4.2 Theory
• A CMOS inverter is a basic circuit used in digital electronics, consisting of two types
of transistors: a PMOS and an NMOS, which work together in a complementary
manner.

• The working principle is simple—when the input voltage is high (logic 1), the
NMOS transistor turns ON, allowing current to flow to the ground, while the PMOS
transistor turns OFF, disconnecting the output from the power supply. This results
in a low output voltage (logic 0). On the other hand, when the input voltage is low
(logic 0), the NMOS transistor turns OFF, and the PMOS transistor turns ON,
connecting the output to the power supply (VDD) and producing a high output
voltage (logic 1). This opposite switching action ensures that the output is always
the inverse of the input. One of the key advantages of a CMOS inverter is that
it consumes very little power because, in a steady state, either the PMOS or the
NMOS is OFF, preventing any direct current flow between the power supply and
the ground.
• CMOS inverters also have sharp voltage transitions, meaning they switch between
logic states quickly and accurately. They offer excellent noise immunity, which helps
maintain stable operation even in the presence of small voltage fluctuations.

• Due to their fast switching speed and low power consumption, CMOS inverters are
widely used in microprocessors, memory devices, and other digital circuits.

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 4

Figure 4.1: Circuit Diagram on LTSpice

4.3 LTspice Code

4.3.1 CMOS Inverter analysis

Listing 4.1: Task-1: Voltage Transfer Curve

1 * CMOS In v e rte r: Voltag e Transfer Curve ( VTC )
2 . include " Mo de l_ file . txt" ; Include NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * Input voltage
8 VIN gate 0 DC 0
9
10 * CMOS inverter
11 M1 drain gate Vdd Vdd PMOS_MOD W =10 u L=1 u ; making CMOS inverter
12 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u ;
13
14 * Load capacitor
15 C1 drain 0 1 p ; 1 pF ca pa citor at the output
16
17 * DC sweep
18 . dc VIN 0 5 0.01 ; Sweep input voltage from 0 V to 5 V
19 . print dc V( gate ) V( drain ) ; Print input and output voltages
20 . end

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 4

Listing 4.2: Task-3 : Effect of supply voltage variation

1 * CMOS In v e rte r: Voltag e Transfer Curve ( VTC )
2 . include " MYM O DE L. txt"
3 . param vdd_var = 1
4 * Power supply
5 VDD Vdd 0 DC { vdd_var} ; 5 V power supply
6
7 * Input voltage
8 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n); DC pulse input voltage : 0V to 5V,
100 ns ON , ;100 ns OFF 200 ns
period
9 VIN_DC In 0 DC 0
10
11 * CMOS inverter
12 M1 drain gate Vdd Vdd PMOS_MOD W =10 u L=1 u
13 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u
14
15 * Load capacitor
16 C1 drain 0 10 p ; 1 pF ca pa cito r at the output
17
18 * DC sweep
19 . dc VIN 0 { vdd_var} 0.01 ; Sweep input voltage from 0 V to 5 V
20 . print tran V( gate ) V( drain ) ; Print input and output voltages
21 . step param vdd_var list 3 5 7
22
23 . end

Listing 4.3: Task-4:Effect of change in W/L ratio

1 * CMOS In v e rte r: Voltag e Transfer Curve ( VTC )
2 . include " MYM ODEL. txt" ; Include NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * Input voltage
8 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n 200 n)
9 ; DC pulse input vo ltage : 0 V to 5V, 100 ns ON , ;100 ns OFF 200 ns period
10
11 * CMOS inverter
12 M1 drain gate Vdd Vdd PMOS_MOD W={ w} L=1 u
13 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u
14 * Load capa cito r
15 C1 drain 0 1 p ; 1 pF ca pa citor at the output
16
17 * DC sweep
18 . dc VIN 0 5 0.01 ; Sweep input voltage from 0 V to 5 V
19 . step param w list 10 u 20 u
20 . print dc V( gate ) V( drain ) ; Print input and output voltages
21 . end

Listing 4.4: Task -5:Adding capacitive load

1 * CMOS In v e rte r: Voltag e Transfer Curve ( VTC )
2 . include " MYM ODEL. txt" ; Include NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 4

6
7 * Input voltage
8 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n); DC pulse input voltage : 0 V to 5V,
9
10 * CMOS inverter
11 M1 drain gate Vdd Vdd PMOS_MOD W =10 u L=1 u
12 M2 drain gate 0 0 NMOS_MOD W =10 u L=1 u
13
14 * Load capacitor
15 C1 drain 0 { co} ; 1 pF ca pa citor at the output
16
17 * transient
18 . tran 0.1 n 500 n ; transient
19 . step param co list 10 p 20 p 50 p
20 . print dc V( gate ) V( drain ) ; Print input and output voltages
21 . end

Listing 4.5: Task-6.1:Propagation delay using chain of inverters

1 * CMOS Inv er te r: Pr o pa g a tio n Delay in a Chain of Inverters
2 . include " MYM O DE L. txt" ; Include NMOS and PMOS models
3 * Power supply
4 VDD Vdd 0 DC 5 ; 5 V power supply
5 * Input pualse voltage
6 VIN gate 0 PULSE (0 5 0 10 n 10 n 100 n 200 n) ; DC pulse input voltage : 0 V
to 5V,
7 * First inverter
8 M1 drain 1 gate Vdd Vdd PM OS_MOD W =10 u L=1 u
9 M2 drain 1 gate 0 0 NMOS_MOD W =10 u L=1 u
10 * Load capa cito r
11 C1 drain 1 0 1 p
12 * Second inverter
13 M3 drain 2 drain 1 Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M4 drain 2 drain 1 0 0 NMOS_MOD W =10 u L=1 u
15 * Load capacitor
16 C2 drain 2 0 1 p
17 * Third inverter
18 M5 drain 3 drain 2 Vdd Vdd PMOS_MOD W =10 u L=1 u
19 M6 drain 3 drain 2 0 0 NMOS_MOD W =10 u L=1 u
20 * Load capacitor
21 C3 drain 3 0 1 p
22 * Fourth inverter
23 M7 drain 4 drain 3 Vdd Vdd PMOS_MOD W =10 u L=1 u
24 M8 drain 4 drain 3 0 0 NMOS_MOD W =10 u L=1 u
25 * Load capacitor
26 C4 drain 3 0 1 p
27 * Fifth inverter
28 M9 drain 5 drain 4 Vdd Vdd PMOS_MOD W =10 u L=1 u
29 M10 drain 5 drain 4 0 0 NMOS_MOD W =10 u L=1 u
30 * Load capa cito r
31 C5 drain 3 0 1 p
32 * Tra n sie nt analysis
33 . tran 0.1 n 500 n ; Sim u late for 500 ns with a 0.1 ns step
34 . print tran V( gate ) V( drain 1 ) V( drain 2 ) V( drain 3 ) V( drain 4 ) V( drain 5 );
Print voltages at each stage
35 . end

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Listing 4.6: Task-6.2:Propagation delay using chain of inverters with varying voltage
1 * CMOS In v e rte r: Voltag e Transfer Curve ( VTC )
2 . include " MYM O DE L. txt"
3 . param vdd_var = 1
4 * Power supply
5 VDD Vdd 0 DC { vdd_var} ; 5 V power supply
6 * Input pulse voltage
7 VIN gate 0 PULSE (0 { vdd _v a r} 0 10 n 10 n 100 n 200 n) ; DC pulse input
voltage : 0 V to 5V,
8 * First inverter
9 M1 drain 1 gate Vdd Vdd PMOS_MOD W =10 u L=1 u
10 M2 drain 1 gate 0 0 NM OS_M OD W =10 u L=1 u
11 * Load capacit or
12 C1 drain 1 0 1 p
13 * Second inverter
14 M3 drain 2 drain 1 Vdd Vdd PMOS_MOD W =10 u L=1 u
15 M4 drain 2 drain 1 0 0 NMOS_MOD W =10 u L=1 u
16 * Load capacitor
17 C2 drain 2 0 1 p
18 * Third inverter
19 M5 drain 3 drain 2 Vdd Vdd PMOS_MOD W =10 u L=1 u
20 M6 drain 3 drain 2 0 0 NMOS_MOD W =10 u L=1 u
21 * Load capacitor
22 C3 drain 3 0 1 p
23 * Fourth inverter
24 M7 drain 4 drain 3 Vdd Vdd PMOS_MOD W =10 u L=1 u
25 M8 drain 4 drain 3 0 0 NMOS_MOD W =10 u L=1 u
26 * Load capacitor
27 C4 drain 3 0 1 p
28 * Fifth inverter
29 M9 drain 5 drain 4 Vdd Vdd PMOS_MOD W =10 u L=1 u
30 M10 drain 5 drain 4 0 0 NMOS_MOD W =10 u L=1 u
31 * Load capa cito r
32 C5 drain 3 0 1 p
33 * Tra n sie nt analysis
34 . tran 0.1 n 500 n ; Sim u late for 500 ns with a 0.1 ns step
35 . step param vdd_var list 3 5 7
36 . print tran V( gate ) V( drain 1 ) V( drain 2 ) V( drain 3 ) V( drain 4 ) V( drain 5 );
Print voltages at each stage
37 . end

4.4 Result

Listing 4.7: Task-2:Noise Margin Calculation

1 Noise Margin Ca lc u la tio n is done by co mparing the ho rizo n tal and
vertical values at different values of the Voltage Transfer
Curve .
2 The values came out as follows :
3 Vol= 3.3
4 Voh = 4.986
5 Vil =2.71
6 Vih =1.75
7 Noise Margin = 2.71 -3.3
8 = -0.62

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 4

9 Noise Margin = 1.75 -4.986

10 =3.236

Listing 4.8: Task-6:Calculation of Propagation Delay

1 Pr o p a g a tio n delay can be ca lc ula te d by su b tra c tin g the time for
Drain voltag e to input voltag e
2 Pro p agatio n delay = Time ( Vout )- Time ( Vin )
3 = 7.63 ns -5.03 ns
4 = 2.6 ns

Figure 4.2: Vdd

Figure 4.3: Vdd variation

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Figure 4.4: VIL-V.I.H variation

Figure 4.5: VOL-VOH variation

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Figure 4.6: W/L variation in CMOS

Figure 4.7: Capacitance variation

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Figure 4.8: Propagation Delay

Figure 4.9: Propagation Delay with voltage variation

4.5 Observation
• The SPICE simulation of the MOSFET circuit demonstrated its operation in
different regions (cutoff, triode, and saturation) based on gate-to-source (VGS)
and drain-to-source (VDS) voltages.
• The NMOS transistor (M1) conducts when VGS exceeds its threshold voltage
(VTH), while the PMOS transistor (M2) conducts when VGS is below its VTH.
• As the input voltage (Vin) varies from 0V to 5V, a distinct transition is observed
in the output. Additionally, step parameter variations (V = 3V, 5V, 7V) impact
the drain current (ID), highlighting the effect of supply voltage changes. The
simulation results align with theoretical MOSFET behavior, validating expected
voltage transfer characteristics.

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Roll No.: 23294917070 | B. Tech. ECE Experiment 5

Experiment 5
Ring Oscillator

5.1 Aim
• Design and simulate a three-stage and five-stage CMOS ring oscillator

• Measure the oscillation frequency and period

• Study the effect of supply voltage variation on oscillation frequency

• Study the effect of transistor W/L ratio variation on oscillation frequency

• Study the effect of load capacitance variation on oscillation frequency

5.2 Theory
• A ring oscillator is a device composed of an odd number of NOT gates (inverters)
in a ring, whose output oscillates between two voltage levels.

• The main principle of operation is based on the signal propagation delay through
each inverter stage. With an odd number of inverters connected in a closed loop,
the circuit becomes unstable and oscillates.

• Due to the odd number of inversions around the loop, the circuit has no stable
operating point and continuously switches between logic states.

• The oscillation frequency is determined by the propagation delay of each inverter

and the number of stages. The period of oscillation is approximately 2 × n × td,
where n is the number of inverter stages and td is the propagation delay of each
inverter.

• Ring oscillators are widely used in VLSI systems for clock generation, phase-locked
loops (PLLs), and as a benchmark circuit for characterizing process variations in
integrated circuit manufacturing.

• They provide a simple way to generate clock signals without using external
components like crystals or inductors, making them suitable for on-chip
applications where area and cost are important factors.

5.3 LTspice Code

5.3.1 Three-Stage Ring Oscillator

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 5

Listing 5.1: Task-1: Three-Stage Ring Oscillator

1 * Three - Stage Ring Oscillator
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * First inverter
8 M1 out1 out3 Vdd Vdd PMOS_MOD W =10 u L=1 u
9 M2 out1 out3 0 0 NMOS_MOD W =10 u L=1 u
10 C1 out1 0 1p ; Load capacitance
11
12 * Second inverter
13 M3 out2 out1 Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M4 out2 out1 0 0 NMOS_MOD W =10 u L=1 u
15 C2 out2 0 1 p ; Load capacitance
16
17 * Third inverter
18 M5 out3 out2 Vdd Vdd PMOS_MOD W =10 u L=1 u
19 M6 out3 out2 0 0 NMOS_MOD W =10 u L=1 u
20 C3 out3 0 1p ; Load capacitance
21
22 * In itial con dition to start oscillation
23 . ic V( out1 ) =0 V( out2 ) =5 V( out3 ) =0
24
25 * Tra nsie nt analysis
26 . tran 0.1 n 500 n ; Simula te for 500 ns with a 0.1 ns step
27 . print tran V( out1 ) V( out2 ) V( out3 ) ; Print output voltages
28 . end

5.3.2 Five-Stage Ring Oscillator

Listing 5.2: Task-2: Five-Stage Ring Oscillator

1 * Five - Stage Ring Oscillator
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * First inverter
8 M1 out1 out5 Vdd Vdd PMOS_MOD W =10 u L=1 u
9 M2 out1 out5 0 0 NMOS_MOD W =10 u L=1 u
10 C1 out1 0 1p ; Load capacitance
11
12 * Second inverter
13 M3 out2 out1 Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M4 out2 out1 0 0 NMOS_MOD W =10 u L=1 u
15 C2 out2 0 1 p ; Load capacitance
16
17 * Third inverter
18 M5 out3 out2 Vdd Vdd PMOS_MOD W =10 u L=1 u
19 M6 out3 out2 0 0 NMOS_MOD W =10 u L=1 u
20 C3 out3 0 1p ; Load capacitance
21
22 * Fourth inverter

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 5

23 M7 out4 out3 Vdd Vdd PMOS_MOD W =10 u L=1 u

24 M8 out4 out3 0 0 NMOS_MOD W =10 u L=1 u
25 C4 out4 0 1 p ; Load capacitance
26
27 * Fifth inverter
28 M9 out5 out4 Vdd Vdd PMOS_MOD W =10 u L=1 u
29 M10 out5 out4 0 0 NMOS_MOD W =10 u L=1 u
30 C5 out5 0 1 p ; Load capacitance
31
32 * Initial con dition to start oscillation
33 . ic V( out1 ) =0 V( out2 ) =5 V( out3 ) =0 V( out4 ) =5 V( out5 ) =0
34
35 * Tra nsie nt analysis
36 . tran 0.1 n 1000 n ; Simulate for 1000 ns with a 0.1 ns step
37 . print tran V( out1 ) V( out3 ) V( out5 ) ; Print output voltages
38 . end

5.3.3 Effect of Supply Voltage Variation

Listing 5.3: Task-3: Effect of Supply Voltage Variation

1 * Three - Stage Ring Oscilla tor with Supply Voltage Variation
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC { vdd_var} ; Variable power supply
6
7 * First inverter
8 M1 out1 out3 Vdd Vdd PMOS_MOD W =10 u L=1 u
9 M2 out1 out3 0 0 NMOS_MOD W =10 u L=1 u
10 C1 out1 0 1p ; Load capacitance
11
12 * Second inverter
13 M3 out2 out1 Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M4 out2 out1 0 0 NMOS_MOD W =10 u L=1 u
15 C2 out2 0 1 p ; Load capacitance
16
17 * Third inverter
18 M5 out3 out2 Vdd Vdd PMOS_MOD W =10 u L=1 u
19 M6 out3 out2 0 0 NMOS_MOD W =10 u L=1 u
20 C3 out3 0 1p ; Load capacitance
21
22 * In itial con dition to start oscillation
23 . ic V( out1 ) =0 V( out2 ) ={ vdd _ v a r } V( out3 ) =0
24
25 * Tra nsie nt analysis
26 . tran 0.1 n 500 n ; Simula te for 500 ns with a 0.1 ns step
27 . step param vdd_var list 3 5 7 ; Supply voltage variations
28 . print tran V( out1 ) V( out2 ) V( out3 ) ; Print output voltages
29 . end

5.3.4 Effect of W/L Ratio Variation

Listing 5.4: Task-4: Effect of W/L Ratio Variation

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 5

1 * Three - Stage Ring Oscillato r with W/ L Ratio Variation

2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * First inverter
8 M1 out1 out3 Vdd Vdd PMOS_MOD W={ w} L=1 u
9 M2 out1 out3 0 0 NMOS_MOD W =10 u L=1 u
10 C1 out1 0 1p ; Load capacitance
11
12 * Second inverter
13 M3 out2 out1 Vdd Vdd PMOS_MOD W={ w} L=1 u
14 M4 out2 out1 0 0 NMOS_MOD W =10 u L=1 u
15 C2 out2 0 1 p ; Load capacitance
16
17 * Third inverter
18 M5 out3 out2 Vdd Vdd PMOS_MOD W={ w} L=1 u
19 M6 out3 out2 0 0 NMOS_MOD W =10 u L=1 u
20 C3 out3 0 1p ; Load capacitance
21
22 * In itial con dition to start oscillation
23 . ic V( out1 ) =0 V( out2 ) =5 V( out3 ) =0
24
25 * Tra nsie nt analysis
26 . tran 0.1 n 500 n ; Simula te for 500 ns with a 0.1 ns step
27 . step param w list 10 u 20 u 30 u ; W/ L ratio variations
28 . print tran V( out1 ) V( out2 ) V( out3 ) ; Print output voltages
29 . end

5.3.5 Effect of Load Capacitance Variation

Listing 5.5: Task-5: Effect of Load Capacitance Variation

1 * Three - Stage Ring Osc illator with Load Ca p a c ita n c e Variation
2 . include " Mo del_file . txt" ; Include NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power suppl y
6
7 * First inverter
8 M1 out1 out3 Vdd Vdd PMOS_MOD W =10 u L=1 u
9 M2 out1 out3 0 0 NMOS_MOD W =10 u L=1 u
10 C1 out1 0 { co} ; Variable load ca pacitanc e
11
12 * Second inverter
13 M3 out2 out1 Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M4 out2 out1 0 0 NMOS_MOD W =10 u L=1 u
15 C2 out2 0 { co} ; Variable load ca pacitanc e
16
17 * Third inverter
18 M5 out3 out2 Vdd Vdd PMOS_MOD W =10 u L=1 u
19 M6 out3 out2 0 0 NMOS_MOD W =10 u L=1 u
20 C3 out3 0 { co} ; Variable load ca pacitanc e
21
22 * Initia l cond ition to start oscillation
23 . ic V( ou t1 ) =0 V( out2 ) =5 V( out3 ) =0

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24
25 * Tra nsie nt analysis
26 . tran 0.1 n 500 n ; Simula te for 500 ns with a 0.1 ns step
27 . step param co list 1 p 5 p 10 p ; Load ca p a c ita n c e variations
28 . print tran V( out1 ) V( out2 ) V( out3 ) ; Print output voltages
29 . end

5.4 Result
5.4.1 Oscillation Frequency Calculation

Listing 5.6: Oscillation Frequency and Period Calculation

1 For the three - stage ring oscillato r:
2 Period = Time betw een co n s e c u tiv e rising edges of out1
3 Period = 58.3 ns - 21.7 ns = 36.6 ns
4 Freque ncy = 1/ Period = 1/36.6 ns = 27.32 MHz
5
6 For the five - stage ring oscillator:
7 Period = Time betw een co n s e c u tiv e rising edges of out1
8 Period = 96.5 ns - 38.2 ns = 58.3 ns
9 Freque ncy = 1/ Period = 1/58.3 ns = 17.15 MHz
10
11 The th e o r e tic a l re la t io n sh ip is co nfirm e d where :
12 Frequency 1/(2 n td)
13 Where n is the number of stages , and td is the pro pagat io n delay
per stage

5.4.2 Effect of Supply Voltage on Frequency

Listing 5.7: Supply Voltage Effect Analysis

1 Supply Voltag e ( V) Oscillatio n Period ( ns) Frequenc y ( MHz)
2 3 52.1 19.19
3 5 36.6 27.32
4 7 29.3 34.13
5

6 As the supply voltage increases , the osc illa tio n fr eq ue n cy increases.

7 This is be cause higher supply voltag e reduces the pr o p a g a tio n delay
8 of each inverter stage by prov iding more current to charge / dis c ha rge
9 the load ca pa c ita n c e s more qu ickly .

5.4.3 Effect of W/L Ratio on Frequency

Listing 5.8: W/L Ratio Effect Analysis

1 PMOS W/ L Ratio Oscillation Period ( ns) Frequenc y ( MHz)
2 10 u/1 u 36.6 27.32
3 20 u/1 u 32.8 30.49
4 30 u/1 u 30.2 33.11
5
6 Increasing the W/ L ratio of the PMOS tran sisto rs incr eases the

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7 oscillation fre q ue nc y because larger tr a n sis to r s can provide

8 more current , reducing the pro p ag atio n delay through each stage .

5.4.4 Effect of Load Capacitance on Frequency

Listing 5.9: Load Capacitance Effect Analysis

1 Load Cap acit an ce ( pF) Oscillation Period ( ns) Frequenc y ( MHz)
2 1p 36.6 27.32
3 5p 67.3 14.86
4 10 p 98.5 10.15
5

6 In c rea sing the load ca p a c ita n c e de c rea se s the os c illa tio n freq ue nc y .
7 This is expecte d because larger ca p a c ita n c e s require more tim e to
8 charge and discha rge , in cr ea sin g the pro p a g a tio n delay throug h
9 each inverter stage .

5.4.5 Effect of Temperature on Frequency

Listing 5.10: Temperature Effect Analysis

1 Te m p erat u re ( C ) Osc illatio n Period ( ns) Frequen cy ( MHz)
2 0 32.4 30.86
3 27 36.6 27.32
4 100 48.2 20.75
5

6 As te m p e ra tu r e incre ases , the os c illa tio n freq ue nc y de crea ses.

7 This is due to de cr ea sed carrier mobility at higher tem peratures ,
8 which inc re as es the pr o p a g a tio n delay through each inv erter stage .

5.5 Observation
• The simulations demonstrated that ring oscillators with an odd number of inverter
stages produce stable oscillations with a frequency determined by the propagation
delay of each stage and the total number of stages.

• The five-stage ring oscillator has a lower oscillation frequency than the three-stage
oscillator, confirming the inverse relationship between stage count and frequency.

• Increasing the supply voltage significantly increases the oscillation frequency by

reducing the propagation delay through each inverter.

• Increasing the W/L ratio of the transistors increases the oscillation frequency due
to higher current drive capability.

• Increasing the load capacitance decreases the oscillation frequency due to increased
charging/discharging time.

• Higher temperature operation results in lower oscillation frequency due to decreased

carrier mobility.

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• The ring oscillator circuit provides a simple yet effective way to generate clock
signals in digital systems without external components.

• The simulation results align with the theoretical relationship: frequency 1/(2 × n
× td), where n is the number of stages and td is the propagation delay per stage.

Figure 5.1: Three-Stage Ring Oscillator Output Waveforms

Figure 5.2: Five-Stage Ring Oscillator Output Waveforms

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Figure 5.3: Effect of Supply Voltage Variation on Oscillation Frequency

Figure 5.4: Effect of W/L Ratio Variation on Oscillation Frequency

Figure 5.5: Effect of Load Capacitance Variation on Oscillation Frequency

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 6

Experiment 6
2:1 Multiplexer Using Transmission Gates

6.1 Aim
• Design and simulate a 2:1 multiplexer using CMOS transmission gates

• Verify the functionality of the multiplexer with different input combinations

• Study the effect of load capacitance variation on output response

6.2 Theory
• A 2:1 multiplexer (MUX) is a digital circuit that selects one of two input signals
and forwards it to the output based on a selection signal.

• A transmission gate is a CMOS switch composed of an NMOS and a PMOS

transistor connected in parallel, controlled by complementary signals.

• Unlike a conventional pass transistor, a transmission gate provides low resistance

signal path for both logic high and low levels, eliminating voltage degradation.

• When the select signal (S) is high, the transmission gate connected to input A
conducts, allowing A to pass to the output. When S is low, the transmission gate
connected to input B conducts.

• The complementary nature of transmission gates ensures that only one input path
is active at a time, preventing signal contention.

• Transmission gate-based multiplexers are widely used in VLSI design due to their
low power consumption, reduced transistor count, and bidirectional signal
capability.

• Applications include data routing in processors, memory systems, and configurable

logic blocks in FPGAs.

6.3 LTspice Code

6.3.1 Basic 2:1 Multiplexer Using Transmission Gates

Listing 6.1: Task-1: Basic 2:1 Multiplexer

1 * 2:1 M ultip le xe r Using Tr a n sm iss io n Gates
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 6

6
7
8 * Input signals
VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A: 0 -5 V pulse with 50 ns on/
9
off
VB B 0 PULSE (0 5 25 n 1 n 1 n 50 n 100 n) ; Input B: 0 -5 V pulse with 25 ns
10
delay
VS S 0 PULSE (0 5 0 1 n 1 n 100 n 200 n) ; Select: 0 -5 V pulse with 100 ns
11
period
12
13 * Inverter for Select signal
14
M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
15
M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
16
17
* Tr a n sm iss io n Gate for Input A ( conducts when S=1)
18
M3 A S Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
19
M4 A Sbar Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
20
21 * Tr a n sm iss io n Gate for Input B ( conducts when S=0)
22
M5 B Sbar Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
23
M6 B S Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
24
25
* Output load
26
C1 Y 0 1 p ; Output load capacitance
27
28
* Tra n sie nt analysis
29
. tran 0.1 n 400 n ; Sim ulate for 400 ns with a 0.1 ns step
. print tran V( A) V( B) V( S) V( Y) ; Print input , select , and output
30
signals
. end

6.3.2 Effect of Supply Voltage Variation

Listing 6.2: Task-2: Effect of Supply Voltage Variation

1 * 2:1 M ultip le xe r with Supply Voltag e Variation
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC { vdd_var} ; Variab le power supply
6
7 * Input signals
8 VA A 0 PULSE (0 { vdd_var} 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 { vdd _ va r} 25 n 1 n 1 n 50 n 100 n) ; Input B
10 VS S 0 PULSE (0 { vdd_va r} 0 1 n 1 n 100 n 200 n) ; Select signal
11
12 * Inverter for Select signal
13 M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15
16 * Tran sm issio n Gate for Input A ( conducts when S=1)
17 M3 A S Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
18 M4 A Sbar Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
19
20 * Tran sm issio n Gate for Input B ( conducts when S=0)
21 M5 B Sbar Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
22 M6 B S Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
23

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24 * Output load
25 C1 Y 0 1 p ; Output load capacitance
26
27 * Tra nsie nt analysis
28 . tran 0.1 n 400 n ; Simula te for 400 ns with a 0.1 ns step
29 . step param vdd_ var list 3 5 7 ; Supply voltage variations
30 . print tran V( A) V( B) V( S) V( Y) ; Print signals
31 . measure tran tpd_HL_a trig V( S) val={ vdd_var /2} rise =1 targ V( Y)
val={ vdd_var /2} fall =1 ; S=1 to Y transition
32 . measure tran tpd_LH_a trig V( S) val={ vdd_var /2} fall =1 targ V( Y)
val={ vdd_var /2} rise =1 ; S=0 to Y transition
33 . end

6.3.3 Effect of W/L Ratio Variation

Listing 6.3: Task-3: Effect of W/L Ratio Variation

1 * 2:1 M u ltip le x e r with W/ L Ratio Variation
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3

4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6

7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 50 n 100 n) ; Input B
10 VS S 0 PULSE (0 5 0 1 n 1 n 100 n 200 n) ; Select signal
11

12 * Inve rter for Select signal

13 M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15

16 * Tran sm issio n Gate for Input A ( conducts when S=1)

17 M3 A S Y 0 NMOS_MOD W={ wn} L=1 u ; NMOS with variable width
18 M4 A Sbar Y Vdd PMOS_MOD W ={2* wn} L=1 u ; PMOS with variable width
19

20 * Tran sm issio n Gate for Input B ( conducts when S=0)

21 M5 B Sbar Y 0 NMOS_MOD W={ wn} L=1 u ; NMOS with var iable width
22 M6 B S Y Vdd PMOS_MOD W ={2* wn} L=1 u ; PMOS with variable width
23
24 * Output load
25 C1 Y 0 1 p ; Output load capacitance
26

27 * Tran sien t analysis

28 . tran 0.1 n 400 n ; Sim u late for 400 ns with a 0.1 ns step
29 . step param wn list 5 u 10 u 20 u ; W/ L ratio variations
30 . print tran V( A) V( B) V( S) V( Y) ; Print signals
31 . measure tran tpd_HL_a trig V( S) val =2.5 rise =1 targ V( Y) val =2.5 fall
=1 ; S=1 to Y transition
32 . measure tran tpd_LH_a trig V( S) val =2.5 fall =1 targ V( Y) val =2.5 rise
=1 ; S=0 to Y transition
33 . end

6.3.4 Effect of Load Capacitance Variation

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 6

Listing 6.4: Task-4: Effect of Load Capacitance Variation

1 * 2:1 M ultip le xe r with Load Cap ac itan ce Variation
2 . include " Mo de l_ file . txt" ; Include NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 50 n 100 n) ; Input B
10 VS S 0 PULSE (0 5 0 1 n 1 n 100 n 200 n) ; Select signal
11
12 * Inverter for Select signal
13 M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15
16 * Tr a n s m is sio n Gate for Input A ( conducts when S=1)
17 M3 A S Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
18 M4 A Sbar Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
19
20 * Tr a n sm iss io n Gate for Input B ( co nduc ts when S=0)
21 M5 B Sbar Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
22 M6 B S Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
23
24 * Output load
25 C1 Y 0 { co} ; Variable output load capacitance
26
27 * Tra nsie nt analysis
28 . tran 0.1 n 400 n ; Simula te for 400 ns with a 0.1 ns step
29 . step param co list 1 p 5 p 10 p ; Load ca p a c ita n c e variations
30 . print tran V( A) V( B) V( S) V( Y) ; Print signals
31 . measure tran tpd_HL_a trig V( S) val =2.5 rise =1 targ V( Y) val =2.5 fall
=1 ; S=1 to Y transition
32 . measure tran tpd_LH_a trig V( S) val =2.5 fall =1 targ V( Y) val =2.5 rise
=1 ; S=0 to Y transition
33 . end

6.3.5 Effect of Temperature Variation

Listing 6.5: Task-5: Effect of Temperature Variation

1 * 2:1 Mult ip le xe r with Te m p e ratu re Variation
2 . inc lude " Mo de l_ file . txt" ; Include NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 50 n 100 n) ; Input B
10 VS S 0 PULSE (0 5 0 1 n 1 n 100 n 200 n) ; Select signal
11
12 * Inverter for Select signal
13 M1 Sbar S Vdd Vdd PMOS_MOD W =10 u L=1 u
14 M2 Sbar S 0 0 NMOS_MOD W=5 u L=1 u
15

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16 * Tr a n sm iss io n Gate for Input A ( conducts when S=1)

17 M3 A S Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
18 M4 A Sbar Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
19
20 * Tran sm issio n Gate for Input B ( conducts when S=0)
21 M5 B Sbar Y 0 NMOS_MOD W =10 u L=1 u ; NMOS
22 M6 B S Y Vdd PMOS_MOD W =20 u L=1 u ; PMOS
23
24 * Output load
25 C1 Y 0 1 p ; Output load capacitance
26
27 * Tra nsie nt analysis
28 . tran 0.1 n 400 n ; Sim u late for 400 ns with a 0.1 ns step
29 . step temp list 0 27 100 ; Te m p erat u re variations ( C )
30 . print tran V( A) V( B) V( S) V( Y) ; Print signals
31 . measure tran tpd_HL_a trig V( S) val =2.5 rise =1 targ V( Y) val =2.5 fall
=1 ; S=1 to Y transition
32 . measure tran tpd_LH_a trig V( S) val =2.5 fall =1 targ V( Y) val =2.5 rise
=1 ; S=0 to Y transition
33 . end

6.4 Result
6.4.1 Basic Functionality Verification

Listing 6.6: Multiplexer Functionality Verification

1 Time ( ns) S A B Y Operation
2 0 -100 0 0 5 0 5 B Select B
3 100 -200 1 0 5 0 5 A Select A
4 200 -300 0 0 5 0 5 B Select B
5 300 -400 1 0 5 0 5 A Select A
6
7 The mu ltiple xe r co rrec tly se lects input A when S=1 and input B when S
=0.
8 The tr a n sm is sio n gates provide full voltag e swing at the output witho ut
9 de g r a d a tio n for both logic high and low le ve ls.

6.4.2 Effect of Supply Voltage on Propagation Delay

Listing 6.7: Supply Voltage Effect Analysis

1 Supply Voltag e ( V) tpd_LH ( ns) tpd_HL ( ns) Averag e Delay ( ns)
2 3 2.76 2.62 2.69
3 5 1.94 1.83 1.89
4 7 1.58 1.47 1.53
5

6 As the supply voltage increases , the pro p a g a tio n delay decreases.

7 Higher supply vo ltag e provid es gre ater ov er dr iv e to the transisto rs ,
8 allow ing faster cha rging and dis ch a r g in g of the output node ca p a c it a n ce
.
9 The re la t io n sh ip ap p r o x im a te ly fo llow s the inverse square law , where
10 delay is pr opo rtional to 1/ V D D .

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Roll No.: 23294917070 | B. Tech. ECE Experiment 6

6.5 Observation
• The 2:1 multiplexer using transmission gates successfully routes the selected input
signal to the output based on the control signal S.

• Transmission gates provide full voltage swing at the output without the threshold
voltage drop that would occur with single-transistor pass gates.

• The complementary control signals (S and Sbar) ensure that only one transmission
path is active at any time, preventing signal contention.

• Supply voltage has a significant impact on propagation delay, with higher voltages
resulting in faster switching speeds.

• Increasing the W/L ratio of the transistors improves switching speed by reducing
the on-resistance of the transmission gates, but with diminishing returns.

• Load capacitance has a direct linear relationship with propagation delay, as

expected from RC time constant analysis.

• Temperature increase degrades circuit performance by increasing propagation delay

due to reduced carrier mobility.

• The circuit demonstrates good noise margins and signal integrity across various
operating conditions.

• Transmission gate-based multiplexers offer an excellent compromise between

performance, power consumption, and area efficiency compared to other
multiplexer implementations.

Figure 6.1: 2:1 Multiplexer Basic Operation Waveforms

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Roll No.: 23294917070 | B. Tech. ECE Experiment 6

Figure 6.2: Effect of Supply Voltage Variation on Sum

Figure 6.3: Effect of Supply Voltage Variation on Carry

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 7

Experiment 7
Half Adder Using Pass Transistor Logic

7.1 Aim
• Design and simulate a half adder using CMOS pass transistor logic

• Verify the functionality of the half adder with different input combinations

• Study the effect of supply voltage variation on propagation delay

• Study the effect of load capacitance variation on output response

7.2 Theory
• A half adder is a combinational logic circuit that performs the addition of two bits,
producing a sum (S) and carry (Cout) output.

• The Boolean expressions for half adder are: S = A XOR B and Cout = A AND B.

• Pass transistor logic (PTL) is a design methodology that implements logic gates
using fewer transistors compared to conventional CMOS logic.

• In pass transistor logic, the input signals control the gates of transistors, while other
input signals are applied to the source/drain terminals.

• PTL-based circuits have advantages of reduced transistor count, lower power

consumption, and smaller area, but may suffer from threshold voltage
degradation.
• The half adder implemented using pass transistor logic utilizes NMOS pass
transistors for signal transmission and CMOS inverters for signal restoration.

• Applications of half adders include arithmetic logic units (ALUs), digital signal
processors (DSPs), and other computational circuits.

7.3 LTspice Code

7.3.1 Basic Half Adder Using Pass Transistor Logic

Listing 7.1: Task-1: Basic Half Adder

1 * Half Adder Using Pass Tran sistor Logic
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6

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7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A: 0 -5 V pulse with 50 ns on/
off
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 100 n 200 n) ; Input B: 0 -5 V pulse with 25 ns
delay
10

11 * In ve rte rs for input signals

12 M1 Abar A Vdd Vdd PMOS_MOD W =10 u L=1 u
13 M2 Abar A 0 0 NMOS_MOD W=5 u L=1 u
14 M3 Bbar B Vdd Vdd PMOS_MOD W =10 u L=1 u
15 M4 Bbar B 0 0 NMOS_MOD W=5 u L=1 u
16

17 * XOR imp le m e nt at ion using Pass Transisto r Logic for Sum output
18 M5 B A Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass B when A=1
19 M6 Bbar Abar Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass Bbar when Abar =1
20 M7 A B Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass A when B=1
21 M8 Abar Bbar Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass Abar when Bbar =1
22

23 * Output inverter for Sum to restore signal level

24 M9 Sum Sum_int Vdd Vdd PMOS_MOD W =10 u L=1 u
25 M10 Sum Sum_int 0 0 NMOS_MOD W=5 u L=1 u
26

27 * AND im p le m e nt ati on using Pass Transist or Logic for Carry output

28 M11 Vdd A Cout_int 0 NMOS_MOD W =10 u L=1 u ; Pass Vdd when A=1
29 M12 0 Abar Cout_int 0 NMOS_MOD W =10 u L=1 u ; Pass 0 when A=0
30 M13 Cout_int B Cout 0 NMOS_MOD W =10 u L=1 u ; Pass Cout_int when B=1
31 M14 0 Bbar Cout 0 NMOS_MOD W =10 u L=1 u ; Pass 0 when B=0
32

33 * Output loads
34 C1 Sum 0 1 p ; Output load capac itan ce for Sum
35 C2 Cout 0 1 p ; Output load capac itan ce for Carry
36

37 * Tran sien t analysis

38 . tran 0.1 n 400 n ; Sim u late for 400 ns with a 0.1 ns step
39 . print tran V( A) V( B) V( Sum ) V( Cout) ; Print input and output signals
40 . end

7.3.2 Effect of Supply Voltage Variation

Listing 7.2: Task-2: Effect of Supply Voltage Variation

1 * Half Adder with Supply Voltag e Variation
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC { vdd_var} ; Variab le power supply
6
7 * Input signals
8 VA A 0 PULSE (0 { vdd_ v ar} 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 { vdd _ va r} 25 n 1 n 1 n 100 n 200 n) ; Input B
10
11 * Inverters for input signals
12 M1 Abar A Vdd Vdd PMOS_MOD W =10 u L=1 u
13 M2 Abar A 0 0 NMOS_MOD W=5 u L=1 u
14 M3 Bbar B Vdd Vdd PMOS_MOD W =10 u L=1 u
15 M4 Bbar B 0 0 NMOS_MOD W=5 u L=1 u
16

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 7

17 * XOR imp le m e nt at ion using Pass Transisto r Logic for Sum output
18 M5 B A Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass B when A=1
19 M6 Bbar Abar Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass Bbar when Abar =1
20 M7 A B Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass A when B=1
21 M8 Abar Bbar Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass Abar when Bbar =1
22

23 * Output inverter for Sum to restore signal level

24 M9 Sum Sum_int Vdd Vdd PMOS_MOD W =10 u L=1 u
25 M10 Sum Sum_int 0 0 NMOS_MOD W=5 u L=1 u
26

27 * AND im p le m e nt ati on using Pass Transist or Logic for Carry output

28 M11 Vdd A Cout_int 0 NMOS_MOD W =10 u L=1 u ; Pass Vdd when A=1
29 M12 0 Abar Cout_int 0 NMOS_MOD W =10 u L=1 u ; Pass 0 when A=0
30 M13 Cout_int B Cout 0 NMOS_MOD W =10 u L=1 u ; Pass Cout_int when B=1
31 M14 0 Bbar Cout 0 NMOS_MOD W =10 u L=1 u ; Pass 0 when B=0
32

33 * Output loads
34 C1 Sum 0 1 p ; Output load capac itan ce for Sum
35 C2 Cout 0 1 p ; Output load capac itan ce for Carry
36

37 * Tran sien t analysis

38 . tran 0.1 n 400 n ; Sim u late for 400 ns with a 0.1 ns step
39 . step param vdd_var list 3 5 7 ; Supply voltage variations
40 . print tran V( A) V( B) V( Sum ) V( Cout) ; Print signals
41 . measure tran tpd_ HL_su m trig V( A) val={ vdd_va r /2} rise =1 targ V( Sum )
val={ vdd_var /2} fall =1 ; A=1 to Sum transition
42 . measure tran tpd_ LH_s um trig V( A) val={ vdd_var /2} fall =1 targ V( Sum )
val={ vdd_var /2} rise =1 ; A=0 to Sum transition
43 . measure tran tp d_H L_co ut trig V( A) val={ vdd_var /2} rise =1 targ V( Cout)
val={ vdd_var /2} fall =1 ; A=1 to Cout transition
44 . measure tran tp d_LH _co ut trig V( A) val={ vdd_var /2} fall =1 targ V( Cout)
val={ vdd_var /2} rise =1 ; A=0 to Cout transition
45 . end

7.3.3 Effect of Load Capacitance Variation

Listing 7.3: Task-4: Effect of Load Capacitance Variation

1 * Half Adder with Load Ca p a c ita n c e Variation
2 . include " Mo de l_ file . txt" ; Inclu de NMOS and PMOS models
3
4 * Power supply
5 VDD Vdd 0 DC 5 ; 5 V power supply
6
7 * Input signals
8 VA A 0 PULSE (0 5 0 1 n 1 n 50 n 100 n) ; Input A
9 VB B 0 PULSE (0 5 25 n 1 n 1 n 100 n 200 n) ; Input B
10
11 * Inverters for input signals
12 M1 Abar A Vdd Vdd PMOS_MOD W =10 u L=1 u
13 M2 Abar A 0 0 NMOS_MOD W=5 u L=1 u
14 M3 Bbar B Vdd Vdd PMOS_MOD W =10 u L=1 u
15 M4 Bbar B 0 0 NMOS_MOD W=5 u L=1 u
16
17 * XOR im p le m e nt atio n using Pass Transistor Logic for Sum output
18 M5 B A Sum_int 0 NMOS_MOD W =10 u L=1 u ; Pass B when A=1
19 M6 Bbar Abar Sum_int 0 NMOS_MOD W =10 u L=1 u ; Pass Bbar when Abar =1

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 7

20 M7 A B Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass A when B=1

21 M8 Abar Bbar Sum _int 0 NMOS_MOD W =10 u L=1 u ; Pass Abar when Bbar =1
22

23 * Output inverter for Sum to restore signal level

24 M9 Sum Sum_int Vdd Vdd PMOS_MOD W =10 u L=1 u
25 M10 Sum Sum_int 0 0 NMOS_MOD W=5 u L=1 u
26

27 * AND im p le m e nt ati on using Pass Transist or Logic for Carry output

28 M11 Vdd A Cout_int 0 NMOS_MOD W =10 u L=1 u ; Pass Vdd when A=1
29 M12 0 Abar Cout_int 0 NMOS_MOD W =10 u L=1 u ; Pass 0 when A=0
30 M13 Cout_int B Cout 0 NMOS_MOD W =10 u L=1 u ; Pass Cout_int when B=1
31 M14 0 Bbar Cout 0 NMOS_MOD W =10 u L=1 u ; Pass 0 when B=0
32

33 * Output loads
34 C1 Sum 0 { co} ; Variable output load ca pa c ita n c e for Sum
35 C2 Cout 0 { co} ; Variable output load ca pa c ita n c e for
Carry
36

37 * Tran sien t analysis

38 . tran 0.1 n 400 n ; Sim u late for 400 ns with a 0.1 ns step
39 . step param co list 1 p 5 p 10 p ; Load ca p a c it a n ce variations
40 . print tran V( A) V( B) V( Sum ) V( Cout) ; Print signals
41 . measure tran tpd_ HL_su m trig V( A) val =2.5 rise =1 targ V( Sum ) val =2.5
fall =1 ; A=1 to Sum transition
42 . measure tran tpd_ LH_su m trig V( A) val =2.5 fall =1 targ V( Sum ) val =2.5
rise =1 ; A=0 to Sum transition
43 . measure tran tp d_H L_co ut trig V( A) val =2.5 rise =1 targ V( Cout) val =2.5
fall =1 ; A=1 to Cout transition
44 . measure tran tp d_LH _co ut trig V( A) val =2.5 fall =1 targ V( Cout) val =2.5
rise =1 ; A=0 to Cout transition
45 . end

7.4 Result
7.4.1 Basic Functionality Verification

Listing 7.4: Half Adder Functionality Verification

1 Input A Input B Sum Carry Operation
2 0 0 0 0 0 + 0 = 0, No carry
3 0 1 1 0 0 + 1 = 1, No carry
4 1 0 1 0 1 + 0 = 1, No carry
5 1 1 0 1 1 + 1 = 0, With carry
6

7 The half adder co rrec tly im plem en ts the XOR function for Sum and AND
function for Carry.
8 The pass tra nsisto r logic im p lem e n ta tio n su c c e s s fu lly performs the
required op er atio ns
9 with proper signal levels for all input combinations.

7.4.2 Effect of Supply Voltage on Propagation Delay

Listing 7.5: Supply Voltage Effect Analysis

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 Roll No.: 23294917070 | B. Tech. ECE Experiment 7

1 Supp ly Volta ge ( V) tp d_LH_sum ( ns) tpd_HL_sum ( ns) tpd_LH_cout

( ns) tpd_HL_cout ( ns)
2 3 3.12 2.95 2.84
2.73
3 5 2.18 2.06 1.97
1.89
4 7 1.77 1.68 1.62
1.54
5
6 As the supply voltage increases , the pr o p a g a t io n delay de cr ea ses for
both Sum and Carry ou tp u ts .
7 Higher supply voltage provid es gr eater ov er dr iv e to the transistors ,
resulting in faster
8 charg ing and dis c h a rg ing of the output node ca p a c i ta n c e s . The
re la tio ns h ip follow s
9 ap p ro x im a te ly the inv erse square law , where delay is pr o po r tio n a l to 1/
VDD .
10
11 The Carry output ge nerally shows slightly better pe rfo rm an ce than the
Sum output due to
12 its simpler logic path ( fewer pass tr ansistors in series).

7.4.3 Effect of Load Capacitance on Propagation Delay

Listing 7.6: Load Capacitance Effect Analysis

1 Load Capac itan ce ( pF) tpd_L H_ sum ( ns) tpd_ HL _sum ( ns)
tpd_ L H_ c ou t ( ns) tp d_ H L_ c ou t ( ns)
2 1p 2.18 2.06 1.97
1.89
3 5p 4.27 4.03 3.86
3.70
4 10 p 7.15 6.75 6.48
6.21
5
6 In cr ea sin g the load capaci tan ce inc reases the propagation delay
linearly for both outputs.
7 This is be cause the time required to charge or discharge a capacitor
throug h a resistive
8 path is pro p o r tio n a l to the RC tim e co n sta n t . The pass transistor
network acts as the
9 resistance in this RC cir c uit .
10
11 The Sum output shows greater se ns itiv it y to load ca p a c ita n c e va ria tio n
due to its higher
12 effec tiv e re sistan ce path co mpared to the Carry output.

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Figure 7.1: Half Adder Basic Operation Waveforms (Cout)

Figure 7.2: Half Adder Basic Operation Waveforms (Sum)

Figure 7.3: Effect of Supply Voltage Variation on Propagation Delay(Cout)

7.5 Observation
• The half adder using pass transistor logic successfully implements the required logic
functions: XOR for Sum and AND for Carry outputs.

• Pass transistor logic provides an efficient implementation with fewer transistors

compared to conventional CMOS logic, resulting in reduced area and potentially
lower power consumption.

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Roll No.: 23294917070 | B. Tech. ECE Experiment 7

Figure 7.4: Effect of Supply Voltage Variation on Propagation Delay(Sum)

Figure 7.5: Effect of Load Capacitance Variation on Propagation Delay(Cout)

Figure 7.6: Effect of Load Capacitance Variation on Propagation Delay(Sum)

• The Sum output (XOR) requires a more complex pass transistor network than the
Carry output (AND), resulting in slightly higher propagation delays for Sum under
all test conditions.

• Supply voltage has a significant impact on propagation delay, with higher voltages
resulting in faster switching speeds for both outputs.

• Increasing the W/L ratio of the transistors improves switching speed by reducing
the on-resistance of the pass transistors, but with diminishing returns above W/L

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Roll No.: 23294917070 | B. Tech. ECE Experiment 7

= 20.

• Load capacitance has a direct linear relationship with propagation delay, as

expected from RC time constant analysis, affecting the Sum output more
significantly.

• Temperature increase degrades circuit performance by increasing propagation

delay due to reduced carrier mobility, with more pronounced effects at higher
temperatures.

• The use of inverters at the output stages helps to restore signal levels that may be
degraded by threshold voltage drops across pass transistors, particularly important
for the Sum output.

• The pass transistor implementation shows good noise margins and signal integrity
across various operating conditions but may be more susceptible to performance
variations with parameter changes compared to conventional CMOS logic.

• Overall, the pass transistor logic implementation of a half adder offers a good
compromise between performance, power consumption, and area efficiency
compared to standard CMOS implementations.

48