Texas Instruments Incorporated Data Acquisition

Impact of sampling-clock spurs on

ADC performance
By Thomas Neu
Analog Field Applications Engineer
Introduction Figure 1. Phase noise of CDCE72010’s filtered
As modern, high-speed analog-to-digital and unfiltered LVDS outputs
­converters (ADCs) push the spurious-free
dynamic range (SFDR) beyond the 100-dB
–100
barrier, the demand for a high-quality sam-
pling clock has become greater than ever.
Tradition­ally, system engineers focused –110
mainly on the clock quality when they were
Unfiltered, Spur
trading off the signal-to-noise ratio (SNR) –120 at 27-MHz Offset
against the input-signal frequency in under-
Phase Noise (dBc/Hz)

sampling applications. As tougher system –130

requirements such as multicarrier GSM Unfiltered, Spur
emerge and are starting to demand dynamic at 3-MHz Offset
–140
ranges in excess of 80 dB over a wide band-
width, system designers try to elim­inate any
possible SFDR degradation, such as the spur –150
feedthrough from a distorted sampling clock.
Spurs on the sampling clock as low as –160 With Band-Pass Filter
–90 dBc can significantly impact the SFDR
of the data converter. These low-level spurs –170
can be very difficult to track down because
they can have a variety of different origins. –180
They can be generated from crosstalk with 100 1k 10 k 100 k 1M 10 M
an adjacent digital circuit that occurs due to Frequency (Hz)
layout constraints, or they can occur simply
because the clock source is not properly
­filtered. An example of improper filtering is
shown in Figure 1, which compares two
LVDS outputs of the Texas Instruments (TI) CDCE72010, components of the sampled input signal. In order to derive
one unfiltered and one with a band-pass filter. The spur that relationship, one has to start with the basic sampling
reduction of the filtered output is clearly visible. theory. Let’s consider the setup shown in Figure 2, where
This article will discuss how spurs on the sampling the input signal is
clock get translated into the output spectrum of the data x( t ) = A IN × sin(wIN t ),
converter. It will also investigate how the spur amplitude
changes with different input frequencies. More and more and the clock input with a spurious component is
system designers are moving to an undersampling archi- y( t ) = A × sin(wCLK t ) + B × sin(wS t ).
tecture, and the spur amplitude is highly dependent upon
The quality of the sampling clock can easily be evaluated
input frequency, as will be shown later. This article will
with a phase-noise analyzer. It displays the clock’s phase
also show how to estimate the SNR degradation caused by
noise versus frequency offset from the carrier, which is
the sampling-clock spurs.
very helpful when the clock jitter is calculated to determine
Sampling theory the SNR of the receiver. The phase-noise plot displays any
The spurs that result from sampling a data converter with spurious component on the clock signal, referencing its
a distorted clock are best described by the relationship of frequency offset and spur amplitude, SX, to the main signal.
their frequency and amplitude components to the same If the amplitude is normalized in dBc/Hz, care must be

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 Data Acquisition Texas Instruments Incorporated

Figure 2. Setup with input signal, clock, and clock spur

–100
Clock Input with
Spur Present
Amplitude and

Phase Noise (dBc/Hz)

A –120
Frequency Offset of Spur

Phase-Noise –140
B Measurement

Clean Input Signal –160

AIN fCLK fS
–160

Clock –180
100 1k 10 k 100 k 1 M 10 M
Input ADC Frequency (Hz)
Digital Output
fIN

FFT Processing
Spur
Amplitude
(dBc)

FFT Analysis m m

fS1 fIN fS2 fS1 fIN fS2

taken to extract it with the resolution bandwidth of the instrument in that measurement:
Amplitude (dBc) = SX (dBc/Hz) + 10log(Resolution Bandwidth)
Due to the presence of the spur, the original sampling instant, or zero crossing of the clock, has shifted slightly by ∆T.
Now the sampling instant, y(t) = 0, can be solved for:
y ( t ) = A × sin[wCLK ( t + ∆T )] + B × sin[wS ( t + ∆T )] = 0
y ( t ) = A × sin(wCLK t ) × cos(wCLK ∆T ) + A × cos(wCLK t ) × sin(wCLK ∆T ) + B × sin(wS t ) × cos(wS ∆T ) + B × cos(wS t ) × sin(wS ∆T ) = 0

Assuming that B << A and ∆T ≈ 0 results in: cos(wCLK ∆T ) ≈ 1 sin(wCLK ∆T ) ≈ wCLK ∆T

cos(wS ∆T ) ≈ 1 sin(wS ∆T ) ≈ wS ∆T
The ideal sampling instant is t = 0, hence: sin(wCLK t ) = 0 cos(wCLK t ) = 1 cos(wS t ) = 1
Substituting these results into y(t) = 0 produces:
y ( t ) = A × sin(ωCLK t ) × cos(ωCLK ∆T ) + A × cos(ωCLK t ) × sin(ωCLK ∆T ) + B × sin(ωS t ) × cos(ωS ∆T ) + B × cos(ωS t ) × sin(ωS ∆T ) = 0

0 1 1 ωCLK∆T 1 1 ωS∆T

y ( t ) = A × wCLK ∆T + B × sin(wS t ) + B × wS ∆T = 0
B × sin(wS t ) B × sin(wS t)
Then ∆T can be solved for: ∆T = − . Assuming that A >> B results in ∆T = − .
A × wCLK + B × wS A × wCLK

Next, the input signal, x(t) = AIN×sin(wINt), is sampled at the zero crossing, t + ∆T, of the non-ideal clock:
x( t ) = A IN × sin(ωIN T ) = A IN × sin ωIN ( t + ∆T ) = A IN × sin(ωIN t ) × cos(ωIN ∆T ) + A IN × cos(ωIN t ) × sin ( ωIN ∆T )

1 ωIN∆T

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Texas Instruments Incorporated Data Acquisition

This results in x( t ) = A IN × sin(ωIN t ) + A IN × cos(ωIN t ) × ωIN ∆T.

Ideal Sample Error Sample

Focusing on the error sample and substituting ∆T produces:

−B × sin(ωS t ) B 1
x( t ) = A IN × ωIN × cos(ωIN t ) = A IN × ωIN × × {sin ( −ωS + ωIN ) × t  + sin ( −ωS − ωIN ) × t  }
A × ωCLK A × ωCLK 2
Scale Factor of Two Frequency Products:
Spur Amplitude –ωS + ωIN and –ωS – ωIN

Therefore, it can be observed that each spurious component of the sampling clock generates two spurs, S1 and S2, in the
data converter with amplitude and frequencies relative to the input signal as follows.
B wIN B fIN
S1 and S2 amplitude: × = × or, in terms of decibels,
A 2 × wCLK A 2 × fCLK
 f 
= B − A + 20 log  IN .
 2× fCLK 
S1 and S2 frequencies: fS1 = − fS − fIN
fS 2 = −fS + fIN
The resulting spurs can be shifted by one clock period, 2p/T = fCLK, and considering fS – fCLK = m yields:
fS1 = − fS − fIN + fCLK = −fIN + fCLK − fS = −( fIN − fCLK + fS ) = −( fIN + m ) = fIN + m
fS 2 = − fS + fIN + fCLK = + fIN + fCLK − fS = fIN − m

These equations show that the frequencies of the gener­ Sometimes the fast Fourier transform (FFT) plot can be
ated spurs will be centered around the input signal and a bit misleading when one is trying to trace spurs back to
offset by the distance m, which is the difference between their origins. If the clock spur is relatively far from the
the clock frequency and the clock-spur frequency. The clock frequency, the generated spurs of the ADC can get
amplitude of the generated spurs, on the other hand, is pushed outside the plot’s boundaries—either to negative
highly dependent upon the input frequency. For every frequencies or beyond fCLK/2. The spurs then alias back in-
doubling of the input frequency (e.g., fIN = 20 MHz versus band and generate an asymmetric FFT plot, as demon-
fIN = 10 MHz), the spur amplitude increases by 6 dB! strated in Figure 3.
Hence, as system designers consider sampling in higher
Nyquist zones, this relationship becomes very important
to them.

Figure 3. Spurs pushed outside the FFT band and aliased back in-band

m m m m

fS1 fS2 fCLK /2 fS1 fS2 fCLK /2

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 Data Acquisition Texas Instruments Incorporated

Measurements Figure 4. Test setup to mix a spur and

To further demonstrate the impact of the spur’s frequency clock signal
and amplitude, the following experiment was set up (see
Figure 4). A low-jitter-signal generator was used to provide
fCLK fS
a sine-wave input signal to TI’s ADS5463 evaluation module Clock Generator Power Spur
(EVM). The ADC input was sampled with a 122.88-MHz 122.88 MHz Combiner Generator
clock, and a power combiner and third signal generator
were used to mix a spur into the clock’s frequency. This
way the frequency and amplitude of the spur could easily Phase-Noise
be adjusted. The spur’s amplitude and frequency were Analyzer
verified with a phase-noise analyzer.
For the first experiment, the spur generator was set up
to output a tone with a frequency of 102 MHz and an Clock
fIN
amplitude of –30 dBm. The power combiner reduced the Signal
Data ADS5463
clock and spur signals by about 3 dB. The phase-noise Generator
analyzer showed the amplitudes of the clock and spur at
–9 dBm and about –33 dBm, respectively, with an offset
(m) of about 20.9 MHz (122.88 MHz – 102 MHz) as illus-
trated in the screen capture in Figure 5. As previously
derived, this setup generated two spurs with a spur-
amplitude scale factor of
 f   10 MHz 
B − A + 20 log  IN  = −33 dBm − ( −9 dBm ) + 20 log   = −51.8 dBc
 2 × fCLK   2 × 122. 88 MHz 
and spur frequencies of
fS1 = fIN + m = 10 MHz + 20.9 MHz = 30.9 MHz and
fS 2 = fIN − m = 10 MHz − 20.9
9 MHz = −10.9 MHz.

Figure 5. Phase-noise plot of 102-MHz spur with

–33-dBm amplitude

–10
–20 33 dB
–30 fS = 102 MHz (–30 dBm),
m = 20-MHz Offset
–40
–50
Phase Noise (dBc/Hz)

–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
100 1k 10 k 100 k 1M 10 M
Frequency (Hz)

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Texas Instruments Incorporated Data Acquisition

The resulting FFT plot of the ADS5463

Figure 6. FFT output of 102-MHz, –30-dBm clock spur
output is shown in Figure 6. The gener-
ated spurs are about 52 dB lower than
the input signal and are located at 10.9 0
and 30.9 MHz. This matches the calcu- fIN = 10-MHz sine wave
lated values very closely. –20 fS = 102 MHz (–30 dBm)
52 dB
Next, the spur amplitude was lowered

FFT Output Plot (dBc)

fS2 = 10.9 MHz fS1 = 30.9 MHz
from –30 dBm to –40 dBm. It was expect­ –40
ed that the S1 and S2 spur amplitudes
would drop by 10 dB as well. This was –60
confirmed with the FFT plot of the
ADS5463 output, as illus­trated in –80
Figure 7. The frequencies of the spurs
stayed the same. –100
As discussed previously, the spur
ampli­tude is highly dependent upon the –120
frequency of the input signal. To further 0 10 20 30 40 50 60
illustrate this, the frequency of the input Frequency (MHz)
signal was increased from 10 MHz to
100 MHz. This changed the spur-
amplitude scale factor to
 f   100 MHz 
B − A + 20log  IN  = −33 dBm − ( − 9 dBm) + 20log   = −24 − 7.8 = −31.8 dBc
 2× f   2 × 122.88 MHz 
 CLK 
and the frequencies of the two spurs to fS1 = − fS + fIN = −102 MHz + 100 MHz = −2 MHz and
fS 2 = − fS − fIN = −102 MHz − 100 MHz = −202 MHz.
Aliasing them back in-band generated two spurs, fS1 = −2 MHz = +2 MHz and
fS 2 = −202 MHz + ( 2 × 122.88 MHz) = 43.8 MHz .

Figure 7. FFT output of 102-MHz, –40-dBm clock spur

0
fIN = 10-MHz sine wave
–20 fS = 102 MHz (–40 dBm)
FFT Output Plot (dBc)

62 dB
–40 fS2 = 10.9 MHz fS1 = 30.9 MHz

–60

–80

–100

–120
0 10 20 30 40 50 60
Frequency (MHz)

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 Data Acquisition Texas Instruments Incorporated

This was also confirmed with the FFT plot of the ADS5463 Once again, this correlated very well with the FFT out-
output (see Figure 8). put plot from the ADS5463, as illustrated in Figure 9.
For the last experiment, a comparison of spur frequen-
cies was made with the clock frequency set at 102 MHz Practical example
and at 132 MHz. The spur amplitude was set to –30 dBm, Let’s go back and analyze the case of the CDCE72010,
and the input signal was set to 10 MHz. These settings mentioned earlier under “Introduction.” This device’s low-
caused the spur-frequency offset (m) to change from jitter phase-locked loop was configured to drive the TI
about 20.9 MHz to about 9.1 MHz, respectively. Two new ADS5483 with LVDS outputs at 122.88 MSPS. No filter
spur frequencies resulted: was placed between the outputs of the CDCE72010 and
the clock input of the ADS5483. This way the full effect of
fS1 = fIN + m = 10 MHz + 9.1 MHz = 19.1 MHz
the clock spurs in a real-world design can be observed.
fS 2 = fIN − m = 10 MHz − 9.1 MHz = 0.9 MHz

Figure 8. FFT output of 102-MHz, –30-dBm clock spur

0
fIN = 100-MHz sine wave
32 dB fS = 102 MHz (–30 dBm)
–20
FFT Output Plot (dBc)

fS2 = 43.4 MHz

–40 fS1 = 1.7 MHz

–60

–80

–100

–120
0 10 20 30 40 50 60
Frequency (MHz)

Figure 9. FFT output of –30-dBm clock spur at 132 MHz

versus 102 MHz

0
Spurs at Spurs at fIN = 10-MHz sine wave
–20 0.9 and 10.9 and fS = 102 MHz (–30 dBm)
19.1 MHz 30.9 MHz
FFT Output Plot (dBc)

fS = 132 MHz (–30 dBm)

–40

–60

–80

–100

–120
0 10 20 30 40 50 60
Frequency (MHz)

10

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Texas Instruments Incorporated Data Acquisition

The phase-noise plot of the unfiltered CDCE72010 in

Figure 10. Phase-noise plot of CDCE72010’s
Figure 10 shows two spurs that will impact the SFDR
unfiltered LVDS output
performance of the ADS5483.One spur (S1) is offset
about 27 MHz with an amplitude of about –130 dBc/Hz;
the other spur (S2) is offset about 3 MHz with an ampli- –100
tude of about –138 dBc/Hz. The actual spurs are 6 dB
lower than shown in the plot because the phase-noise –110 S1 Spur at ~ 27- MHz Offset
and ~ –130 dBc/Hz
analyzer sums the spurs of the two sidebands together.
–120
The amplitudes of the two spurs can be converted

LVDS Output (dBc/Hz)

from dBc/Hz to dBc as described before: S2 Spur at ~ 3-MHz Offset
–130
and ~ –138 dBc/Hz
For S1, 136 dBc / Hz = −136 dBc + 10 log( 27 MHz × 1%)
= −136 dBc + 54.4 dB –140

= −81.6 dBc .
–150
For S2, − 144 dBc / Hz = −144 dBc + 10 log(3 MHz × 1%)
= −144 dBc + 45 dB –160
= −99 dBc .
–170
These results can be used to calculate the spur ampli-
tudes of the ADC output spectrum: –180
100 1k 10 k 100 k 1M 10 M
 100 MHz 
S1 = 81.6 dBc + 20 log   Frequency (Hz)
 2 × 122.88 MHz 
= −81.6 dBc − 7.8 dB

= −89.4 dBc
Figure 11. FFT output with 100-MHz input and a
 100 MHz  122.88-MHz LVDS clock
S2 = −99 dBc + 20 log  
 2 × 122.88 MHz 
= −99 dBc − 7.8 dB 0
S1 = – 87.2 dBc fIN = 100-MHz sine wave
= −106.8 dBc –20 mS1 offset = 27 MHz Clock Driver: CDCE72010
These amplitudes match the measured spur
FFT Output Plot (dB)

Test Device: ADS5483

amplitudes of the ADC output spectrum – 40
fairly well (within 1 to 2 dB), as shown in
Figure 11. – 60 S2 = – 107.8 dBc
mS2 offset = 2.6 MHz
– 80

–100

–120
0 10 20 30 40 50 60
Frequency (MHz)

11

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 Data Acquisition Texas Instruments Incorporated

Figure 12. FFT output with 122.88-MHz clock and a 102-MHz, –30-dBm spur

fIN = 10-MHz sine wave

Test Device: ADS5463
SFDR  52 dBc

Spurs 1 and 2
SNR  50 dBFS

Impact of clock spurs on SNR For calculating the SNR of the data converter, the DJ
Besides reducing the SFDR, spurs on the clock also impact needs to be added to the phase noise of the clock and the
the SNR of the data converter. Since the spurs are at a aperture jitter of the ADC. However, in this case, the DJ
fixed frequency, they are considered deterministic jitter far exceeds the other two jitter components. Therefore,
(DJ); and they contribute to the overall clock jitter, which the resulting SNR can be calculated with a jitter of about
in turn highly impacts the SNR. 52 ps (fIN = 10 MHz), which is approximately 50.5 dBFS.
The peak-to-peak DJ from the clock spur can be The resulting FFT plot of this setup with the ADS5463
approximated by is shown in Figure 12. The plot clearly shows the two
resulting spurs with an amplitude of –52 dBc and an SFDR
SX ( dBc )
of about –52 dBc. The SNR ≈ 50 dBFS, which matches the
2 × 10 20 calculated value very well.
DJPP ≈ ,
p × fCLK
Conclusion
where SX (dBc) is the spur amplitude in dBc. The RMS This article has shown that spurs on the ADC sampling
jitter can be calculated as clock can significantly degrade the overall system SFDR
DJPP as well as the SNR. This effect gets amplified even more
DJRMS ≈ . in undersampling applications where the signal input is
14
moved to higher frequencies than those traditionally used
As in the first experiment, with the measured amplitude for baseband input. Therefore, it can be concluded that a
of the spurs at –33 dBm and that of the clock at about filtered, high-quality sampling clock is necessary for system
–10 dBm, the relative spur amplitude is roughly engineers who are trying to achieve maximum data-
–33 dBm – (–10 dBm) = –23 dBc. converter performance.
Substituting –23 dBc into the formula for DJRMS yields Related Web sites
−23
dataconverter.ti.com
DJ 1 2 × 10 20 www.ti.com/sc/device/partnumber
DJRMS ≈ PP = × = 26 ps.
14 14 p × 122.88 MHz Replace partnumber with ADS5463, ADS5483, or
CDCE72010
Since there are two spurs with a 20-MHz offset, the 26-ps
DJ of each spur can be summed together for a total DJ of
about 52 ps.

12

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 IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
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or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
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