Lect 5A LV Current Source Implementation
Lect 5A LV Current Source Implementation
C
S
M
Low Voltage Power Supply A
Current Source
• Simple implementation of a current source in many
applications including a tail current yields a low output
impedance.
• Cascode implementations of current sources yields a larger
output impedance, however the trade-off is the reduction
on the headroom.
• One alternative implementation of a current source with
higher output impedance without sacrificing significant
overhead is presented next.
TAMU-AMSC
• The current source discussed here has an output resistance about 25 times
larger than that of a single transistor current source.
• This current source improves the common-mode input range and the CMRR
of differential pairs.
This current source is applied at the PMOS differential pair ( M2i and M1i) at node Y
Vdd
Z
M2 M1 Vx
A I R 0S
X Y
I R 0B
IB
(b)
M1i R 0S Vi-
Vi+ M2i
(a)
Analog and Mixed-Signal Center (AMSC) TAMU
A conceptual Schematic of the low voltage current source. (a) Current source representation
(b) Architecture
You, F., Embabi, H.K., Duque-Carrillo, J.F., Sanchez-Sinencio, E., “An improved tail current source for low voltage applications ,”
IEEE Journal of Solid-State Circuits , Volume: 32, Issue: 8 , Aug 1997, Page(s): 1173 –1180
1 g m1A o /(g o1 g oB)
R os (1)
g o 2(1 Aog m1 /(go1g ) A og m 2 / g o 2 )
oB
R os R oB (2)
Note that the resistance is negative and is equal to the resistance of the reference source I B.
g m4
R os (3)
g o3g o 4
Z
M2 M1
X Cc
Y
Io
R 0S
M4 Vb
IB ID
M3
V
I Vb
Vi1 Vi 2 M6
M i1 Mi2
Cc Vout
M3 M4
M5
Vss
Ao
As
1 s CZ g Oa IB
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An Alternative Approach for a LV Current Source*
MBC
VBC
Then
VyMAX VDD VDSSAT
icm VDD
Vicmcan be extended to the upper rail V MAX
* J. Ramirez-Angulo, R. G. Carvajal and A. J. Lopez-Martin, “Single Transistor High Impedance Tail Current Source with Extended
Common-Mode Input Range and Reduced Supply Requirements”, IEEE Trans. on Circuits and Systems II, Vol. 54, No. 7,
pp. 581-585, July 2007.
VBC MCB
• To reduce mismatch betweeen
IBC VDS1 and VDS2 a diode connected
VZ
M2 M1 NMOS MDP is inserted.
MDP MCP
Vy
IBREF + IBC
- M2i +
v in M1i MBP VBP v in
Goals: To reduce the input impedance and to increase the output impedance,
while keeping the voltage operation
Iout
Iin Iout
Iin Vref Vref
Mc
M2 Mc
Mm
M1 Mm
M1 Vmirror
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Iout
Iout IB IB Iin Iout
IB IB Iin
Iin M5
Vcas M2 M4
M2 M2 M4 X
M1 M3 M1 M3 M1 M3
Vshift Vdd
Iin Iin IB1 Iin Iout
Iout M3 M4 Iout
ROB
AFB
M1 M2
M1 M2 M1 M2
IB2
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