CS305

Computer Architecture
Instruction Set Design

Bhaskaran Raman
Room 406, KR Building
Department of CSE, IIT Bombay
http://www.cse.iitb.ac.in/~br
 Instruction Set: What and Why
HLL code examples:
C/C++
f()->next = (g() > h()) ? k() : NULL;
Perl
$line =~ s/abc/xyz/g;

 Simple for programmers to write

 But, too complex to be implemented directly in hardware
 Solution: express complex statements as a sequence of simple
statements
 Instruction set: the set of (relatively) simple instructions using
which higher level language statements can be expressed
 A Simple Example
C code:
a = b + c;
d = e + f;
Compiler

Assembly code: Assembler: Machine code:

lw $s1, 4($s0) instruction ...0...1...
encoding
lw $s2, 8($s0) (straight-
...0...1...
add $s3, $s1, $s2 forward) ...0...1...
sw ($s0), $s3 ...0...1...
lw $s3, 16($s0) ...0...1...
lw $s4, 20($s0) ...0...1...
add $s5, $s3, $s4 ...0...1...
sw 12($s0), $s5 ...0...1...
independent
Instruction Set
Algorithm Instruction set is the interface
Machine

Programmer between hardware and

High-Level Language (HLL)
software
Compiler Interface: instruction set
Assembly Language Interface design:
• Central part of any system
Machine

Assembler
specific

Machine Language
design
• Interface before
Computer designer
implementation!
Digital Logic • Allows abstraction,
independence
• Challenge: should be easy
to use by the layer above
 Instruction Set Defines a Machine
HLL code examples:
C/C++
f()->next = (g() > h()) ? k() : NULL;
Perl
$line =~ s/abc/xyz/g;
MIPS's x86's ARM's
instruction instruction instruction
set set set

Assembly code Assembly code

Assembly code
(machine (machine
(machine code)
code) code)
for MIPS
for x86 for ARM
 Instruction Set and the
Stored Program Concept
Control Memory Input

Processor
path =
Program
Data + Output
path Data

● At the processor, two steps in a loop:

● Fetch instruction from memory
● Execute instruction
– May involve data transfer from/to memory
 The Two Aspects of an Instruction
● Instruction: operation, operand
● Example: a := b + c
– Operation is addition
– Operands are b, c, a
– For our discussion: “result” is also considered an operand
● What should be the instruction set? ==
● What set of operations to support?
● What set of operands to support?
● We’ll learn these in context of: the MIPS instruction set
 Registers: Very Fast Operands
Control Input

Processor
path
Registers Memory
Data Output
path

● Registers: very small memory, inside the processor

● Small ==> fast to read/write
● Small also ==> easy to encode instructions (as we'll see)
● Integral part of the instruction set architecture (i.e. the
hardware-software interface) [NOT a cache]
● MIPS has 32 registers, each of 32-bits
 Some Terminology
● 32-bits = 4-bytes = 1-word
● 16-bits = 2-bytes = half-word
● 1-word is the (common-case) unit of data in MIPS
● 32-bit architecture, also called MIPS32
● 64-bit MIPS architecture also exists: MIPS64
● 32-bit & 64-bit architectures are common
● Low end embedded platforms: 8-bit or 16-bit architectures
 Your First MIPS Instruction
add <res>, <op1>, <op2>
Example:
add $s3, $s1, $s2
● The add instruction has exactly 3 operands
● Why not support more operands? Variable number?
● Regularity ==> simplicity in hardware implementation
● Simplicity ==> fast implementation
● All 3 operands are registers
● In MIPS: 32 registers numbered 0-31
● $s0-$s7 are assembly language names for register numbers
16-23 respectively (why? answered later)
 Constant or Immediate Operands
addi <res>, <op1>, <const>
Example:
addi $s3, $s1, 123

● HLL constructs use immediate operands frequently

● Design principle: make the common case fast
● Most instructions have a version with immediate operands
● Question: common case use of constant addition in C?
 Memory Operations: Load and Store
lw <dst_reg>, <offset>(<base_reg>)  Load and store in units of 1-
sw <offset>(<base_reg>), <src_reg>
Example:
word: terminology w.r.t. CPU
lw $s1, 4($s0)  Also called data transfer
sw 12($s0), $s5 instns: memory ↔ registers
0xFFFF FFFC  Address: 32-bit value,
specified as base register +

32-bit address
Memory offset
0x0000 000C space  Question: why is this useful?
0x0000 0008  Alignment restriction: address
0x0000 0004
0x0000 0000 has to be a unit of 4 (why?
32-bits answered later)
 Test Your Understanding...
● Is a subi instruction needed? Why or why not?
● Is sub instruction needed? Why or why not?
 Test Your Understanding (continued)...
● Translate the following C-code into assembly lang.:
● Ex1: a[300]=x+a[200]; // all 32-bit int
● What more information do you need?
● Ex2: a[300]=x+a[i+j]; // all 32-bit int
● Can you do it using instructions known to you so far?

# a in s0, x in s1 # a in s0, x in s1
lw $t0, 800($s0) # i in s2, j in s3
add $t1, $t0, $s1 add $t2, $s2, $s3
sw 1200($s0), $t1 muli $t2, $t2, 4
add $t3, $t2, $s0
Registers $t0-$t9 lw $t0, 0($t3)
usually used for add $t1, $t0, $s1
temporary values sw 1200($s0), $t1
 Notion of Register Assignment
● Registers are statically assigned by the
compiler to registers
● Register management during code generation:
one of the important jobs of the compiler
● Example from previous exercise...
 Instructions for
Bit-Wise Logical Operations
Logical C/C++/Java MIPS
Operators Operators Instructions
Shift Left << sll
Shift Right >> srl
Bit-by-bit AND & and, andi
Bit-by-bit OR | or, ori
Bit-by-bit NOT ~ nor
 The Notion of the Program Counter
 The program is fetched and
executed instruction-by-
Program
instruction
(in memory)  Program Counter (PC)
PC
 A special 32-bit register

 Points to the current

• In MIPS: (only) special instructions for PC instruction

manipulation  For sequential execution:

• PC not part of the register file PC += 4 for each instruction

 Non-sequential execution
• In some other architectures: arithmetic or
data transfer instructions can also be used implemented through
to manipulate the PC manipulation of the PC
 Branching Instructions
● Stored program concept: usually sequential execution
● Many cases of non-sequential execution:
● If-then-else, with nesting
● Loops
● Procedure/function calls
● Goto (bad programming normally)
● Switch: special-case of nested if-then-else
● Instruction set support for these is required...
Conditional and Unconditional Branches
● Two conditional branch instructions:
● beq <reg1>, <reg2>, <branch_target>
● bne <reg1>, <reg2>, <branch_target>
● An unconditional branch, or jump instruction:
● j <jump_target>
● Branch (or jump) target specification:
● In assembly language: it is a label
● In machine language, it is a PC-relative offset
– Assembler computes this offset from the program
 Using Branches for If-Then-Else
if(x == 0) { y=x+y; } else { y=x-y; }

Convention in my slides:
s0, s1... assigned to variables# in order of appearance

# s0 is x, s1 is y
bne $s0, $zero, ELSE
add $s1, $s0, $s1
j EXIT
ELSE:
sub $s1, $s0, $s1
EXIT:
# Further instructions below
Note: use of $zero register (make the common case fast)
 Using Branches for Loops
while(a[i] != 0) i++;

# s0 is a, s1 is i
BEGIN:
sll $t0, $s1, 2
add $t0, $t0, $s0
lw $t1, 0($t0)
beq $t1, $zero, EXIT
addi $s1, $s1, 1
j BEGIN
EXIT:
# Further instructions below

Q: is $t1 really needed above?

 Testing Other Branch Conditions
● slt <dst>, <reg1>, <reg2>
● slt == set less than
● <dst> is set to 1 if <reg1> is less than <reg2>, 0 otherwise
● slti <dst>, <reg1>, <immediate>
● Can be followed by a bne or beq instruction
● How about <= or > or >= comparisons?
● Note: register 0 in the register file is always ZERO
● Denoted $zero in the assembly language
● Programs use 0 in comparison operations very frequently
● Why not single blt or blti instruction?
 For Loop: An Example
for(i = 0; i < 10; i++) { a[i] = 0; }

# s0 is i, s1 is a
addi $s0, $zero, 0
BEGIN:
slti $t0, $s0, 10
beq $t0, $zero, EXIT
sll $t1, $s0, 2
add $t2, $t1, $s1
sw 0($t2), $zero
addi $s0, $s0, 1
j BEGIN
EXIT:
# Further instructions below

Q: min # temporary registers needed for above code secn?