0% found this document useful (0 votes)
0 views

Cadence Question Paper Set 2

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
0 views

Cadence Question Paper Set 2

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 8

QP Set 2

Question 1:

In the circuit shown, the positive angular frequency ω (in radians per second) at
which the magnitude of the phase difference between the voltages V 1 and V2
equals π/4 radians, is __________.

Question 2:

For the operational amplifier circuit shown, the output saturation voltages are ±
15V. The upper and lower threshold voltages for the circuit are, respectively,

(1) +5 V and –5 V
(2) +7 V and –3 V
(3) +3 V and –7 V
(4) +3 V and –3 V

Question 3:

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation
delays. The present input condition is: P = Q = ‘0’. If the input condition is changed
simultaneously to P = Q = ‘1’, the outputs X and Y are:
(1) X = ‘1’, Y = ‘1’
(2) either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘1’
(3) either X = ‘1’, Y = ‘1’ or X = ‘0’, Y = ‘0’
(4) X = ‘0’, Y = ‘0’

Question 4:

The clock frequency of an 8085 microprocessor is 5 MHz. If the time required to


execute an instruction is 1.4 μs, then the number of T-states needed for executing
the instruction is:

(1) 1
(2) 6
(3) 7
(4) 8

Question 5:

Consider the D-Latch shown in the figure, which is transparent when its clock input
CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a
50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty
cycle at the output of the latch in percentage is __________.

Question 6:

The figure shown an RLC circuit excited by the sinusoidal voltage 100 cos (3t)
Volts, where t is in seconds. The ratio amplitude of V2/amplitude of V1 is
__________.

Question 7:

In the figure shown, the NPN transistor acts as a switch


For the input Vin(t)as shown in the figure, the transistor switches between the cut-off
and saturation regions of operation, when T is large. Assume collector to- emitter
voltage at saturation VCE(sat) = 0.2V and base-to-emitter voltage VBE = 0.7V.The
minimum value of the common-base current gain (α) of the transistor for the
switching should be_______.

Question 8:

The amplifier circuit shown in the figure is implemented using a compensated


operational amplifier (op-amp) and has an open-loop voltage gain. A 0 = 105 V/V and
an open-loop cut-off frequency, fc = 8 Hz. The voltage gain of the amplifier at 15
kHz, in V/V, is _________.

Question 9:

Which one of the following gives the simplified sum of products expression for the
Boolean function F = m0 + m2 +m3 + m5, where m0,m2,m3 and m5 are minterms
corresponding to the inputs A, B, and C with A as the MSB and C as the LSB?

Question 10:

A 4-bit shift register circuit configured for right-shift operation is D in →A, A →B, B→ C,
C→ D, is shown. If the present state of the shift register is ABCD = 1101, the number
of clock cycles required to reach the state ABCD = 1111 is ______.
Question 11:

A finite state machine (FSM) is implemented using the D flip-flops A and B and logic
gates, as shown in the figure below. The four possible states of the FSM are Q A QB =
00, 01, 10, and 11.

Assume that XIN is held at a constant logic level throughout the operation of the
FSM. When the FSM is initialized to the state Q AQB = 00 and clocked, after a few
clock cycles, I starts cycling through.

(1) All of the four possible states if X IN = 1


(2) Three of the four possible states if X IN = 0
(3) Only two of the four possible states if X IN = 1
(4) Only two of the possible states if X IN = 0

Question 12:

In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5
volts. At the input, unit step voltage is applied, i.e.VIN(t) = u(t) volts. Also, at t = 0,
the voltage across each of the capacitors is zero.

The time t in milliseconds, at which the output voltage V OUT crosses −10 V is

(A) 2.5
(B) 5
(C) 7.5
(D) 10

Question 13:

A good transimpedance amplifier has


(A) low input impedance and high output impedance.
(B) high input impedance and high output impedance.
(C) high input impedance and low output impedance.
(D) low input impedance and low output impedance.
Question 14:

The circuit shown in the figure is used to provide regulated voltage (5V) across the
1K  resistor. Assume that the Zener diode has a constant reverse breakdown
voltage for a current range, starting from a minimum required Zener current, IZ m in
= 2m A to its maximum allowable current. The input voltage V1 may vary by 5%
from its nominal value of 6 V. The resistance of the diode in the breakdown region is
negligible.

The value of R and the minimum required power dissipation rating of the diode,
respectively, are
(A) 186 Ω and 10 mW
(B) 100 Ω and 40 mW
(C) 100 Ω and 10 mW
(D) 186 Ω and 40 mW

Question 15:

A four-variable Boolean function is realized using 4 × 1 multiplexers as shown in the


figure.

The minimized expression for F(U, V, W, X) is


Question 16:

For the circuit given in the figure, the voltage Vc(in volts) across the capacitor is

Question 17:

A dc current of26 µA flows through the circuit shown. The diode in the circuit is
forward biased and it has an ideality factor of one. At the quiescent point, the diode
has a junction capacitance of 0.5 nF. Its neutral region resistances can be
neglected. Assume that the room temperature thermal equivalent voltage is 26 mV.
For ω = 2* 106rad /s, the amplitude of the small-signal component of diode
current (in µA, correct to one decimal place) is _______.

Question 18:

An op-amp based circuit is implemented as shown below.

In the above circuit, assume the op-amp to be ideal. The voltage (in volts, correct to
one decimal place) at node A, connected to the negative input of the op-amp as
indicated in the figure is _________.

Question 19:
Question 20:

Consider the network shown below with R 1 = 1Ω, R2 = 2Ω, andR3 = 3Ω. The network
is connected to a constant voltage source of 11V.

The magnitude of the current (in amperes, accurate to two decimal places) through
the source is_______.

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy