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Cadence Question Paper Set 1

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Central Placement Cell - RVSCET, Coimbatore
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Cadence Question Paper Set 1

Uploaded by

Central Placement Cell - RVSCET, Coimbatore
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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QP Set 1

Question 1:

In the Given circuit, the current Ix (in mA) is

Question 2:

In the circuit shown, the breakdown voltage and the maximum current of the Zener diode are 20V and
60 mA, respectively. The values of R1 and RL are 200Ω and 1kΩ, respectively. What is the range of Vi that
will maintain the Zener diode in the ‘on’ state?

Question 3:

Consider the circuit shown in the figure.

The current l flowing through the 7 Ω resistor between P and Q (rounded off to one
decimal place) is ______A.
Question 4:

Question 5:

Question 6:
Question 7:

For the transistor M1 in the circuit shown in the figure, μnCox= 100 μA/V2 and (W/L) = 10, where μn is
the mobility of electron, Cox is the oxide capacitance per unit area, W is the width and L is the length.

The channel length modulation coefficient is ignored. If the gate-to-source voltage VGS is 1V to keep the
transistor at the edge of saturation, then the threshold voltage of the transistor (rounded off to one
decimal place) is _________ V

Question 8:

A circuit with an ideal OP AMP is shown in the figure. A pulse VIN of 20 ms duration is applied to the
input. The capacitors are initially uncharged.

The output voltage VOUT of this circuit at t = 0+ (in integer) is _________ V.


Question 9:

The propagation delay to the exclusive-OR (XOR) gate in the circuit in the figure is 3 ns. The propagation
delay of all the flip-flops is assumed to

The output voltage VOUT of this circuit at t = 0+ (in integer) is _________ V.

Question 10:

A signal crystal intrinsic semiconductor is at a temperature of 300 K with effective density of states for
holes twice that of electrons. The thermal voltage is 26 mV. The intrinsic Fermi level is shifted from mid-
band gap energy level by

Solve it

(1) 18.02 meV


(2) 9.01 meV
(3) 13.45 meV
(4) 26.90 meV

Question 11:

The components in the circuit shown below are ideal. If the op-amp is in positive feedback and the input
voltage Vi is a sine wave of amplitude 1V, the output voltage V0 is:

Solve it

(1) A non-inverted sine wave of 2 V amplitude


(2) An inverted sine wave of 1 V amplitude
(3) A square wave 5 V amplitude
(4) A constant of either + 5 V or -5 V
Question 12:

The figure below shows a multiplexer where S1 and S0 are the select lines, I0 to I3 are the input data lines,
EN is the enable line and F(P,Q,R) is the output, F is:

Solve it

Question 13:

The current in the RL-circuit shown below is i(t)=10cos(5t−π/4)A. The value of the inductor (rounded off
to two decimal places) is _________ H.

Question 14:

In the circuit shown below, all the components are ideal and the input voltage is sinusoidal. The
magnitude of the steady-state output V0 (rounded off to two decimal places) is _________ V.
Question 15:

In the circuit shown below, all the components are ideal. If Vi is +2V, the current I0 sourced by the op-
amp is ________ mA.

Question 16:

The current I in the given network is

Solve it

2.38 ∠–96.37° A
(1) 0A

2.38 ∠143.63° A
(2)

2.38 ∠–23.63° A
(3)
(4)

Question 17:

An enhancement MOSFET of threshold voltage 3 V is being used in the sample and hold circuit given
below. Assume that the substrate of the MOS devices is connected to –10V. If the input voltage V 1 lies
between ±10V, the minimum and the maximum values of VG required for proper sampling and holding
respectively are

(1) 3 V and –3 V
(2) 10 V and –10 V
(3) 13 V and –7 V
(4) 10 V and –13 V
Question 18:

The components in the circuit given below are ideal. If R=2kΩ and C=1μF, the –3 dB
cut-off frequency of the circuit in Hz is

(1) 14.92
(2) 34.46
(3) 59.68
(4) 79.58

Question 19:

Question 20:

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