System Verilog

INTERVIEW QUESTIONS

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1 Susheela Patagar
 12. What are system task/
functions give example.

• System task/function:
• Verilog & SV includes a number of useful
tasks and functions that can be enabled
and called in the same way as user defined
tasks and functions.
• The system tasks and functions begin with
the ‘$’to distinguish them from ordinary
tasks and functions.

• Display system tasks

• Simulation control system tasks
• Simulation time control system tasks
• Random number system functions
• Bit vector system functions
• Severity system tasks
• Signal system tasks
• Array system tasks
• Conversion system functions
• Math system function
• VCD file system tasks
2 Susheela Patagar
 Display system tasks

System
Description
task

Normal display, which executes its

$display parameters wherever it is present in the
code.
Similar to $display except that $display
displays the contents in the next
$write
line.But in $write contents are displayed
in the same line.
Executes only once in a time instant,
$strobe when all processes in that time instant
have executed.
Executes only if any of its parameters
$monitor
change (in one time instant).

3 Susheela Patagar
 Simulation control system tasks

System task Description

Causes simulator to exit the

$finish()
simulation

Suspend the simulation but does not

$stop
finish it

Waits for all the program blocks and

$exit
then make an implicit call to $finish

Simulation time control system tasks

System task Description

Returns an integer i.e,64 bit

$time time,scaled to the time precision of
the module that invoked it
Same as that of $time but is a 32 bit
$stime
time.
Returns real number time, scaled to
$realtime the time precision of the module that

has invoked it
4 Susheela Patagar
 Random number system functions

System
Description
tasks
The system function $urandom
provides a mechanism for generating
pseudo-random numbers. The
$urandom
function returns a new 32-bit random
number each time it is called. The
number shall be unsigned.
The srandom() method allows
$srandom manually seeding the RNG of objects
or threads.
The $urandom_range() function
$urandom_
returns an unsigned integer within a
range
specified range.

5 Susheela Patagar
 Bit vector system functions

System task Description

$countbits(expr, Counts the no of bits in an
control bit) expression whose value match
with one of the control bits

$countones(expr) Counts ones. Equivalent to

countbits(expression,’1)

$onehot(expr) Returns true if there is atmost

one “1” in the expression

$onehot0(expr) Returns true when single bit is

high or all bits are zero

$onecold(expr) Returns true if there is atmost

one “0” in the expression

$isunknown(expr) Returns true if any bit of the

expression is x or z

6 Susheela Patagar
 Array system tasks

System task Description

Returns' the total number of

dimensions in the array (packed
and unpacked, static or dynamic) 1
for the string data type or any other
$dimensions non array type that is equivalent to
a simple bit vector, 0 for any other
type total number of unpacked
dimensions for an array (static or
dynamic) 0 for any other type
$unpacked_dim Return's the the total number of
ensions unpacked dimensions for an array
(static or dynamic).
$left Return's the left bound (MSB) of
the dimension
$right Return's the right bound (LSB) of
the dimension
$low Return's the minimum of $left and
$right of the dimension
$high Return's the maximum of $left and
$right of the dimension
$increment Return's 1 if $left is greater than
$right else returns -1
$size Returns the number of elements in
the dimension

7 Susheela Patagar
 Severity system tasks
System tasks Description

Used to display informational

$info
message during simulation
Used to display the warning
$warning message(potential errors)during
simulation
Used to display the run time error
$error
message(report critical errors)
Used to report a fatal error message
$fatal and immediately terminate the
simulation

Conversion system functions

System function Description

Convert real number to integer

$rtoi
number
Convert integer number to real
$itor
number
$realtobits Convert real number to bits

$bitstoreal Convert bits to real number

Convert shortreal number to
$shortrealtobits
bits
$bitstoshortreal Convert bits to real number
8 Susheela Patagar
 Signal system tasks

System task Description

Return true if signal changes from

$rose
0/x/z to 1

Return true if signal changes from

$fell
1/x/z to 0

Return true if the value of a signal

did not change in the current
$stable
evaluation and previous evaluation
point
Return true if the value of a signal
did change in the current
$changed
evaluation and previous evaluation
point

9 Susheela Patagar
 Math system function

System task

$clog2(x)

$ln(x)
$log10(x)
$exp(x)
$sqrt(x)
$pow(x,y)
$sin(x) , $sinh(x)
$cos(x), $cosh(x)
$tan(x), $tanh(x)

10 Susheela Patagar
 VCD file system tasks

System task Description

Allows you to specify the name of
$dumpfile
the vcd file
Lists the variables to dump into the
$dumpvars
file specified by $dumpfile

$dumpon/off Used to suspend the dump

Is used to empty the current vcd

file to verify that all the data in the
$dumpflush
data buffer are flushed/stored in the
vcd file
$dumplimit Sets the size of vcd file
All the variables are dumped into
the dumpfile at that particular
$dumpall time,regardless of whether the port
values have changed since the last
time step
Dumps all the ports i.e, primary IO
$dumpports
pins

11 Susheela Patagar
 13. Verilog and system Verilog
format specifiers
Format specifier Description
%b %B Binary format
%c %C Character format
%d %D Decimal format
%e %E Exponential format
Floating point format(fixed-point
%f %F
format)
%g %G General format floating point
%h,%x %H,%X Hexadecimal format
%l %L Library binding information
%m %M Hierarchical name, no expression
%o %O Octal format
Displaying complex data
%p %P
structures
%s %S String format
Simulation time, expression is
%t %T
$time
Unformatted two value data 0
%u %U
and 1
%v %V Net signal strength
Unformatted four value data 0,
%z %Z
1, x, z

12 Susheela Patagar
14. Difference b/w format specifier
%d, %0d, %4d & %04d
module top;
reg[7:0] a; //8 bit data

initial begin a= 5 a=5 a= 5 a=0005

a=5;
$display("a=%d | a=%0d | a=%4d | a=%04d",a,a,a,a);
a=255;
$display("a=%d | a=%0d | a=%4d | a=%04d",a,a,a,a);
end
endmodule
a=255 a=255 a= 255 a=0255
%d=Used to display numbers with a fixed width that
accommodates the largest possible value for the expression
being displayed.
--------------------------------------------------------------------
%0d=Used to display numbers with a minimum width, but
without any leading zeros or spaces.
--------------------------------------------------------------------
%4d=Used to display numbers with a minimum width of
four characters, padding with leading spaces if necessary to
meet the width requirement.
--------------------------------------------------------------------
%04d=Used to display numbers with a minimum width of
four characters, padding with leading zeros if necessary to
meet the width requirement.

13 Susheela Patagar
15. Find the non-repeated value in
an odd sized array where all
elements appear exactly twice
except for one.

module find_non_repeated_value;
int unique_val;
int a[9] = '{5, 3, 8, 5, 2, 3, 8, 6, 2};
//(non-repeated value: 6) Every element except
the unique one cancels
out because a^a=0.
initial begin 000 ^ 110 = 110
for (int i = 1; i < $size(a); i++)
begin A B A^B
0 0 0
a[i] = ( a[i-1] ^ a[i] ); 0 1 1
1 0 1
unique_val = a[i]; 1 1 0

end
$display("unique value=%0d",unique_val);
end
endmodule If the element in odd
sized array repeats even
time (2,4,6,8…) then go
for XOR logic to find the
unique value

14 Susheela Patagar
16. How to swap two values
without temp variable?
module swap_example;
logic [3:0] a = 5;
logic [3:0] b = 3;
a=5 b=3
initial begin
$display(“Before: a=%0d b=%0d", a, b);
a = a ^ b; a = 5^3;
b=a^b XOR b = (5^3)^3; →5
a = (5^3)^5; →3
a = a ^ b;
$display(“After: a=%0d b=%0d", a, b);
end
endmodule a=3 b=5

a = a + b;
Arithmetic operators b = a - b;
a = a - b;

15 Susheela Patagar
17. How to implement randc
behaviour without using randc
keyword?
`define width 3
class packet;
rand logic[(`width-1):0] a;
int queue[$];
constraint c1 { !(a inside {queue});}
function void post_randomize();
queue.push_back(a);
if(queue.size == 2**`width)
queue.delete(); // queue = {};
endfunction
endclass
module randc_gen;
packet p;
initial begin
p = new();
repeat(10)begin
p.randomize();
$display(p.a);
end
end
endmodule
16 Susheela Patagar
18. How to generate and check
even and odd parity using
constraints?
class packet;
XOR:
rand bit [9:0] data; Odd 1’s detector
rand bit even_parity,odd_parity;
constraint c1{(even_parity ^ (^data)) = = 0;}
constraint c2{(odd_parity ^ (^data)) = = 1;}
endclass
module q_con; a b XOR
packet p; 0 0 0
0 1 1
initial begin
1 0 1
repeat(10)begin 1 1 0
p=new();
p.randomize();
$display(“data=%b : even_parity=%0d |
odd_parity=%0d",p.data,p.even_parity,
p.odd_parity);
end
end
endmodule
17 Susheela Patagar
 19. What is the difference
between $display, $write,
$monitor and $strobe?
$display :
• $display is the normal display, which
executes its parameters wherever it is
present in the code.
• Executes in active region
$write:
• $write is similar to $display but the
contents are displayed in the same line.
• Executes in active region
$strobe:
• $strobe executes only once in a time unit,
when all processes in that time unit have
executed.
• Executes in postpone region
$monitor:
• $monitor executes only if any of its
parameters change (in one time unit).
• Executes in postpone region
18 Susheela Patagar
module print;
reg a,b,c; Example
initial begin
#1;
{a,b} = 2'b01;
c = 1;
b <= 0;
$strobe("at time=%0t strobe1 : a=%0b | b=%0b | c=%0b", $time, a, b, c);
$display("at time=%0t display1 : a=%0b | b=%0b | c=%0b", $time, a, b, c);
$monitor("at time=%0t monitor1 : a=%0b | b=%0b | c=%0b", $time, a, b, c);

$strobe("at time=%0t strobe2 : a=%0b | b=%0b | c=%0b", $time, a, b, c);

$display("at time=%0t display2 : a=%0b | b=%0b | c=%0b", $time, a, b, c);
$monitor("at time=%0t monitor2 : a=%0b | b=%0b | c=%0b", $time, a, b, c);

$strobe("at time=%0t strobe3 : a=%0b | b=%0b | c=%0b", $time, a, b, c);

$display("at time=%0t displa3 : a=%0b | b=%0b | c=%0b", $time, a, b, c);
$monitor("at time=%0t monitor3 : a=%0b | b=%0b | c=%0b", $time, a, b, c);
#10;
{a,b} = 2'b10;
c = 1'bz;
#10;
{a,b} = 2'b11;
c = 0;
#100 $finish;
end
endmodule

19 Susheela Patagar