THE MEMORY SYSTEM

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Memory Systems: Basic concepts
• Memory consists of millions of storage cells which can store a bit of information having the value 1 or 0.

• The memory is organized such that a group of n bits, referred as word can be stored or retrieved in a single
basic operation.

• A unit of 8 bits form 1 Byte.

• If the word length (no: of bits in a word) of a computer is 32, then the word can store 4bytes
of information.

e.g. a 32-bit 2’s complement number, 4ASCII characters etc.

Each byte in the memory is assigned a distinct address. (smallestmemory unit that can be addressed is:
Byte) it is known as byte-addressable memory.

• The maximum size of the memory that can be used in any computer is determined by the addressing
scheme.
• Most modern computers are byte addressable.
• Byte locations have addresses 0,1,2,3,4……..2k -1
• For a 32-bit computer (word length=32 bits), each word is assigned the addresses 0,4,8,..,2k
-4
• There are two ways that the byte addresses can be assigned across a word: big endian and little
Endian.
Connection of Memory to the processor
 Speed of memory units:
• Memory Access Time → It is the time that elapses between the initiation of a memory
operation and the completion of that operation. (time between the read and MFC signal)
• Memory Cycle Time → It is the minimum time delay that required between the initiation
of the two successive memory operations. (time between two successive read signal)
SEMICONDUCTOR RAM MEMORIES
Internal Organization of Memory chips
1.Memory cells are usually organized in the form of an array, in which each cell is
capable of storing one bit of information.

2. Each row of cells constitutes a memory word, and all cells of a row are connected to
a common line referred to as the word line, which is driven by the address decoder on
the chip.

3.The cells in each column are connected to a Sense/Write circuit by two-bit lines.

4. The Sense/Write circuits are connected to the data input/output lines of the chip.
5. During a Read operation, these circuits sense, or read, the information stored in the
cells selected by a word line and transmit this information to the output data lines.

6. During a Write operation, the Sense/Write circuits receive input information and
store it in the cells of the selected word.
Example of a 1K X 1 memory chip organization

1K X 1 memory chip consists of a 10- bit address and one data line, resulting in 15 external
connections.
• The required 10-bit address is divided into two groups of 5 bits each to form the row
and column addresses for the cell array.
•A row address selects a row of 32 cells, all of which are accessed in parallel. However,
according to the column address, only one of these cells is connected to the
external data line by the output multiplexer and input de-multiplexer.
 Semiconductor RAMs
The two categories of RAM are the

• Static RAM (SRAM)

• Dynamic RAM (DRAM).
Asynchronous DRAMS, Synchronous DRAMS
SRAMs and DRAMs vary in speed, density, volatility property and cost.
STATIC RAM-SRAMs DYNAMIC RAM-DRAMs

Static RAMs generally use latches as storage Dynamic RAMs use capacitors as storage
elements and can therefore store data elements and cannot retain data very long
indefinitely as long as dc power is applied. without the capacitors being recharged by a
process called refreshing .

Used to build caches Main memories are made of DRAMS

Implementation of Static RAM

• Two inverters are cross connected to form a latch.

• The latch is connected to two bit lines by
transistors T1 and T2.
• These transistors act as switches that can be
opened / closed under the control of the word line.
• To retain the state of the latch, the word line can be
grounded which turn off the transistors.
Example:
Assume that the cell is in state1:
• Logic value at point X is 1
• Logic value at point Y is 0
• This state is retained as long as the signal on the word line is at ground level.
Read Operation
• In order to read the state of the SRAM cell, the word line is activated to close switches T1
and T2.
• The value stored in the latch is available on bit line b and its complement on b’
• Sense / write circuit connected to the bit lines monitors the states of b and b’
Write Operation
• The state of the cell is set by placing the appropriate value
on bit line b and its complement on bꞌ.
• The word line is then activated so that data is written to the latch.
• The required signal on the bit lines are generated by Sense / Write circuit.
CMOS cell (Implementation of Static RAM using CMOS)
• Transistor pairs (T3, T5) and (T4, T6) form
the inverters in the latch.
• In state 1, the voltage at point X is high by
having T3, T6 ON and T4, T5 are OFF.
• Thus T1 and T2 returned ON (Closed), bit line b
and bꞌ will have high and low signals
respectively.
• The CMOS requires 5V (in older version) or
3.3.V (in new version) of power supply voltage.
• The continuous power is needed for the
cell to retain its state.
Advantages of static memory cells
• CMOS cell has low power consumption because the current flows in the cell only when the
cell is being accessed.

• Static RAMs can be accessed quickly. Its access time is few nanoseconds. Hence it can be
used in application where speed is of critical concern.
• Refresh circuitry is not needed to retain the state.

Disadvantages of static memories

• As SRAMs requires several transistors in a single cell, SRAMs come at very high cost.
• Limited capacity: not economical to manufacture high capacity SRAMs
Dynamic Random Access Memory (DRAMs)
• Dynamic RAMs cannot retain its state even if power supply is on
• Data is stored in the form of charge stored on the capacitor
• Requires periodic refresh: the charge stored in the capacitor cannot be retained for a
long time (Due to the capacitor’s own leakage resistance)
• Less expensive than SRAMs. (Requires less hardware. One transistor and one capacitor)
• Address lines are multiplexed
Reading the contents of the cell automatically refreshes its contents.

All cells in a selected row are read at the same time , which refreshes its contents of the entire row.
Write Operation in DRAM
• The transistor of a particular cell is turned on by activating the word line.

• Depending on the value to be written (either 0 or1), appropriate voltage is supplied to the bit
line.
• The capacitor gets charged to the required voltage level.

• Refreshing of the capacitor requires periodic READ- WRITE cycles (every few msecs)
 Why do dynamic RAMs need constant refreshing? How is this done?
• After the transistor is turned off, the capacitor begins to discharge. This is caused by the
capacitor’s own leakage resistance and by the fact that the transistor continues to conduct a
tiny amount of current, measured in Pico amperes after it is turned off.
• Hence, the information stored in it can be retrieved correctly only if it is read before the
charge on the capacitor drops below some threshold value.

How is refreshing done?

• Through periodic READ- WRITE cycles.
• During a READ operation, a sense amplifier connected to the bit line senses the
charge stored in the capacitor. If the charge is above the threshold, it drives the bit line
to a full voltage, which represents bit 1. This voltage recharges the capacitor to the
full charge representing bit 1.
Types of DRAMs

Asynchronous DRAMs (ADRAM)

• Timing of the memory device is handled asynchronously

Synchronous DRAMs (SDRAM)

.Memory operations are synchronized by a clock
Toensure that the contents of a DRAM are maintained, each row of cells must be accessed
periodically to refresh the contents stored.

Fast page mode (reference)

Increase the performance of ADRAM,

Once fixed the row address is, store the row address in a latch associated with the sense
/write circuit then decode different column addresses and find various columns one
after another.

No need to decode row addresses each time, this will increase speed.
Synchronous DRAM (SDRAMs)
• The operations of the SDRAMs are directly synchronized with a clock signal.
Organization of SDRAMS
• The cell array is same as in asynchronous DRAMs.
• The address and data connections are buffered by means of registers.
• Data input registers Data output registers
output of each sense amplifier is connected to a latch
• A read operation causes the contents of all cells in the selected row to be loaded into
these latches .
• If the row is activated for refreshing purpose only then the data is not loaded into the latches.
 When a column is selected:
• Read operation: data in the latches corresponding to the selected column is placed in the output
register
• Write operation: data in the input register is loaded into the cells corresponding to the selected
column.
• SDRAMs have several modes of operation
• The modes are selected by writing control information into a mode register.

Double data rate SDRAMs (DDR SDRAMs)

• The standard SDRAM performs all actions on the rising edge of the clock signal.
• The double data rate SDRAM transfers data on both the edges (leading edge, trailing edge).
The Bandwidth of DDR-SDRAM is doubled for long burst transfer.
Memory System Considerations
 Semiconductor ROMs
SRAM and SDRAM chips are volatile:
• Lose the contents when the power is turned off.
• Many applications need memory devices to retain contents after the power is turned off.
• For example, computer is turned on, the operating system must be loaded from the disk int
the memory.
• We need to boot the OS from the disk to the main memory.
• Boot program resides in the disk due to its large size.
• The processor must execute instructions that load boot program to the main memory
for execution.
• These instructions should not be lost after the power is turned off.
• We need to store the instructions into a non-volatile memory.
• Non-volatile memory is read in the same manner as volatile memory.
• Separate writing process is needed to place information in this memory.
• Normal operation involves only reading of data, this type of memory is called Read- Onl
memory (ROM).
 PROM: Programmable ROM
• PROM allows the data to be loaded by the user.
• Programmability is achieved by inserting a fuse at point P in a ROM cell.
• Before it is programmed, the memory contains all 0‘s.
• The user can insert 1‘s at the required location by burning out the fuse at these locations
using high current pulse.
• This process is irreversible.
• Merits:
• It provides flexibility.It is faster.
• It is less expensive because they can be programmed directly by the user.
EPROM - Erasable reprogrammable ROM
• EPROM allows the stored data to be erased and new data to be loaded.
• In an EPROM cell, a connection to ground is always made at point P and a special
transistor is used, which has the ability to function either as a normal transistor or as a
disabled transistor that is always turned off.
• This transistor can be programmed to behave as a permanently open switch, by injecting a
charge into it that becomes trapped inside.
• Erasure requires dissipating the charges trapped in the transistor of memory cells.
• This can be done by exposing the chip to ultraviolet light so that EPROM chips are
mounted in packages that have transparent windows.
Merits:
• It provides flexibility during the development phase of digital system.
• It is capable of retaining the stored information for a long time.
Demerits:
• The chip must be physically removed from the circuit for reprogramming and its entire
contents are erased by UV light.
EEPROM:-Electrically Erasable ROM
• stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-
volatile memory used in computers and other electronic devices to store small amounts of data
that must be saved when power is removed, e.g., calibration tables or device configuration.

• When larger amounts of static data are to be stored (such as in USB flash drives) a specific
type of EEPROM such as flash memory is more economical than traditional EEPROM
devices.
• It is possible to erase the cell contents selectively.
• Different voltages are needed for erasing, writing, and reading the stored data. (disadvantage)
Flash memory
• Similar to EEPROM(Single transistor controlled by trapped charge )
• In EEPROM it is possible to read and write the contents of a single cell .
• In flash device it is possible to read the contents of a single cell , but it is only possible to write
an entire block of cells. Prior to writing, the previous contents of the block are erased .
• Flash device has greater capacity and lower cost per bit . They require a single power
supply voltage and consume less power in their operation.
• Low power consumption of flash memory makes it attractive for use in portable equipment tha
is battery driven . Application like hand-held computers ,cell phones ,digital cameras and MP
music players.
• Single flash chip do not provide sufficient storage capacity for the above applications