Verdi Training SystemVerilog

Based on Verdi 2007.01

Goals
To become familiar with Verdi SystemVerilog support and to
use these features to reduce the time spent on debugging.
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Target Audience
Engineers who use SystemVerilog (SV).
Verdi Training SystemVerilog Mar07
Prerequisites
Basic HDL coding skills.
Basic SystemVerilog coding skills.
Familiarity with basic Verdi functions.
Verdi Training SystemVerilog Mar07
Overview
Import SystemVerilog Designs
Debug SystemVerilog Designs
Source Code
Signal Browser
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Schematics
Dump FSDB Files
View Simulation Results
Glossary
RMB = Right Mouse Button
MMB = Middle Mouse Button
LMB = Left Mouse Button
DC = Double-click
Verdi Training SystemVerilog Mar07
DC = Double-click
D&D = Drag and Drop
SV = SystemVerilog
Objectives
After completing this section, you should be able to
Import and debug SystemVerilog designs using source code,
schematic and waveform views.
Generate FSDB files with SystemVerilog data.
View simulation results in waveform window.
Verdi Training SystemVerilog Mar07
View simulation results in waveform window.
Topics
Import SystemVerilog Designs
Debug SystemVerilog Designs
Source Code
Signal Browser
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Schematics
Dump FSDB Files
View Simulation Results
Different Ways to Bring SV Design into Verdi
SystemVerilog
Verilog
Verilog2k
.v2k
SystemVerilog
.sv
Verilog
Verilog2k
.v2k
SystemVerilog
.sv
vericom -2001
vericom -sv
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vericom
.lib++
(KDB)
verdi -sv
verdi +verilog2001ext+.v2k+ \
+systemverilogext+.sv+
verdi -lib .. -top ..
Import SV Source Code from Command Line
Directly
Load directly from file(s):
%> verdi sv f run.f
All the source files have to be SystemVerilog compliant.
If not (e.g. using SV keywords as variable names), then use other flows
Verdi Training SystemVerilog Mar07
If not (e.g. using SV keywords as variable names), then use other flows
described in next 2 slides.
Source files and/or options can be specified in the file that is argument
to f.
-sv
system.v
TopModule.v
ALUB.v
PCU.v
CCU.v
child1.v
child2.v
child3.v
master.v
pram.v
mem.v
Import Mixed SV / Verilog Source Code
For mixed Verilog/ SystemVerilog code:
%> verdi f run.f +verilog2001ext+.v2k+ +systemverilogext+.sv+.SV+
Files with extension name (.sv or .SV) will automatically be recognized as
SystemVerilog.
Files with extension name (.v2k) will automatically be recognized as Verilog-
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2001.
Files with extension name (.v) will automatically be recognized as Verilog-95.
Example run.f file:
system.v
pram.SV
TopModule.v
ALUB.v2k
CCU.sv
PCU.v
alu.v2k
-v lib.v
Compile and Import SV Source Code
from Library
First, compile the Verilog/SV source code:
Either
%> vericom f run.f +verilog2001ext+.v2k+ +systemverilogext+.sv+.SV+
Or
%> vericom f run_verilog_files.f
%> vericom -2001 f run_v2k_files.f
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%> vericom -2001 f run_v2k_files.f
%> vericom sv f run_sv_file.f
Then import:
Either
%> verdi lib work
Or
%> verdi top $root TopModule
Multiple top levels, $root and TopModule - Note the single quotes
TopModule is the top-level design module. $root is included because the design
defines some global typedefs outside any modules dont worry about this if you
dont use SV design constructs and, more specifically, global variables.
Note: Default compile library is work.lib++.
Alternate libName can be specified using -lib
option.
Topics
Import SystemVerilog Designs
Debug SystemVerilog Designs
Source Code
Signal Browser
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Schematics
Dump FSDB Files
View Simulation Results
Debug SV Designs Source Code
Implicit $root in the hierarchy browser.
Includes type
definitions.
New folder icon
for interface.
Implicit $root
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for interface.
Refer to Help
Legend for tree
node details.
Interface
Debug SV Designs generate in nTrace
Each generate
instance is a scope
in the hierarchy
browser with its
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browser with its
elements.
Debug SV Designs Signal Browser (1/3)
New dedicated browser for visualizing complex signals (e.g. structs).
Invoke the browser from nTrace, nSchema, or nWave
Tools Browse Structure Signal
Hierarchy Signal Tree Pane
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Hierarchy Scope Pane
Value Annotation
Source Code
Pane
Signal List Pane
Options form
Debug SV Designs Signal Browser (2/3)
General
Multiple Browse Signals windows can be invoked.
D&D is supported between Browse Signals and other windows.
Hierarchical Scope Pane
Same as nTrace but without package nodes.
Verdi Training SystemVerilog Mar07
Same as nTrace but without package nodes.
Signal List Pane
Supports regular expression in search window.
Complex signals will be shown in Red.
Signals are sorted alphabetically.
The two options Match Case and Show Structure Signal Only in the
Options form will be applied to this pane.
Debug SV Designs Signal Browser (3/3)
Hierarchical Signal Tree Pane
The signal tree will be built when selecting a signal in the signal list
pane.
Settings for Source Signal Value Radix and Source Signal
Value Notation in nTrace will be applied to this pane.
If an FSDB file is loaded, the annotation value will be shown for all leaf
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If an FSDB file is loaded, the annotation value will be shown for all leaf
nodes.
The Value Annotation Pane will be closed if the Show Annotation
Value option is turned off.
The annotated value will be changed according to current time point.
Source Code Pane
Enabled/disabled with the Show Source Definition and Declaration
option in the Options form.
Debug SV Designs Schematic
New symbol for visualizing interfaces.
Double-click to trace into interface.
Interface
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Double-click
Topics
Import SystemVerilog Designs
Debug SystemVerilog Designs
Source Code
Signal Browser
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Schematics
Dump FSDB Files
View Simulation Results
Dump FSDB Files System Tasks
The following Novas system tasks can be used for recording SystemVerilog
information to FSDB:
$fsdbDumpfile
To specify the FSDB file name. If not defined, the default name is verilog.fsdb.
$fsdbDumpvars
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To dump SystemVerilog results to FSDB.
SystemVerilog constructs (e.g. port interface signals, complex SystemVerilog data
constructs, etc.) are automatically dumped when the $fsdbDumpvars system task is
specified.
Two options were added to the $fsdbDumpvars system task to enable dumping of
complex SystemVerilog data constructs. The options are:
+mda Dump all memory/MDA signals but exclude MDA struct/union signals.
+all Dump all memory/MDA and struct signals.
$fsdbDumpvars(top, "+all");
Dumps all scalar, vector, memory/MDA and struct signals under top and its descendent
scopes.
Dump FSDB Files VCS Options
If you have memories or MDAs in your design, you must also specify
the '+memcbk' compile-time option.
For example (VCS 7.2 used in the example):
%> vcs P <NOVAS_INST_DIR>/share/PLI/vcsd72/SOL2/vcsd.tab \
<NOVAS_INST_DIR>/share/PLI/vcsd72/SOL2/pli.a f run.f +cli+2 \
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<NOVAS_INST_DIR>/share/PLI/vcsd72/SOL2/pli.a f run.f +cli+2 \
+vcsd line +sysvcs +memcbk
Note: For SystemVerilog only, VCS 7.1 or greater is recommended. If
SystemVerilog Assertions are also used, VCS 2005.06 or greater is
recommended.
Topics
Import SystemVerilog Designs
Debug SystemVerilog Designs
Source Code
Signal Browser
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Schematics
Dump FSDB Files
View Simulation Results
View Simulation Results Waveform
Elements of complex signals can be expanded by double-
clicking the name in nWave and shown as individual signals.
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Double-click
View Simulation Results Active Annotation
Step forwards/backwards in
time.
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Values for current time will be
annotated.
View Simulation Results
Parameter Annotation for generate
To compute and annotate variables inside a generate block (genvars)
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Value for "current scope will
be annotated.
Summary
In this section, you have learned
How to import and debug SystemVerilog designs using source
code, schematic and signal browser views.
How to generate FSDB files with SystemVerilog data.
How to view and debug simulation results in waveform window
Verdi Training SystemVerilog Mar07
How to view and debug simulation results in waveform window
and source code.
Lab Exercise
Verdi Users Guide and Tutorial, Application Tutorials chapter
Debug with SystemVerilog
Verdi Training SystemVerilog Mar07