Jaeger/Blalock

10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 1
Chapter 7
Complementary MOS (CMOS) Logic
Design
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 2
Chapter Goals
Introduce CMOS logic concepts
Explore the voltage transfer characteristics CMOS inverters
Learn to design basic and complex logic gates
Discuss static and dynamic power in CMOS logic
Present expressions for dynamic performance of CMOS logic
devices
Present noise margins for CMOS logic
Introduce dynamic logic and domino CMOS logic techniques
Introduce design techniques for cascade buffers
Explore layout of CMOS logic gates
Discuss the concept of latchup

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 3
CMOS Inverter Technology
Complementary MOS, or CMOS, needs both
PMOS and NMOS devices for their logic gates to
be realized
The concept of CMOS was introduced in 1963 by
Wanlass and Sah, but it did not become common
until the 1980s as NMOS microprocessors were
dissipating as much as 50 W and alternative
design technique was needed
CMOS still dominates digital IC design today
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 4
CMOS Inverter Technology
The CMOS inverter consists of a PMOS stacked on top on
a NMOS, but they need to be fabricated on the same wafer
To accomplish this, the technique of n-well implantation
is needed as shown in the figure which shows the cross-
section of a CMOS inverter
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 5
CMOS Inverter
(a) Circuit schematic for a CMOS inverter
(b) Simplified operation model with a high input applied
(c) Simplified operation model with a low input applied

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 6
CMOS Inverter Operation
When v
I
is pulled high (V
DD
), the PMOS inverter
is turned off, while the NMOS is turned on pulling
the output down to V
SS

When v
I
is pulled low (V
SS
), the NMOS inverter is
turned off, while the PMOS is turned on pulling
the output up to V
DD

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 7
CMOS Inverter Layout
Two methods of laying
out a CMOS inverter
are shown
The PMOS transistors
lie within the n-well,
whereas the NMOS
transistors lie in the p-
substrate
Polysilicon is used to
form common gate
connections, and metal
is used to tie the two
drains together
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 8
Static Characteristics of the CMOS
Inverter
The figure shows the
two modes of static
operation with the
circuit and simplified
models
Notice that V
H
= 5V
and V
L
= 0V, and that
I
D
= 0A which means
that there is no static
power dissipation
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 9
CMOS Voltage Transfer Characteristics
The VTC shown is for a
CMOS inverter that is
symmetrical (K
P
= K
N
)
Region 1: v
O
= V
H

v
I
< V
TN

Region 2: |v
DS
| |v
GS
V
TP
|
Region 4: v
DS
v
GS
V
TN

Region 5: v
O
= V
L

v
I
> V
DD
|V
TP
|
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 10
CMOS Voltage Transfer Characteristics
The simulation
result shows the
varying VTC of
the inverter as
V
DD
is changed
The minimum
voltage supply for
a certain MOS
technology is
2V
T
ln(2)
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 11
CMOS Voltage Transfer Characteristics
The simulation
result shows the
varying VTC of the
inverter as K
N
/K
P
=
K
R
is changed
For K
R
> 1 the
NMOS current
drive is greater and
it forces v
I
< V
DD
/2
For K
R
< 1 the
PMOS current drive
is greater and it
forces v
I
> V
DD
/2

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 12
Noise Margins for the CMOS Inverter
Noise margins
are defined by
the regions
shown in the
given figure
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 13
Noise Margins for the CMOS Inverter
( )
( )
( )
( )
( )
( )
( )
( )
2
1
1
3 1
2
2
1
1
3 1 1
2
TP TN R DD IL R
OL
R
TP TN R DD
R R
TP TN DD R
IL
R
TP TN R DD IH R
OL
R
TP TN R DD
R R
TP TN DD R
IH
V V K V V K
V
K
V V K V
K K
V V V K
V
K
V V K V V K
V
K
V V K V
K K
V V V K
V
+ +
=

+
+
=
+
=

+
+
=
IH OH H
OL IL L
P
N
R
V V NM
V V NM
K
K
K
=
=
=
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 14
Propagation Delay Estimate
The two modes of capacitive charging that contribute to
propagation delay
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 15
Propagation Delay Estimate
If it is assumed the inverter in symmetrical,
(W/L)
P
= 2.5(W/L)
N
, then
PLH
=
PHL

( )
PHL
PLH PHL
p
TN H n
onN
TN H
TN
L H
TN H
onN PHL
V V K
R
V V
V
V V
V V
C R
t
t t
t
t
=
+
=

+
(

|
|
.
|

\
|
+

=
2
1
2
1 4 ln
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 16
Rise and Fall Times
The rise and fall times are given by the following
expressions:
PLH r
PHL f
t
t
t
t
2
2
=
=
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 17
Reference Inverter Example
Design a reference inverter to achieve a delay of
250ps with a 0.1pF load given the following
information:

V V V
ps
pF C
V V
TP TN
p
DD
75 . 0
250
1 . 0
3 . 3
= =
=
=
=
t
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 18
Reference Inverter Example
Assuming the inverter is symmetrical and using
the values given in Table 7.1:
ps
V
A
K
V
A
K
PLH PHL p
p
n
250
10
25
2
'
2
'
= = =
=
=
t t t

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 19
Reference Inverter Example
Solving for R
onN
:



Then solve for the transistor ratios:

O =

+
(

|
|
.
|

\
|
+

= 2020
2
1
1 4 ln
L DD
TN DD
PHL
onN
V V
V V
C
R
t
( )
1
4 . 19
5 . 2
1
77 . 7 1
'
=
|
.
|

\
|
=
|
.
|

\
|
=

=
|
.
|

\
|
n p
TN DD onN n n
L
W
L
W
V V R K L
W
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 20
Delay of Cascaded Inverters
An ideal step was used to derive the previous
delay equations, but this is not possible to
implement
By using putting the following circuit in SPICE, it
is possible to produce more accurate equations
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 21
Delay of Cascaded Inverters
The output of the previous circuit looks like the following
an it can be seen that the delay for the nonideal step input
is approximately twice than the ideal case:

+
(

|
|
.
|

\
| +
~

+
(

|
|
.
|

\
|
+

~
2
1
1 4 ln 2
2
1
1 4 ln 2
H
TP DD
onP PLH
L DD
TN DD
onN PHL
V
V V
C R
V V
V V
C R
t
t
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 22
Static Power Dissipation
CMOS logic is considered to have no static power
dissipation

Since the R
OFF
of the two transistors is very large,
the DC current driving a capacitive load is zero

This is not completely accurate since MOS
transistors have leakage currents associated with
the reverse-biased drain-to-substrate connections
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 23
Dynamic Power Dissipation
There are two
components that add
to dynamic power
dissipation:
1) Capacitive load
charging at a
frequency f given
by: P
D
= CV
DD
f
2) The current that
occurs during
switching which can
be seen in the figure
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 24
Power-Delay Product
f CV P
P PDP
DD av
P av
2
=
= t
The figure shows a symmetrical
inverter switching waveform
T
f
1
=
( )
5 5
5
8 . 0
2 2
8 . 0
2
2 2
DD
P
P
DD
P
P r
b f a r
CV CV
PDP
t
t t t t T
= >
= = = + + + >
t
t
t
t
The power-delay product is given as:
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 25
CMOS NOR Gate
Reference Inverter CMOS NOR gate
implementation

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 26
CMOS NOR Gate Sizing
When sizing the transistors, it is ideal to keep the
delay times the same as the reference inverter

To accomplish this, the on-resistance on the
PMOS branch of the NOR gate must be the same
as the reference inverter

For a two-input NOR gate, the (W/L)
p
must be
made twice as large
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 27
CMOS NOR Gate Body Effect
Since the bottom PMOS body contact is not
connected to its source, its threshold voltage
changes as V
SB
changes during switching

Once v
O
= V
H
is reached, the bottom PMOS is not affected
by body effect, thus the total on-resistance of the PMOS
branch is the same

However, the rise time is slowed down due to |V
TP
| being a
function of time
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 28
Two-Input NOR Gate Layout
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 29
Three-Input NOR Gate Layout
It is possible to extend this same design technique to create
multiple input NOR gates
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 30
Shorthand Notation for NMOS and
PMOS Transistors
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 31
CMOS NAND Gates
CMOS NAND gate
implementation
Reference Inverter
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 32
CMOS NAND Gates Sizing
The same rules apply for sizing the NAND gate as
the did for the NOR gate, except for now the
NMOS transistors are in series

The (W/L)
N
will be twice the size of the reference
inverters NMOS
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 33
Multi-Input CMOS NAND Gates
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 34
Complex CMOS Logic Gate Design
Example
Design a CMOS logic gate for (W/L)
p,ref
=5/1 and for (W/L)
n,ref
=2/1
that exhibits the function: Y = A + BC +BD
By inspection (knowing Y), the NMOS branch of the gate can drawn
as the following with the corresponding graph, while considering the
longest path for sizing purposes:
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 35
Complex CMOS Logic Gate Design
Example
By placing nodes in the interior of each arc, plus two more outside the
graph for V
DD
(3) and the complementary output (2), the PMOS
branch can be realized as shown on the left figure
Connect all of the nodes in the manner shown in the right figure, and
the NMOS arc that PMOS arc intersects have the same inputs
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 36
Complex CMOS Logic Gate Design
Example
From the PMOS
graph, the PMOS
branch can now be
drawn for the final
CMOS logic gate
while once again
considering the
longest PMOS path
for sizing
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 37
Complex CMOS Gate with a Bridging
Transistor Design Example
Design a CMOS gate that implements the following logic function
using the same reference inverter sizes as the previous example:
Y = AB +CE + ADE + CDB
The NMOS branch can be realized in the following manner using
bridging NMOS D to implement Y. The corresponding NMOS graph
is shown to the right.
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 38
Complex CMOS Gate with a Bridging
Transistor Design Example
By using the same technique as before, the PMOS
graph can now be drawn
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 39
Complex CMOS Gate with a Bridging
Transistor Design Example
By using the PMOS
graph the PMOS
branch can now be
realized as the
following (considering
the longest path for
sizing)

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 40
Minimum Size Gate Design and
Performance
With CMOS technology, there is a area/delay
tradeoff that needs to be considered

If minimum feature sized are used for both
devices, then the
PLH
willbedecreased
comparedtothesymmetricalreference
inverter
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 41
Minimum Size Complex Gate and
Layout
The following shows the layout of a complex minimum size
logic gate
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 42
Dynamic Domino CMOS Logic
One technique to help decrease power in MOS
logic circuits is dynamic logic
Dynamic logic uses different precharge and
evaluation phases that are controlled by a system
clock to eliminate the dc current path in single
channel logic circuits
Early MOS logic required multiphase clocks to
accomplish this, but CMOS logic can be operated
dynamically with a single clock
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 43
Dynamic Domino CMOS Logic
The figure demonstrates the basic concept of
domino CMOS logic operation
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 44
Simple Dynamic Domino Logic Circuit

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 45
Dynamic Domino CMOS Logic
It should be noted that domino CMOS circuits only
produce true logic outputs, but this problem can be
overcome by using registers that have both true and
complemented output to complete the function shown by
the following
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 46
Cascade Buffers
In some circuit, the logic must be able to drive
large capacitances (10 to 50pF)
By cascading an even number of increasing larger
inverters, it is possible to drive the loads
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 47
Cascade Buffers
The taper factor determinestheincreaseofthe
cascadedinverters size in manner shown of the
previous image.



where C
o
is the unit inverters load capacitance

The delay of the cascaded buffer is given by the following:
o
L
N
C
C
= |
o
N
o
L
B
C
C
N t t
/ 1
|
|
.
|

\
|
=
Where
o
istheunitinverters
propagationdelay
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 48
Optimum Design of Cascaded Stages
The following expressions can aid in the design of
an optimum cascaded buffer
o
o
L
Bopt
C
C
o
L
opt
o
L
opt
C
C
C
C
C
C
N
o
L
ct t
c |
|
|
.
|

\
|
=
=
|
|
.
|

\
|
=
|
|
.
|

\
|
=
|
|
.
|

\
|
ln
ln
ln
1
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 49
The CMOS Transmission Gate
The CMOS
transmission gate
(T-gate) is one of the
most useful circuits for
both analog and digital
applications
It acts as a switch that
can operate up to V
DD

and down to V
SS


Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 50
The CMOS Transmission Gate
The main consideration that needs to be
considered is the equivalent on-resistance which is
given by the following expression:
onn onp
onn onp
EQ
R R
R R
R
+
=
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 51
CMOS Latchup
There is one major downfall to the CMOS logic
gate Latchup

There are many safeguards that are done during
fabrication to suppress this, but it can still occur
under certain transient or fault conditions

Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 52
CMOS Latchup
Latchup occurs due parasitic bipolar transistors
that exist in the basic inverter as shown below
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 53
CMOS Latchup
The configuration of
these bipolar
transistors create a
positive feedback
loop, and will cause
the logic gate to
latchup as shown to
the left
By using heavily
doped material
where R
n
and R
p

exist, there
resistance will be
lowered thereby
reducing the chance
of latchup occurring
Jaeger/Blalock
10/15/03
Microelectronic Circuit Design
McGraw-Hill
Chap 7 - 54
End of Chapter 7