EE221 Lecture 29 30

Digital
Fundamentals
Tenth Edition
Floyd
Chapter 7
© 2009 Pearson Education,©Upper

2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Saddle River, NJ 07458. All Rights Reserved
Summary
Sequential Circuits
What will happen to a logic circuit if we feedback the output
back to one of the inputs?
• A=1 A Output
 Output = 0
0 ?
latch
• A = 0NOR gate keeps output
The
to Output
stay at 0, as= long
? as A = 1 1 0
1
0 0 ?1
• When A = 0, the output could be A
Output
either 0 or 1, depending upon the prior 0
state of the circuit
• The proper way to complete the truth

table  Replace ? by the word “latch”
Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Multivibrators
• A digital circuit employing feedback is called a

multivibrator.
• As the name multivibrator suggests, something is changing.
• There are three types of mutivibrators
• Astable
• Bistable
• Monostable
Summary
Multivibrators
• Astable (Not stable)
Continuously oscillates between two states.
The simplest example is that of an inverter with feedback to the input.
• Bistable (Two stable states)

The circuit is stable in either state . It can be flipped from one state to the
other by an external trigger pulse.
An example is a flip-flop. It can be used to store one bit of information.
Summary
Multivibrators
• Monostable (One stable state)
The device has one stable state, but the other state is unstable (transient).
A trigger pulse causes the circuit to enter the unstable state. After entering the
unstable state, the circuit will return to the stable state after a set time
For example if the stable state is 0 and when we apply a pulse, it comes to 1
and immediately goes back to its stable state.
The circuit is known as a on shot
1
1
Summary
Latches
A latch is a temporary storage device that has two stable
states (bistable). It is a basic form of memory.
• The S-R (Set-Reset) latch is the most basic type.
• It can be constructed from NOR gates or NAND gates.
• With NOR gates, the latch responds to active-HIGH inputs.
• With NAND gates, it responds to active-LOW inputs.
R S
Q Q
Q Q
S R
NOR Active-HIGH Latch NAND Active-LOW Latch
Summary
Latches
The
The active-HIGH
latch remainsS-R
SET,latch is in a stable
if previously SET,(latched)
and condition
when bothremains
The latch inputs are LOW.if previously RESET.
RESET,
0 R 1
0
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their 0 Latch
inactive level (0). initially
RESET
To SET the latch (Q = 1), a 0
1
Q
momentary HIGH signal is applied 0 S
to the S input while the R remains
0 R 1
0
LOW. Q
To RESET the latch (Q = 0), a Latch
momentary HIGH signal is initially
applied to the R input while the S SET
0 1
0
Q
remains LOW. 0 S
Summary
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 01 S 01
(Q = 0) and the inputs are at their Q
inactive level (1). Latch
initially
To SET the latch (Q = 1), a 1 RESET
1
0
momentary LOW signal is applied 1 R Q
to the S input while the R remains
HIGH. 1 S 1
0
Q
To RESET the latch a momentary 1
Latch
LOW is applied to the R input initially
while S is HIGH.
1 SET
0
Never apply an active set and 01R Q
reset at the same time (invalid).
Summary
Latches Truth Tables
The active-HIGH S-R latch
Inputs Outputs
Comments
S R Q Q
0 0 NC NC No Change (previous state)
1 0 1 0 SET
0 1 0 1 RESET
1 1 1 1 Invalid Condition
Summary
Latches Truth Tables
The active-LOW S-R latch
Inputs Outputs
Comments
S R Q Q
1 1 NC NC No Change (previous state)
0 1 1 0 SET
1 0 0 1 RESET
0 0 1 1 Invalid Condition
Summary
Latches The block diagrams
S Q S Q
R Q R Q
The active-HIGH S-R latch The active-LOW S-R latch
Summary
Latches Waveform Example
What is the output wave form?
Summary
Latches
The active-LOW S-R latch is available as the 74LS279A IC.
It features four internal latches with two having two S inputs.
To SET any of the latches, the S line is pulsed low.
1Q
2Q
3Q
4Q
74LS279A
Summary
Latches
A gated latch is a variation on the basic latch.
10
The gated latch has an additional S 1
Q
input, called enable (EN) that must
be HIGH in order for the latch to 1
EN
respond to the S and R inputs.
Show the Q output with 0
Q
relation to the input signals. R 1
0
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R
EN
Q
Summary
Latches Gated Latch Truth Tables
Inputs Outputs
Comments
EN S R Q Q
1 0 0 NC NC No Change (previous
state)
1 1 0 1 0 SET
1 0 1 0 1 RESET
1 1 1 1 1 Invalid Condition
0 1
X 1
X NC NC No Change (previous
state)
Summary
Latches
The D latch is a variation of the S-R latch but combines
the S and R inputs into a single D input as shown:
1
D 0 11 Q
Q D
1
EN EN
0 Q
1 Q
0
Summary
Latches
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:
0
D 1 0 Q
Q D
1
EN EN
11
Q
0 Q
1
A simple rule for the D latch is:

Q follows D when the Enable is active.
Summary
Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change
Summary
Latches D Q
EN
Determine the Q output for the
Q
D latch, given the inputs shown.
EN
Notice that the Enable is not active during these times, so

the output is latched.
Summary
Clock
Digital waveforms change between the LOW and HIGH levels.
A positive going pulse is one that goes from a normally LOW
logic level to a HIGH level and then back again.
HIGH HIGH
Rising or Falling or Falling or Rising or
leading edge trailing edge leading edge trailing edge
LOW LOW
t0 t1 t0 t1
(a) Positive–going pulse (b) Negative–going pulse
Clocks are made up of a series of pulses
Summary
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q
C C
Dynamic Q Q
input
indicator (a) Positive edge-triggered (b) Negative edge-triggered
Summary
The Edge-Triggered S-R Flip-Flop
LOW (0)
S 1 0 Q
G1 G3
CLK = LOW (0) 0
1
G2 G4
R 1 Q
LOW (0 )
Summary
This spike SETS flip-flop.
HIGH (1) 1
S 0 1 Q
G1 G3 0
1
0
1
G2 G4
R 1 0 Q
LOW (0 )
Summary
LOW (0)
S 1 1 Q
G1 G3
0
1
0
1
G2 G4
R 1 0 Q
HIGH (1 ) 0
This spike RESETS flip-flop.
Summary
Truth Tables
Inputs Outputs
Comments
S R CLK Q Q
0 0 X Q0 Q0 No Change
1 0 ↑ 1 0 SET
0 1 ↑ 0 1 RESET
1 1 ↑ ? 1 Invalid Condition
Summary

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Digital

© 2009 Pearson Education,©Upper

• The proper way to complete the truth

• A digital circuit employing feedback is called a

• Bistable (Two stable states)

0 0 NC NC No Change (previous state)

1 1 NC NC No Change (previous state)

The active-HIGH S-R latch The active-LOW S-R latch

What is the output wave form?

A simple rule for the D latch is:

Notice that the Enable is not active during these times, so

(a) Positive–going pulse (b) Negative–going pulse

Clocks are made up of a series of pulses

This spike SETS flip-flop.

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