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    A Project Review Seminar On Designe and Implimentation of Application Specific Low Power Multipliers

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    SaiKishore
    The document describes two low power multiplier architectures - selective activation multiplier and partitioned multiplier. It aims to reduce power consumption by exploiting characteristics of input data for applications like DCT and DWT. The partitioned multiplier divides multiplication into four independent parts, while the selective activation multiplier uses a Vedic mathematics technique to reduce partial products. Simulation results show the proposed architectures reduce power compared to standard multipliers. Future work includes combining these architectures with other techniques to further lower power usage.

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    A Project Review Seminar On Designe and Implimentation of Application Specific Low Power Multipliers

    Uploaded by

    SaiKishore
    21 views16 pages
    The document describes two low power multiplier architectures - selective activation multiplier and partitioned multiplier. It aims to reduce power consumption by exploiting characteristics of input data for applications like DCT and DWT. The partitioned multiplier divides multiplication into four independent parts, while the selective activation multiplier uses a Vedic mathematics technique to reduce partial products. Simulation results show the proposed architectures reduce power compared to standard multipliers. Future work includes combining these architectures with other techniques to further lower power usage.

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    Polytronics Document 2

    Original Title

    Polytronics Document 2

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    The document describes two low power multiplier architectures - selective activation multiplier and partitioned multiplier. It aims to reduce power consumption by exploiting characteristics of input data for applications like DCT and DWT. The partitioned multiplier divides multiplication into four independent parts, while the selective activation multiplier uses a Vedic mathematics technique to reduce partial products. Simulation results show the proposed architectures reduce power compared to standard multipliers. Future work includes combining these architectures with other techniques to further lower power usage.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    21 views16 pages

    A Project Review Seminar On Designe and Implimentation of Application Specific Low Power Multipliers

    Uploaded by

    SaiKishore
    The document describes two low power multiplier architectures - selective activation multiplier and partitioned multiplier. It aims to reduce power consumption by exploiting characteristics of input data for applications like DCT and DWT. The partitioned multiplier divides multiplication into four independent parts, while the selective activation multiplier uses a Vedic mathematics technique to reduce partial products. Simulation results show the proposed architectures reduce power compared to standard multipliers. Future work includes combining these architectures with other techniques to further lower power usage.

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    © All Rights Reserved
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    You are on page 1of 16

    A

    Project Review Seminar


    on
    DESIGNE AND IMPLIMENTATION OF APPLICATION
    SPECIFIC LOW POWER MULTIPLIERS
    BACHELOR OF TECHNOLOGY
    In
    ELECTRONICS AND COMMUNICATION ENGINEERING
    By
    K SAI KISHORE -13WJ1A04J8
    K RAMA RAO -13WJ1A04L3
    J NAVVENKUMAR-14WJ5A0418
    Under the Guidance of
    M SWETHA

    DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING


    GURU NANAK INSTITUIONS TECHNICAL CAMPUS
    School of Engineering and Technology 1
    2016-17
    Outline
    Objective
    ABSTRACT
    Problem Definition
    Problem Approach
    Block Diagram – Explanation
    Schematic Diagram
    Algorithm or Flow Chart – Explanation
    Results & discussion
    Conclusions
    Future Scope
    2
    Objective
    • The multipliers proposed are target
    application domains where the input data
    have specific characteristics
    • replace the multiplier with a minimum
    number of additions and shifts in order to
    decrease power dissipation
    • . The proposed architectures reduce power by
    exploiting the statistics of the input data.
    Benefits are achieved for specific applications
    3
    • Increased circuit complexity means more
    static power dissipation and may increase the
    overall power needs

    4
    ABSTRACT
    • The multipliers are mainly focusing for low power.
    • Here proposed two architectures for two inputs signed
    multipliers namely selective activation multiplier and
    partitioned multiplier.
    • The proposed technique is mainly applied in DCT and DWT
    Application.
    • Power is reduced. The proposed multiplier is applied to all low
    power techniques with moderate area and time overhead.

    5
    Problem Definition
    • present a multiplier architecture which utilizes
    the dynamic operand interchange technique.
    • That technique has more no of partitioned
    multipliers and uses more power

    6
    Problem Approach

    • To reduce number of partial products we use


    some vedic mathematic technique called
    "urdva triyanka sutram” to reduce partial
    products
    • By that technique we designed an
    architectures namely partitioned
    multiplication and selective activation

    7
    Block Diagram – Explanation

    • Partitioned multiplier architecture

    8
    • the multiplication is divided into four
    independent multiplications which compute
    four products p22, p21, p12, and p11
    • the architecture provides two paths, one for
    small-number and one for large-number
    multiplications
    • Then the urdva triyanka sutram executes

    9
    Algorithm(urdva triyanka srutram)
    • In English it is called as Vertically and
    Crosswise

    10
    • Process: (Left –> Right)
    • Vertical Multiplication of 1st digits of the
    numbers.
    • Crosswise Multiplication Addition (i.e.
    Crosswise Multiplication and adding them).
    • Vertical Multiplication of last digits of the
    numbers.

    11
    • For all steps, except 1st step, each step
    (compartment) needs to have ONLY 1 digits. If
    not then carry forward initial digits to previous
    compartment (Check below examples to
    understand).

    12
    • For 3 digits

    13
    Results
    • Extensive power consumption simulations
    show that by taking advantage of the
    characteristics of the input data and the
    processing algorithm
    • architectures reduce power consumption

    14
    Future Scope
    • The proposed architectures can be combined
    with other techniques in both the internal
    architecture and the algorithmic level to
    further reduce power consumption

    15
    • What is the difference between block diagram
    & Schematic Diagram?
    • Add date..

    16

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