04 - Generation of Control Signals & Address Decoding

Generation of Control Signal &
Memory Interfacing
Generation of Control Signal
 The Control signals required are RD and
WR, but in any microprocessor based
system, we will find memory devices as well
as I/O devices.
 Hence, the control signals required are

MEMR, MEMW, IOR and IOW and normally
used to distinguish between memory and
I/O devices. These signals can be generated
by using 3:8 decoder 74LS138 as shown in
figure below:
Typical 8085 System
Configuration
 The typical 8085 system can be designed
using decoder (74LS138) to generate
different control signals, latch 74LS373 to de-
multiplexed address/data bus i.e separate
address and data bus.
 The device 72LS245 Octal Transceiver is

optional but in buffered system is required.
 The typical 8085 based system configuration

is shown in figure below:
The Overall Picture
Address Decoding Techniques
 As we know, 8085 has 16 address lines using which
allows addressing up to 64 KB of main memory.
 Most of the time we do not need complete 64KB
memory, so most of the address lines will remain
free which can be used generate chip select and
determine the range of the addresses the memory
will occupy.
 There are two types of decoding technique
depending on the number of lines used for the
decoder.
◦ Full or absolute decoding
◦ Partial decoding
 In full decoding, all remaining address lines are used
for the decoder to generate chip select signal for the
memories as shown in figure below:
Address Decoding Techniques
 For example, suppose we want to interface 8k of
memory, then thirteen address lines are required
for the memory.
 Then remaining three address lines can be used
for decoder, so more hardware is required for
decoding the numbers of address bits.
 But in partial decoding, only one line out of
remaining address lines is used to generate chip
select signal as shown in figure below:
 For above example, out of remaining three
address lines, we can use any one of them as chip
select signal and rest of the address lines will
remain open or unconnected, so less hardware is
required for decoding.
INTERFACING TECHNIQUES
 There are two method of interfacing
memory or I/O devices with the
microprocessor are as follows:
a) I/O mapped I/O
b) Memory mapped I/O
I/O MAPPED I/O
 In this technique, I/O device is treated as a I/O device and memory
as memory.
 Each I/O device uses eight address lines.
 If eight address lines are used to generate the address of the I/O
port, then 256 input/output devices can be interfaced with the
microprocessor.
 The address bus of the 8085 microprocessor is 16 bit, so we can
either use lower order address lines i.e. A0 – A7 or higher order
address lines i.e. A8 – A15 to address I/O devices where the
address available on A0 – A7 will be copied on the address lines A8
– A15 .
 In I/O mapped I/O, the complete 64 Kbytes of memory can be
interfaced with the microprocessor as all address lines can be used
to address memory locations as the address space is not shared
among I/O devices and memory.
 In this type,. the data transfer is possible between accumulator A
register and I/O devices only
 Address decoding is simple, as less hardware is required.
 The separate control signals are used to access I/O devices and
memory such as IOR, IOW for I/O port and MEMR,
I/O MAPPED I/O
 MEMW for memory hence memory location
are protected from the I/O access.
 But in this type, arithmetic and logical
operation are not possible directly.
The figure below shows interfacing I/O devices
in I/O mapped I/O.
MEMORY MAPPED I/O
 In this technique, I/O devices are treated as memory
and memory as memory, hence the address of the I/O
devices are as same as that of memory i.e. 16 bit for
8085 microprocessor.
 So, the address space of the memory i.e. 64 Kbytes
will be shared by the I/O devices as well as by
memory.
 All 16 address lines i.e. A0-A15 is used to address
memory locations as well as I/O devices.
 The control signals MEMR and MEMW are used to
access memory devices as well as I/O devices.
 The data transfer is possible between any register of
the microprocessor and I/O device or memory
device.
 Hence, all memory related instructions can be used to
access I/O devices as they are treated as memory
devices.
MEMORY MAPPED I/O
 Address decoding of the I/O devices and memory devices
are complicated and expensive as more hardware is
required.
 The 8085 microprocessor can access either 64 K I/O ports
or memory locations, hence the total numbers of the I/O
ports and memory locations should not be greater than 64
K.
 I/O devices and memory locations are distinguished by the
addresses only.
 Arithmetic and logical operation can be performed directly
on the I/O devices.
 Most of the memory instructions are long; hence it reduces
the speed of I/O.
 Normally, the speed of the I/O devices are very slow, hence
the common interface used in memory mapped I/O will
reduce the speed of memory access unnecessarily.
Difference Between Memory Mapped
I/O And I/O Mapped I/O

04 - Generation of Control Signals & Address Decoding

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What are the different types of control signals that can be generated?

What are the two main techniques for interfacing memory and I/O devices with a microprocessor?

Generation of Control Signal &

 Hence, the control signals required are

 The device 72LS245 Octal Transceiver is

 The typical 8085 based system configuration

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