Scribd Logo
Upload

Welcome to Scribd!

  • 36 views

    Fpga Implementation of Ddr3 Sdram Memory Controller: N.V.Apparao

    Uploaded by

    apparao_nandam7352
    This document discusses the design of a DDR3 SDRAM memory controller using an FPGA. It begins with an introduction on the need for memory controllers and an overview of DDR SDRAM. The objective is then stated as designing a high-speed, low-power DDR3 SDRAM memory controller compatible with AXI bus. The existing DDR1 system and its limitations are described. The proposed DDR3 system provides improvements like higher data rates, lower voltages, and compatibility with AXI bus. Finally, the document outlines the plan of action and lists references used.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Fpga Implementation of Ddr3 Sdram Memory Controller: N.V.Apparao

    Uploaded by

    apparao_nandam7352
    36 views14 pages
    This document discusses the design of a DDR3 SDRAM memory controller using an FPGA. It begins with an introduction on the need for memory controllers and an overview of DDR SDRAM. The objective is then stated as designing a high-speed, low-power DDR3 SDRAM memory controller compatible with AXI bus. The existing DDR1 system and its limitations are described. The proposed DDR3 system provides improvements like higher data rates, lower voltages, and compatibility with AXI bus. Finally, the document outlines the plan of action and lists references used.

    Original Description:

    ddr3ppt

    Original Title

    ddr3vvvv

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document discusses the design of a DDR3 SDRAM memory controller using an FPGA. It begins with an introduction on the need for memory controllers and an overview of DDR SDRAM. The objective is then stated as designing a high-speed, low-power DDR3 SDRAM memory controller compatible with AXI bus. The existing DDR1 system and its limitations are described. The proposed DDR3 system provides improvements like higher data rates, lower voltages, and compatibility with AXI bus. Finally, the document outlines the plan of action and lists references used.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    36 views14 pages

    Fpga Implementation of Ddr3 Sdram Memory Controller: N.V.Apparao

    Uploaded by

    apparao_nandam7352
    This document discusses the design of a DDR3 SDRAM memory controller using an FPGA. It begins with an introduction on the need for memory controllers and an overview of DDR SDRAM. The objective is then stated as designing a high-speed, low-power DDR3 SDRAM memory controller compatible with AXI bus. The existing DDR1 system and its limitations are described. The proposed DDR3 system provides improvements like higher data rates, lower voltages, and compatibility with AXI bus. Finally, the document outlines the plan of action and lists references used.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 14

    FPGA Implementation of DDR3

    SDRAM Memory Controller


    By
    N.V.AppaRao
    12481D5519
    E.S

    Under the Guidance of


    V.NarasimhaRao
    Assistant Professor
    Contents
    •Introduction
    •Objective

    •Existing System
    •Limitations in existing model
    •Proposed system
    •Plan of Action
    •References
    Introduction
    •Need of memory controller is to maintain speed
    synchronization between RAM(memory) and
    microprocessor/microcontroller

    •Double Data Rate (DDR) SDRAM memory Controller


    that is located between the DDR SDRAM memory and
    Bus Master.

    •The Memory Controller provides command signals for


    memory refresh, read and write operation and
    initialization of SDRAM.
    Objective
    To design high speed and low power DDR3

    SDRAM memory controller compatible with

    AXI(advance extensible interface) bus, flexible

    to connect other interfacing devices.


    Existing System
    DDR
    system
    system
    interface
    interface

    DDR/DDR1
    DDR
    Bus master SDRAM
    SDRAM
    controller

    DDR SDRAM CONTROLLER SYSTEM

    5
    Contd..
    DDR/DDR1 SDRAM controller with write
    and read operations are performed at
    same clock pulse, DDR transfers data on
    both the rising and falling edges of the
    clock

    This will increase the speed of operation


    in the memory.

    6
    Limitations in Existing Model(DDR1)

    DDR1 SDRAM doubles the data rate of

    SDRAM without changing clock speed or

    frequency (200-400Mbps) (less)

    2-bit Prefetch architecture(less)

    CAS latency is 15ns (more)

    Operating voltage 2.5+/- 0.2 V(more)


    Proposed System(DDR3)
    DDR3 provides two burst modes for both reading and
    writing: burst chop (BC4) and burst length eight (BL8)

    BL8 allows transfer of 64-bit data packets (eight) to or


    from consecutive addresses in memory, which means
    addressing occurs once for every eight data packets
    sent

    BC4 allows bursts of four, which creates smooth


    transitioning if switching from DDR2 to DDR3 memory

     Improved memory latency, operate at low voltages

    8
    Contd…
    For attaining the maximum throughput
    from the memory, it operates all the
    memory banks in parallel and minimizes
    the effect of precharge/refresh and other
    DDR3 internal operations

    9
    Contd..
    And also the DDR3 memory controller is
    comparing with DDR1, and DDR2 memory in
    performance wise.
    Another modification make to this DDR3
    memory controller is for faster memory access
    to the high interfacing devices, designing the
    memory controller compatible with AXI
    (advance extensible interface) Bus.
    This AXI Bus with memory controller uses in
    advance microcontroller interfacing devices.

    10
    Plan of Action
    S.NO ACTIVITY WEEKS(40)

    1 Selection of topic 1
    2 Problem identification 2
    3 Literature survey 4
    4 Selection of base paper for the 2
    identified problem
    5 Study and implementation of 5
    base paper
    6 Identification of important 8
    parameters
    7 Consideration of the base paper 10
    algorithm for improve the
    performance/ results
    8 Paper publication work 6
    9 Project documentation work 2

    11
    References
    1. DDR SDRAM Controller white paper, Lattice Semiconductor
    Corporation, Reference Design: RD1020, April 2004.

    2. SDR SDRAM Controller white paper, Lattice Semiconductor


    Corporation, Reference Design: RD1010, April 2011.

    3. Chen Shuang-yan, Wang Dong-hui, Shan Rui Hou Chao, “An


    Innovative design of DDR/DDR2 SDRAM Compatible Controller”,
    ASICON International Conference, pp 62-66 24th Oct 2005.

    4. Micron Technology, Micron’s Synchronous DRAM (2002).

    5. www.xilinx.com.

    6. Verilog HDL: A guide to Digital Design and Synthesis by Samir


    Palnitkar
    THANK YOU

    13
    14

    You might also like

    pFad - Phonifier reborn

    Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

    Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


    Alternative Proxies:

    Alternative Proxy

    pFad Proxy

    pFad v3 Proxy

    pFad v4 Proxy