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ABSTRACT: DDR3 SDRAM is a memory interface technology which is of random-access memory used
to store data of a computer or any other electronic device in high-bandwidth storage. DDR3 is a type of
DRAM that belongs to the SDRAM class of technology. The DDR3 Memory Controller is the 3rd gen of
DDR memory controllers, and it provides superior efficiency while using less power. Due to a greater clock
speed and reduced power consumption, the DDR3 Memory Controller provides a higher density and
bandwidth than prior generations of DDR1/2 SDRAM. The DDR3 memory controller's design includes the
Initializing the FSM, bank control, data route, clock counter, refresh counter, Address FIFO, , write data
FIFO, command FIFO, and Read data reg. An improved DDR3 memory controller design will be created
in this project. Verilog is used to create the design, and System Verilog OVM is used to verify it.

OBJECTIVES: The primary goal of this project is to create a DDR3 memory controller that is of high-
speed and high-efficiency and also consists of significant advantages over DDR2. These devices use less
power, run at faster speeds, provide better performance (2x the bandwidth), and have higher density. DDR3
devices utilize 30% less power than DDR2 devices, which is considered to be one of the most significant
differences between the two
.
INTRODUCTION: DDR3 Memory controller employs a memory technology in order to achieve high-
bandwidth for storing a computer's or other digital device's working data. The capacity to send I/O data at
a faster rate is DDR3's main advantage. When compared to the memory bits it contains, it has a 8 fold data
rate, resulting in greater bus and peak rates. Moreover, there seems to be no comparable drop in latencies,
that is consequently more inconvenient. DDR3 memory technology also provides chips with sizes ranging
from 512 MB to 8 GB, essentially enabling for a 16 GB memory module. In terms of architecture and
operation, DDR3 SDRAM is similar to prior DDR memory. DDR3 SDRAM is, in fact, the third generation
of DDR SDRAM principles. Because data prefetch was shifted from the data memory system to I/O buffers,
DDR3 memory speeds may be increased beyond those of DDR2DDR3 memory controller uses an 8-bit
prefetch, commonly known as 8n-prefetch, while DDR2 uses 4-bit samples. DDR3 memory
controller's technology doubles the inbuilt bus width between the Dynamic random-access memory
(DRAM) core and the I/O buffers. As a result, the greater data transfer rate of DDR3 SDRAM does not
necessitate quicker memory core operation. However, external or additional buffers begin to work more
quickly. The memory chips' core frequency looks to be eight times lower than the external memory bus and
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DDR3 buffers. However, the method described above has a drawback: it increases memory latencies while
boosting memory bandwidth. Therefore, despite the fact that DDR3 SDRAM operates at higher frequencies
than DDR2, we cannot expect it to outperform DDR2 SDRAM. There are a few more benefits to DDR3
SDRAM that will persuade manufacturers and end users to convert to the new technology.

PROPOSED WORK: DDR3 memory controller employs a dual data rate design in order to accomplish
operations with a better speed. An 8n prefetch architecture having I/O pins capable of transporting two data
words per clock cycle is used in the double data rate design. DDR3 has a very high signaling rate, and for
this to work reliably, it has added complexity such as, Read/write levelling and ZQ calibration which helps
in aligning the inputs and output with respect to the differential clock. DDR3 also consists of various
features for improving its performance like activate, pre-charge, self-refresh and refresh operations. Main
aim of the project is to implement all these features and successfully exercise them on the Xilinx Artix7
FPGA board at much lower speeds as in normal operating mode (DLL-on mode), DDR3 has a minimum
clock frequency (300MHz+). However, it is possible to turn the DDR3 DLL off (in most DRAM parts) and
run at frequencies <= 125MHz. DLL-off mode (which this memory controller utilizes) is listed as an
optional feature for DDR3 parts to implement can be accessed using its mode registers. The idea with this
project is to run DDR3 at a much slower clock frequency than the maximum supported by the DDR part,
reducing the complexity required in the DDR3 controller by giving the bus interface much more margin
and tolerance.

SUMMARY AND CONCLUSION: Verilog and System Verilog HVL are used to create and verify a fully
functional DDR3 Memory controller. The memory operates at twice the frequency of the CPU, without
impacting the system's performance, and so the data bus size is lowered. The DDR3 memory controller's
main flaw is its complicated schematic, which includes a significant number of buffers. This increases the
delay. The controller generates a variety of timing and control signals that coordinate the operation's time
and control flow. The memory system runs at twice the processor's frequency without compromising
performance. As a result, the size of the data bus can be reduced. The complexity of the controller's
schematic, which includes a large number of buffers, increases the amount of delay. Through double
pumping, DDR3 SDRAM provides almost double the bandwidth of DDR2 SDRAM without increasing the
clock frequency. DDR3 SDRAM's voltage was reduced from 2.5V to 1.5V when compared to
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DDRSDRAM. This reduces power consumption and heat output while also allowing for more dense
memory layouts for increased capacity and Improved thermal design and low-power capabilities (cooler).
Increased bandwidth performance, which is now almost around 2,400 MHz. DDR memory controller
(DDR3 SDRAM) is a more expensive option than DDR3 memory controller, therefore most chipset makers
no longer support it.

PROPOSED SCHEDULE:
Duration Objectives to be completed
03/2022 (March) - 04/2022 (April) Exploring and studying the DDR3 memory controller
specification
05/2022 (May) - 06/2022 (June) Implementing the RTL code for DDR3 and synthesis.

07/2022 (July) - 0/9 2022 (September) Implementation of synthesized code on the Artix-7
FPGA board for testing the features
10/2022 (October) -12/2022 (December) Final performance analysis and report

REFERENCES:
[1] Mrs. Komala M, “Design and Implementation of High Performance DDR3 SDRAM controller”,
International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181) Vol. 4 Issue 05,
May-2015
[2] T. Mladenov, “Bandwidth, Area Efficient and Target Device Independent DDR SDRAM
Controller”,Proceedings of World Academy of Science, Engineering and Technology, Vol. 18, De. 2006,pp.
102-106.
[3] DDR3 SDRAM Specification (JESD79-3A), JEDEC Standard, JEDEC Solid State Technology
Association, Sept. 2007.
[4] www.altera.com/literature/ug/ug_altmemphy.pdf, External DDR Memory PHY Interface Mega
function User Guide (ALTMEMPHY) accessed on 23 Feb