Chapter 2 Data Manipulation
Chapter 2 Data Manipulation
Chapter 2 Data Manipulation
Data Manipulation
Chapter 2: Data Manipulation
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Introduction
Memory
operation Peripheral
control
Memory
Operation peri
CPU controller
pher
Control
al
Computer Architecture
• Central Processing Unit (CPU) or processor
that controls the manipulation of data.
– Arithmetic/Logic unit: performs operations on
data (such as addition and subtraction)
– Control unit: coordinating the machine’s activities
– Registers unit: used for temporary storage of
information within the CPU
• General purpose
• Special purpose
• Bus: CPU and main memory are connected by a
collection of wires
• Motherboard: machine’s main circuit board
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Motherboard
CPU Socket
Main
Memory
slot
Figure 2.1 CPU and main memory connected
via a bus
0 读写控制电路
CS 存储器
存储器读命令
CPU 控制线
0 读写控制电路
CS 存储器
存储器写命令
CPU 控制线
CPU 通过地址线发出地址,并把数据放到数据线上;
由地址译码电路对地址线进行“翻译” ,“ 选中”某一单元
;发出存储器写命令; 把数据线信息送入选中的存储单元。
CPU
Figure 2.2 Adding values stored in memory
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Summary: System architecture
AB Bus
C I/O peripheral
Memory Memory
controller
P
U
DB BUS
CB BUS
Stored Program Concept
A program can be encoded as bit patterns and
stored in main memory, just like data.
compile
source
object
link upload
Executable
code
execution
Other program
library
Terminology
• Machine language: To apply the
stored-program concept, CPUs are
designed to recognize instructions
encoded as bit patterns. This
collection of instructions along with
the encoding system is Machine
language
• Machine instruction: An instruction
expressed in this language is called a
machine-level instruction
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Machine Language Philosophies
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Figure 2.2 Adding values stored in memory
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Figure 2.3 Dividing values stored in memory
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Figure 2.4 The architecture of the machine
described in Appendix C
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Figure 2.5 The composition of an
instruction for the machine in Appendix C
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Figure 2.6 Decoding the instruction 35A7
STORE the bit pattern found in register 5 in the memory cell whose
address is A7 0-26
Program execution
• A computer follows a program stored in its
memory by copying the instructions from
memory into the CPU as needed. Once in
the CPU, each instruction is decoded and
obeyed.
• The order in which the instructions are
fetched from memory corresponds to the
order in which the instructions are stored
in memory unless otherwise altered by a
JUMP instruction.
Program Execution
• Controlled by two special-purpose registers
– Program counter: address of next instruction
– Instruction register: current instruction
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Figure 2.8 The machine cycle
Machine Cycle:
three steps
Fetch
Decode
Execute
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Figure 2.10 The program from Figure 2.2 stored
in main memory ready for execution
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Figure 2.11 Performing the fetch step of
the machine cycle
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Figure 2.11 Performing the fetch step of
the machine cycle (cont’d)
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Figure 2.7 An encoded version of the
instructions in Figure 2.2
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Arithmetic/Logic Operations
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Communicating with Other Devices
AB Bus
C I/O Peripheral
Memory Memory Device
controller
P
U
DB BUS
CB BUS
Communicating with Other Devices
• Controller: An intermediary apparatus that
handles communication between the computer
and a peripheral device
– Specialized controllers for each type of
device ( purchasing a new peripheral device often
required the purchase of a new controller as well. )
– General purpose controllers (USB and
FireWire): by which a single controller is able to
handle a variety of devices
• Port: The point at which a device connects to a
computer
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Figure 2.13 Controllers attached to a
machine’s bus
With this
arrangement, the
CPU is able to
communicate with
the controllers
attached to the bus
in the same manner
that it communicates
with main memory.
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Communicating with Other Devices
(continued)
• Communication between
computing devices is handled over
two types of paths:
• Parallel Communication:
Several communication paths
transfer bits simultaneously.
• Serial Communication: Bits
are transferred one after the
other over a single
communication path.
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Other architecture
• The Multi-Core CPU
• Today’s state of the art allows for more than one
entire CPU to be placed on a single chip. This is the
underlying architecture of devices known as multi-
core CPUs,
• Multi-core CPUs containing two processing units
are typically called dual-core CPUs.
Conclusion
C I/O Peripheral
Memory Memory Device
controller
P
U
DB BUS
CB BUS
Thank you !