CHIP DESIGN TECHNOLOGIES

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CHIP DESIGN TECHNOLOGIES

Offers Value Added Solutions

VLSI TECHNOLOGY
EMBEDDED TECHNOLOGY
VLSI DESIGN TECHNOLOGY

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 Building Blocks of a Technology
 Area
 Components
 Power
 Heat
 Speed
 Efficiency
 Memory
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 Processor
Maintenance
Cost
Functionality
Flexibility
Portability
Rigidity
Dependability / faithful

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 History of VLSI
1948 TRANSISTOR INVENTED (SHOCKLEY AT&T)

1956 TRANSISTOR COMPUTER (CRAY)

1958 FIRST MONOLITHIC CIRCUIT (IC)

1960 SSI (< 100 TRANSISTORS) MOSFET - PMOS, METAL GATE (BELL
LABS)

1961 TTL (PACIFIC MICROTEL) - 25UM FEATURE SIZE

1962 ECL (MOTOROLA)

1964 OPAMP (WILDAR - FAIRCHILD U709)

1966 MSI (100 - 1000 TRANSISTORS)

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 1967 FIRST PRODUCTION OF MOS CHIPS

1969 LSI (1000 - 10000 TRANSISTORS) PMOS, NMOS, CMOS ( E-BEAM

PRODUCTION, DIGITAL WATCHES, CALCULATORS)

1971 ION IMPLANTATION

1972 I2L (IBM), 16 BIT MICROS

1975 VLSI (10,000 - 100,000 TRANSISTORS)

1980’s (> 100,000 TRANSISTORS)

(ASICS , PLD, TRENCH CAPS,DUAL WELL, BIMOS, HVICS FEATURE
SIZE 2UM )

1990’s > 1,000,000 TRANSISTORS

64-bit MICROS, MICROMACHINING, FPGA SYNTHESIS, VHDL,
FEATURE SIZE 0.5UM

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 Digital Logic Families
RTL, DTL, and TTL
ECL
MOS
CMOS (Complementary Metal
Oxide Semiconductors)
FET Family
High packing Density
Low power Consumption
Low Noise Margin

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 About VLSI / Technology
Standardized Technology

Entry For The Elite Group - Electronics Related

Engineers Only

India becoming HUB For Designing Chips

Qualification:

B.E / M.E – ECE , EEE, CSE, IT, E&I,

VLSI, APPL Electronics.

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 Introduction to VLSI
Non standardized HDLs
ALTERA
AHPL
ABEL
TI-HDL

IEEE standardized Languages

VHDL
Verilog HDL

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 VHDL
Very High Speed Integrated
Circuit Hardware Description
Language

In 1981 by DOD
In 1987 by IEEE & ANSI (Version 1076)
In 1993 by IEEE (Version 1164)

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 Verilog

In 1983 by GDA
In 1995 by IEEE (Version 1364)
In 2001 by IEEE (New Version)

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 Technology summary
Year Unit 1993 1995 1998 2001 2004 2007 2010 2013
Feature Size  microns 0.50 0.35 0.25 0.18 0.13 0.10 0.07 0.05

Internal Clock  Mhz/GHz 200 300 450 600 800 1 1.1 1.2
(high performance)

Logic transistors million/c 2 4 7 13 25 50 90 150

m2
Microprocessor million 5.2 12 28 64 150 350 800  
transistor
s/chip
DRAM size Mbit/Gbit 16 64 256 1 4 16 64 256

SRAM size Mbit/Gbit 1 4 16 64 256 1 4 8

Voltage Vdd 5 3.3 2.5 1.8 1.5 1.2 0.9 0.9

Source : Semiconductors Industry Association release 1994

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 Year Unit 1993 1995 1998 2000 2003 2007 2010 2013

Feature Size Microns / 0.50 0.35 0.25 0.18 0.13 0.10 0.07 0.05
nm
Internal Clock   Mhz/Ghz 200 300 750 1 1.5      
(high
performance)
Logic million/c 2 4 7 13 25 50 90 150
transistors  m2
Microprocesso million 5.2 12 4? ? 18 350 800  
r transistor
s/chip
DRAM size  Mbit/Gbit 16 64 256 1 4 16 64 256

SRAM size Mbit/Gbit 1 4 16 64 256 1 4 8

Voltage Vdd 5 3.3 2.5 1.8 1.5 1.2 0.9 0.9

Source : Semiconductors Industry Association release 1997

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 Year Unit 1993 1995 1999 2001 2003 2005 2008 2011 2014 2016

Feature Size Microns 0.50 0.35 180 130 100 80 70 50 34 22

/nm
Internal Clock   Mhz/Ghz 200 300 750 1.68 2.31 5.17 6.74 11.5 19.3 28.7
(high
performance)

Logic transistors  million/cm2 2 4 6.6 13 24 44 109 269 664  

Microprocessor million 5.2 12 23.8 47.6 95.2  190 539 1523 4308  
transistors/
chip
DRAM size  Mbit/Gbit 16 64 256 512  1 2 6 16 48  

SRAM size Mbit/Gbit 1 4 16 64 256          

Voltage Vdd 5 3.3 2.5 1.2 1.0 0.9 0.7 0.6 0.5 0.4 

Source : Semiconductors Industry Association release 2000/2001

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 Design Flow
VLS
I

VHD VERILO
L G

FPG
A

ASIC
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 Design Flow
Specification
Specification
VLSI
Language
HDL Coding
VHDL VERILOG
Coding
Simulation
FPGA Compilation
Synthesis
ASIC
Debugging
Floor Plan
Implementation
Place &
Route VLSI
VLSI Software
Software
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 Design Flow
Specification

Functional
HDL coding Simulation

Timing, power
Synthesis & Gate-level
Simulation

Floor planning

Placement Verification
& Routing &Testing

Chip Post-Silicon
Manufacturing Validation

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 Structure of VHDL design
Entity :
External view of a design unit

HALF ADDER INPUT1 HALF ADDER SUM

HALF ADDER

HALF ADDER INPUT2 HALF ADDER CARRY

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 Architecture :
Internal view of a design unit

HALF ADDER INPUT1

HALF ADDER SUM
XOR

HALF ADDER CARRY

HALF ADDER INPUT2 AND

HALF ADDER

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 Inside Architecture :

Declaration – To declare internal

connections
Process –Behavioral operations
Assignment –Data flow operations
Component –Structural operations

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 Test bench or Stimulus :
To test the output by the
given stimulating values

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 Structure of Verilog design
Modules :
External view of a design unit
Initial / Always :
Syntax to behavioral architecture
Assignment :
Data flow operation

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 Test bench :

To test the output by the given

stimulating values

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 Modeling
Structural:
Describes how the components are
Interconnected to perform a certain function
Data flow:
Describes the design in concurrent way
Behavioral:
Describes how a particular design should
respond to a given set of Inputs
Switch level: (only applicable for verilog)
A module can be implemented in terms of
switches,storage nodes and the
interconnection between them

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 Half adder design-VHDL
Syntax: Library name
library IEEE;
use IEEE.std_logic_1164.all; Design unit name
entity ha is
port(ha_ip:in STD_LOGIC_VECTOR(1 downto 0);
ha_ops:out STD_LOGIC;
Port declaration
ha_opc:out STD_LOGIC);
end ha; Architecture name
architecture ha_arch of ha is
begin Building design
ha_ops <= ha_ip(0) xor ha_ip(1); unit
ha_opc <= ha_ip(0) and ha_ip(1);
end ha_arch;

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 Half adder design-Verilog
Design unit name
Syntax:
module half_adder (a,b,carry,sum);
input a,b;
Port list
output carry,sum;
assign carry = (a & b); Port declarations
assign sum = (a ^ b);
endmodule Building design
unit

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 Synthesis
Synthesis uses the functionally
verified code.
Process which converts the HDL/
Schematic/ State machines into a
appropriate Hardware elements
The resulting Hardware depends
upon the Constraints which is
specified during the synthesis
process.
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 Simulation result of a
Half Adder

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 Synthesis Result
RTL View

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 Verification

Verification is a process of testing

the functionality of the design after
synthesis
Verification was done at all levels
from behavioral Domain to the
Physical domain

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 Floor Planning
Floorplanning is the task of Placing different
blocks in the chip so as to fit in the minimum
possible area with minimum empty space.

The Goal of the floorplanner is to minimize the die

size,Maximize routability and optimize pin location
Minimize the chip area
Minimize the delay

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 Example of Floorplanning
C E
C F
A D
B
E G B
D A
F G

Physical View of the Physical View of the

Chip Before FloorPlan Chip After FloorPlan
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 Placement and it’s objectives
After completing floor plan, placements of
logic cells are done within the flexible
blocks on a chip
Placement is a task of placing the Logical
blocks to the adjacent block to minimize
the area of the Chip size.
Number of pins and I/O pads were
calculated
Guarantee the router can complete the
routing step
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 Minimize all the critical net delays
Make the chip as dense as possible
Minimize power dissipation
Minimize cross talk between signals
Minimize the total estimated
interconnect length
Meet the timing requirements for critical
nets
Minimize the interconnect congestion

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 ROUTING

Routing is task of connecting the logical

blocks with the wires
The two types of routing are
Global routing
Detailed routing
Global routing is to provide complete
instructions to the detailed router on
where to route every net.
Detailed routing is to complete all the
connections between logic cells.

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Example of Placement & routing

A E A C E

F D
C B I
F
B J
H J
G
H I D G

Before Place & Route After Placement & routing

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 What Company Expects?
Eligibility:
Compulsory High end Training in
VHDL
VERILOG HDL
FPGA
ASIC

Qualification:

B.E / M.E – ECE , EEE, CSE, IT, E&I,

VLSI, APPL Electronics.

Note: Final years, Pre-Final years also Eligible for Training

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 Placement Opportunities
L&T InfoTech
HCL
Wipro
LSI Logic
Intel
ATI
Synplicity
GDA Technologies
CG-CorEl
Analog Devices
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 AMD
Tektronix
Alliance Semiconductors
Cadence
Zilog
Mentor Graphics
GE Electronics
National Semiconductors
Texas Instruments
Sanyo
Sasken

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 Scale Of Pay
Very High Take Home Salary
Beginners:
Indian Majors / MNC – INR 25 K / m (approx)

Very High Career Growth Achievable than any other

Technology

Unexplored , Plenty of Opportunities

Immediate Job Opportunities

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 CHIP DESIGN TECHNOLOGIES
Offers Value Added Solutions

Contact No: 94442 41023

Email ID: Zylinks@rediffmail.com

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